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Differential D72185

AMDGPU: Partially merge indirect register write handling
ClosedPublic

Authored by arsenm on Jan 3 2020, 2:43 PM.

Details

Reviewers
nhaehnle
mareko
rampitec
Summary

a785209bc2fb switched to using a pseudos instead of manually tying
operands on the regular instruction. The VGPR indexing mode path
should have the same problems that change attempted to avoid, so these
should use the same strategy.




Use a single pseudo for the VGPR indexing mode and movreld paths, and

expand it based on the subtarget later. These have essentially the

same constraints, reading the index from m0.






Switch from using an offset to the subregister index directly, instead

of computing an offset and re-adding it back. Also add missing pseudos

for existing register class sizes.
Diff Detail
Event Timeline
arsenm created this revision.Jan 3 2020, 2:43 PM
Herald added a project: Restricted Project.  ·  View Herald TranscriptJan 3 2020, 2:43 PM
Herald added subscribers: hiraditya, t-tye, tpr and 5 others.  ·  View Herald Transcript
arsenm added a child revision: D72187: AMDGPU: Prepare to use scalar register indexing.Jan 3 2020, 3:19 PM
arsenm added a comment.Jan 20 2020, 4:36 AM
ping
Herald added a subscriber: kerbowa.  ·  View Herald TranscriptJan 20 2020, 4:36 AM
rampitec added a comment.Jan 20 2020, 11:31 AM
The change seems to miss parent revision introducing V_INDIRECT_REG_WRITE_*.
arsenm added a comment.Jan 20 2020, 12:43 PM


In D72185#1830007, @rampitec wrote:


The change seems to miss parent revision introducing V_INDIRECT_REG_WRITE_*.





It's introduced /renamed here
rampitec accepted this revision.Jan 20 2020, 12:48 PM
LGTM
This revision is now accepted and ready to land.Jan 20 2020, 12:48 PM
arsenm closed this revision.Jan 20 2020, 2:25 PM
8615eeb455618fabe962f6951ccd8fe95b26bb15
Revision Contents
PathSize
llvm/
lib/
Target/
AMDGPU/
67 lines
37 lines
27 lines
Diff 236133
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,456 Lines • ▼ Show 20 Lines    BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)

      .addReg(SrcReg, RegState::Implicit);
      .addReg(SrcReg, RegState::Implicit);

  }
  }




  MI.eraseFromParent();
  MI.eraseFromParent();




  return LoopBB;
  return LoopBB;

}
}




static unsigned getMOVRELDPseudo(const SIRegisterInfo &TRI,
static unsigned getIndirectRegWritePseudo(const SIRegisterInfo &TRI,

                                 const TargetRegisterClass *VecRC) {
                                 const TargetRegisterClass *VecRC) {

  switch (TRI.getRegSizeInBits(*VecRC)) {
  switch (TRI.getRegSizeInBits(*VecRC)) {

  case 32: // 4 bytes
  case 32: // 4 bytes

    return AMDGPU::V_MOVRELD_B32_V1;
    return AMDGPU::V_INDIRECT_REG_WRITE_B32_V1;

  case 64: // 8 bytes
  case 64: // 8 bytes

    return AMDGPU::V_MOVRELD_B32_V2;
    return AMDGPU::V_INDIRECT_REG_WRITE_B32_V2;

  case 96: // 12 bytes

    return AMDGPU::V_INDIRECT_REG_WRITE_B32_V3;

  case 128: // 16 bytes
  case 128: // 16 bytes

    return AMDGPU::V_MOVRELD_B32_V4;
    return AMDGPU::V_INDIRECT_REG_WRITE_B32_V4;

  case 160: // 20 bytes

    return AMDGPU::V_INDIRECT_REG_WRITE_B32_V5;

  case 256: // 32 bytes
  case 256: // 32 bytes

    return AMDGPU::V_MOVRELD_B32_V8;
    return AMDGPU::V_INDIRECT_REG_WRITE_B32_V8;

  case 512: // 64 bytes
  case 512: // 64 bytes

    return AMDGPU::V_MOVRELD_B32_V16;
    return AMDGPU::V_INDIRECT_REG_WRITE_B32_V16;

  case 1024: // 128 bytes

    return AMDGPU::V_INDIRECT_REG_WRITE_B32_V32;

  default:
  default:

    llvm_unreachable("unsupported size for MOVRELD pseudos");
    llvm_unreachable("unsupported size for IndirectRegWrite pseudos");

  }
  }

}
}




static MachineBasicBlock *emitIndirectDst(MachineInstr &MI,
static MachineBasicBlock *emitIndirectDst(MachineInstr &MI,

                                          MachineBasicBlock &MBB,
                                          MachineBasicBlock &MBB,

                                          const GCNSubtarget &ST) {
                                          const GCNSubtarget &ST) {

  const SIInstrInfo *TII = ST.getInstrInfo();
  const SIInstrInfo *TII = ST.getInstrInfo();

  const SIRegisterInfo &TRI = TII->getRegisterInfo();
  const SIRegisterInfo &TRI = TII->getRegisterInfo();

Show All 30 Lines  if (Idx->getReg() == AMDGPU::NoRegister) {

    MI.eraseFromParent();
    MI.eraseFromParent();

    return &MBB;
    return &MBB;

  }
  }




  if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset, UseGPRIdxMode, false)) {
  if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset, UseGPRIdxMode, false)) {

    MachineBasicBlock::iterator I(&MI);
    MachineBasicBlock::iterator I(&MI);

    const DebugLoc &DL = MI.getDebugLoc();
    const DebugLoc &DL = MI.getDebugLoc();




    if (UseGPRIdxMode) {
    const MCInstrDesc &MovRelDesc

      BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
      = TII->get(getIndirectRegWritePseudo(TRI, VecRC));

          .addReg(SrcVec->getReg(), RegState::Undef, SubReg) // vdst
    BuildMI(MBB, I, DL, MovRelDesc, Dst)

          .add(*Val)

          .addReg(Dst, RegState::ImplicitDefine)

          .addReg(SrcVec->getReg(), RegState::Implicit)

          .addReg(AMDGPU::M0, RegState::Implicit);



      BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));

    } else {

      const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));



      BuildMI(MBB, I, DL, MovRelDesc)

          .addReg(Dst, RegState::Define)

          .addReg(SrcVec->getReg())
      .addReg(SrcVec->getReg())

          .add(*Val)
      .add(*Val)

          .addImm(SubReg - AMDGPU::sub0);
      .addImm(SubReg);

    }
    if (UseGPRIdxMode)

      BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));




    MI.eraseFromParent();
    MI.eraseFromParent();

    return &MBB;
    return &MBB;

  }
  }




  if (Val->isReg())
  if (Val->isReg())

    MRI.clearKillFlags(Val->getReg());
    MRI.clearKillFlags(Val->getReg());




  const DebugLoc &DL = MI.getDebugLoc();
  const DebugLoc &DL = MI.getDebugLoc();




  Register PhiReg = MRI.createVirtualRegister(VecRC);
  Register PhiReg = MRI.createVirtualRegister(VecRC);




  auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg,
  auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg,

                              Offset, UseGPRIdxMode, false);
                              Offset, UseGPRIdxMode, false);

  MachineBasicBlock *LoopBB = InsPt->getParent();
  MachineBasicBlock *LoopBB = InsPt->getParent();




  if (UseGPRIdxMode) {
  const MCInstrDesc &MovRelDesc = TII->get(getIndirectRegWritePseudo(TRI, VecRC));

    BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
  BuildMI(*LoopBB, InsPt, DL, MovRelDesc, Dst)

        .addReg(PhiReg, RegState::Undef, SubReg) // vdst

        .add(*Val)                               // src0

        .addReg(Dst, RegState::ImplicitDefine)

        .addReg(PhiReg, RegState::Implicit)

        .addReg(AMDGPU::M0, RegState::Implicit);

    BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));

  } else {

    const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));



    BuildMI(*LoopBB, InsPt, DL, MovRelDesc)

        .addReg(Dst, RegState::Define)

        .addReg(PhiReg)
    .addReg(PhiReg)

        .add(*Val)
    .add(*Val)

        .addImm(SubReg - AMDGPU::sub0);
    .addImm(AMDGPU::sub0);

  }
  if (UseGPRIdxMode)

    BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));




  MI.eraseFromParent();
  MI.eraseFromParent();



  return LoopBB;
  return LoopBB;

}
}




MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(

  MachineInstr &MI, MachineBasicBlock *BB) const {
  MachineInstr &MI, MachineBasicBlock *BB) const {




  const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
  const SIInstrInfo *TII = getSubtarget()->getInstrInfo();

  MachineFunction *MF = BB->getParent();
  MachineFunction *MF = BB->getParent();

▲ Show 20 Lines • Show All 7,525 Lines • Show Last 20 Lines
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Show First 20 Lines • Show All 1,474 Lines • ▼ Show 20 Lines    MachineInstr *Copy = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO),

                                 MI.getOperand(0).getReg())
                                 MI.getOperand(0).getReg())

      .add(MI.getOperand(2));
      .add(MI.getOperand(2));

    expandPostRAPseudo(*Copy);
    expandPostRAPseudo(*Copy);

    BuildMI(MBB, MI, DL, get(NotOpc), Exec)
    BuildMI(MBB, MI, DL, get(NotOpc), Exec)

      .addReg(Exec);
      .addReg(Exec);

    MI.eraseFromParent();
    MI.eraseFromParent();

    break;
    break;

  }
  }

  case AMDGPU::V_MOVRELD_B32_V1:
  case AMDGPU::V_INDIRECT_REG_WRITE_B32_V1:

  case AMDGPU::V_MOVRELD_B32_V2:
  case AMDGPU::V_INDIRECT_REG_WRITE_B32_V2:

  case AMDGPU::V_MOVRELD_B32_V4:
  case AMDGPU::V_INDIRECT_REG_WRITE_B32_V3:

  case AMDGPU::V_MOVRELD_B32_V8:
  case AMDGPU::V_INDIRECT_REG_WRITE_B32_V4:

  case AMDGPU::V_MOVRELD_B32_V16: {
  case AMDGPU::V_INDIRECT_REG_WRITE_B32_V5:

    const MCInstrDesc &MovRelDesc = get(AMDGPU::V_MOVRELD_B32_e32);
  case AMDGPU::V_INDIRECT_REG_WRITE_B32_V8:

  case AMDGPU::V_INDIRECT_REG_WRITE_B32_V16:

  case AMDGPU::V_INDIRECT_REG_WRITE_B32_V32: {

    unsigned Opc = ST.useVGPRIndexMode() ?

      AMDGPU::V_MOV_B32_indirect : AMDGPU::V_MOVRELD_B32_e32;

    const MCInstrDesc &OpDesc = get(Opc);

    Register VecReg = MI.getOperand(0).getReg();
    Register VecReg = MI.getOperand(0).getReg();

    bool IsUndef = MI.getOperand(1).isUndef();
    bool IsUndef = MI.getOperand(1).isUndef();

    unsigned SubReg = AMDGPU::sub0 + MI.getOperand(3).getImm();
    unsigned SubReg = MI.getOperand(3).getImm();

    assert(VecReg == MI.getOperand(1).getReg());
    assert(VecReg == MI.getOperand(1).getReg());




    MachineInstr *MovRel =
    MachineInstrBuilder MIB =

        BuildMI(MBB, MI, DL, MovRelDesc)
      BuildMI(MBB, MI, DL, OpDesc)

            .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
        .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)

            .add(MI.getOperand(2))
        .add(MI.getOperand(2))

            .addReg(VecReg, RegState::ImplicitDefine)
        .addReg(VecReg, RegState::ImplicitDefine)

            .addReg(VecReg,
        .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));

                    RegState::Implicit | (IsUndef ? RegState::Undef : 0));




    const int ImpDefIdx =
    const int ImpDefIdx =

        MovRelDesc.getNumOperands() + MovRelDesc.getNumImplicitUses();
      OpDesc.getNumOperands() + OpDesc.getNumImplicitUses();

    const int ImpUseIdx = ImpDefIdx + 1;
    const int ImpUseIdx = ImpDefIdx + 1;

    MovRel->tieOperands(ImpDefIdx, ImpUseIdx);
    MIB->tieOperands(ImpDefIdx, ImpUseIdx);



    MI.eraseFromParent();
    MI.eraseFromParent();

    break;
    break;

  }
  }

  case AMDGPU::SI_PC_ADD_REL_OFFSET: {
  case AMDGPU::SI_PC_ADD_REL_OFFSET: {

    MachineFunction &MF = *MBB.getParent();
    MachineFunction &MF = *MBB.getParent();

    Register Reg = MI.getOperand(0).getReg();
    Register Reg = MI.getOperand(0).getReg();

    Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
    Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0);

    Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
    Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1);

▲ Show 20 Lines • Show All 5,113 Lines • Show Last 20 Lines
llvm/lib/Target/AMDGPU/VOP1Instructions.td
Show First 20 Lines • Show All 806 Lines • ▼ Show 20 Lines
def V_MOV_B32_indirect : VPseudoInstSI<(outs),
def V_MOV_B32_indirect : VPseudoInstSI<(outs),

  (ins getVALUDstForVT<i32>.ret:$vdst, getVOPSrc0ForVT<i32>.ret:$src0)>,
  (ins getVALUDstForVT<i32>.ret:$vdst, getVOPSrc0ForVT<i32>.ret:$src0)>,

  PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst,
  PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst,

                                        getVOPSrc0ForVT<i32>.ret:$src0)> {
                                        getVOPSrc0ForVT<i32>.ret:$src0)> {

  let VOP1 = 1;
  let VOP1 = 1;

  let SubtargetPredicate = isGFX8GFX9;
  let SubtargetPredicate = isGFX8GFX9;

}
}




// This is a pseudo variant of the v_movreld_b32 instruction in which the
// This is a pseudo variant of the v_movreld_b32 (or v_mov_b32

// vector operand appears only twice, once as def and once as use. Using this
// expecting to be executed with gpr indexing mode enabled)

// pseudo avoids problems with the Two Address instructions pass.
// instruction in which the vector operand appears only twice, once as

class V_MOVRELD_B32_pseudo<RegisterClass rc> : VPseudoInstSI <
// def and once as use. Using this pseudo avoids problems with the Two

// Address instructions pass.

class V_INDIRECT_REG_WRITE_B32_pseudo<RegisterClass rc> : VPseudoInstSI <

  (outs rc:$vdst),
  (outs rc:$vdst),

  (ins rc:$vsrc, VSrc_b32:$val, i32imm:$offset)> {
  (ins rc:$vsrc, VSrc_b32:$val, i32imm:$subreg)> {

  let VOP1 = 1;
  let VOP1 = 1;




  let Constraints = "$vsrc = $vdst";
  let Constraints = "$vsrc = $vdst";

  let Uses = [M0, EXEC];
  let Uses = [M0, EXEC];



  let SubtargetPredicate = HasMovrel;

}
}




def V_MOVRELD_B32_V1 : V_MOVRELD_B32_pseudo<VGPR_32>;
def V_INDIRECT_REG_WRITE_B32_V1 : V_INDIRECT_REG_WRITE_B32_pseudo<VGPR_32>;

def V_MOVRELD_B32_V2 : V_MOVRELD_B32_pseudo<VReg_64>;
def V_INDIRECT_REG_WRITE_B32_V2 : V_INDIRECT_REG_WRITE_B32_pseudo<VReg_64>;

def V_MOVRELD_B32_V4 : V_MOVRELD_B32_pseudo<VReg_128>;
def V_INDIRECT_REG_WRITE_B32_V3 : V_INDIRECT_REG_WRITE_B32_pseudo<VReg_96>;

def V_MOVRELD_B32_V8 : V_MOVRELD_B32_pseudo<VReg_256>;
def V_INDIRECT_REG_WRITE_B32_V4 : V_INDIRECT_REG_WRITE_B32_pseudo<VReg_128>;

def V_MOVRELD_B32_V16 : V_MOVRELD_B32_pseudo<VReg_512>;
def V_INDIRECT_REG_WRITE_B32_V5 : V_INDIRECT_REG_WRITE_B32_pseudo<VReg_160>;

def V_INDIRECT_REG_WRITE_B32_V8 : V_INDIRECT_REG_WRITE_B32_pseudo<VReg_256>;

def V_INDIRECT_REG_WRITE_B32_V16 : V_INDIRECT_REG_WRITE_B32_pseudo<VReg_512>;

def V_INDIRECT_REG_WRITE_B32_V32 : V_INDIRECT_REG_WRITE_B32_pseudo<VReg_1024>;




let OtherPredicates = [isGFX8Plus] in {
let OtherPredicates = [isGFX8Plus] in {




def : GCNPat <
def : GCNPat <

  (i32 (int_amdgcn_mov_dpp i32:$src, timm:$dpp_ctrl, timm:$row_mask, timm:$bank_mask,
  (i32 (int_amdgcn_mov_dpp i32:$src, timm:$dpp_ctrl, timm:$row_mask, timm:$bank_mask,

                      timm:$bound_ctrl)),
                      timm:$bound_ctrl)),

  (V_MOV_B32_dpp $src, $src, (as_i32imm $dpp_ctrl),
  (V_MOV_B32_dpp $src, $src, (as_i32imm $dpp_ctrl),

                       (as_i32imm $row_mask), (as_i32imm $bank_mask),
                       (as_i32imm $row_mask), (as_i32imm $bank_mask),

▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines