Page MenuHomePhabricator

AMDGPU: Partially merge indirect register write handling
ClosedPublic

Authored by arsenm on Jan 3 2020, 2:43 PM.

Details

Summary

a785209bc2fb switched to using a pseudos instead of manually tying
operands on the regular instruction. The VGPR indexing mode path
should have the same problems that change attempted to avoid, so these
should use the same strategy.

Use a single pseudo for the VGPR indexing mode and movreld paths, and
expand it based on the subtarget later. These have essentially the
same constraints, reading the index from m0.

Switch from using an offset to the subregister index directly, instead
of computing an offset and re-adding it back. Also add missing pseudos
for existing register class sizes.

Diff Detail

Event Timeline

arsenm created this revision.Jan 3 2020, 2:43 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 3 2020, 2:43 PM

The change seems to miss parent revision introducing V_INDIRECT_REG_WRITE_*.

The change seems to miss parent revision introducing V_INDIRECT_REG_WRITE_*.

It's introduced /renamed here

This revision is now accepted and ready to land.Jan 20 2020, 12:48 PM