AMDGPU/GlobalISel: Skip DAG hack passes on selected functions

[arsenm]

Summary

The way fallback to SelectionDAG works is somewhat surprising to
me. When the fallback path is enabled, the entire set of SelectionDAG
selector passes is added to the pass pipeline, and each one needs to
check if the function was selected. This results in the surprising
behavior of running SIFixSGPRCopies for example, but only if
-global-isel-abort=2 is used.

SIAddIMGInitPass is also added in addInstSelector, but I'm not sure
why we have this pass or if it should be added somewhere else for
GlobalISel.

[kerbowa]

test?

[arsenm]

In D71855#1798302, @kerbowa wrote:

test?

I'm not sure this can be meaningfully tested. These passes ideally would end up being no-ops anyway. I think I noticed this from one of these crashing on invalid MIR, or some situation they don't handle correctly. In either case, there's not supposed to be a useful output to check

[arsenm]

ping

[kerbowa]

LGTM

[arsenm]

d9e8b2cbccccfea5189277f1e5e793320cbbeb19

llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp

static bool hoistAndMergeSGPRInits(unsigned Reg,
 
   if (Changed)
     MRI.clearKillFlags(Reg);
 
   return Changed;
 }
 
 bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
+  // Only need to run this in SelectionDAG path.
+  if (MF.getProperties().hasProperty(
+        MachineFunctionProperties::Property::Selected))
+    return false;
+
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
   MRI = &MF.getRegInfo();
   TRI = ST.getRegisterInfo();
   TII = ST.getInstrInfo();
   MDT = &getAnalysis<MachineDominatorTree>();
 
   SmallVector<MachineInstr *, 16> Worklist;
 

llvm/lib/Target/AMDGPU/SIFixupVectorISel.cpp

for (I = MBB.begin(); I != MBB.end(); I = Next) {
     // Remove the old Global Memop instruction.
     MI.eraseFromParent();
     LLVM_DEBUG(dbgs() << "New Global Mem " << *NewGlob << '\n');
   }
   return FuncModified;
 }
 
 bool SIFixupVectorISel::runOnMachineFunction(MachineFunction &MF) {
+  // Only need to run this in SelectionDAG path.
+  if (MF.getProperties().hasProperty(
+        MachineFunctionProperties::Property::Selected))
+    return false;
+
   if (skipFunction(MF.getFunction()))
     return false;
 
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
   const SIInstrInfo *TII = ST.getInstrInfo();
   const SIRegisterInfo *TRI = ST.getRegisterInfo();
 
   bool FuncModified = false;
   for (MachineBasicBlock &MBB : MF) {
     // Cleanup missed Saddr opportunites from ISel.
     FuncModified |= fixupGlobalSaddr(MBB, MF, MRI, ST, TII, TRI);
   }
   return FuncModified;
 }

llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp

 /// In a first pass, we lower COPYs from vreg_1 to vector registers, as can
 /// occur around inline assembly. We do this first, before vreg_1 registers
 /// are changed to scalar mask registers.
 ///
 /// Then we lower all defs of vreg_1 registers. Phi nodes are lowered before
 /// all others, because phi lowering looks through copies and can therefore
 /// often make copy lowering unnecessary.
 bool SILowerI1Copies::runOnMachineFunction(MachineFunction &TheMF) {
+  // Only need to run this in SelectionDAG path.
+  if (TheMF.getProperties().hasProperty(
+        MachineFunctionProperties::Property::Selected))
+    return false;
+
   MF = &TheMF;
   MRI = &MF->getRegInfo();
   DT = &getAnalysis<MachineDominatorTree>();
   PDT = &getAnalysis<MachinePostDominatorTree>();
 
   ST = &MF->getSubtarget<GCNSubtarget>();
   TII = ST->getInstrInfo();
   IsWave32 = ST->isWave32();