[PowerPC] Adding a match pattern to recognize the and mask with RLWINM8

[steven.zhang]

Summary

This is the motivate case:

define i32 @foo1(i32 %x) {
entry:
  %and = and i32 %x, -2
  ret i32 %and
}

PowerPC has several mechanism(tryBitPermutation() and custom select for AND/OR etc) to generate the bit operation better with the combination of AND/OR/XOR etc. This case isn't handled by these mechanism. So, I added a match pattern in the td to do the final selection, though, technical speaking, we could extend those mechanism to handle this case also.

[nemanjai]

LGTM.

[shchenz]

LGTM too.

Could you please check if there is similar opportunity for and. -> rlwinm.? Thanks.

[steven.zhang]

Oops, I suddenly realize that, the rlwinm can only rotate the high 32bit. We need to check if the mask is UInt32 or not.

rlwinm RA,RS,SH,MB,ME
n <- SH
r <- ROTL32((RS)32:63, n)     #<--- RS 32:63 ...
m <- MASK(MB+32, ME+32)
RA <- r & m

[steven.zhang]

Update the patch as one critical bug was found.

[shchenz]

Right, current patch should still be with bug.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

385

we can only return true when mb is not bigger than me. and mask can be 0XF000000F, it becomes to 0XFFFFFFFFF000000F in rlwinm,then we get a 64bit value. This is wrong.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

385

Good point. And yes, this is the problem.

[lkail]

This comment was removed by lkail.

[lkail]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

385

Do we have to check Mask & 0xffffffff00000000 == 0?

[lkail]

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

1361

Does (and i32:$in, maskimm32:$imm) also work?

[steven.zhang]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

385

No, it has been checked by isUInt<32>(Mask). However, I am planing to abandon this patch to post a completely patch that fix all the "and mask" issue llvm powerpc have.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 def : Pat<(i64 (zext i32:$in)),
           (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
                   0, 32)>;
 def : Pat<(i64 (anyext i32:$in)),
           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
 def : Pat<(i32 (trunc i64:$in)),
           (EXTRACT_SUBREG $in, sub_32)>;
 
+// RLWINM8
+def : Pat<(and i64:$in, maskimm64:$imm),
+          (RLWINM8 $in, 0, (MB maskimm64:$imm), (ME maskimm64:$imm))>;
+
 // Implement the 'not' operation with the NOR instruction.
 // (we could use the default xori pattern, but nor has lower latency on some
 // cores (such as the A2)).
 def i64not : OutPatFrag<(ops node:$in),
                         (NOR8 $in, $in)>;
 def        : Pat<(not i64:$in),
                  (i64not $in)>;
 

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def maskimm32 : PatLeaf<(imm), [{
   // maskImm predicate - True if immediate is a run of ones.
   unsigned mb, me;
   if (N->getValueType(0) == MVT::i32)
     return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
   else
     return false;
 }]>;
 
+def maskimm64 : PatLeaf<(imm), [{
+  // maskImm predicate - True if immediate is a run of ones.
+  unsigned mb, me;
+  if (N->getValueType(0) == MVT::i64) {
+    // High 32-bit need to be zero.
+    uint64_t Mask = (uint64_t)N->getZExtValue();
+    return isUInt<32>(Mask) && isRunOfOnes((unsigned)Mask, mb, me);
+  }
+  else
+    return false;
+}]>;
+
 def imm32SExt16  : Operand<i32>, ImmLeaf<i32, [{
   // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
   // sign extended field.  Used by instructions like 'addi'.
   return (int32_t)Imm == (short)Imm;
 }]>;
 def imm64SExt16  : Operand<i64>, ImmLeaf<i64, [{
   // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
   // sign extended field.  Used by instructions like 'addi'.

llvm/test/CodeGen/PowerPC/cmpb.ll

entry:
   %conv50 = select i1 %cmp34, i32 458752, i32 0
   %conv53 = select i1 %cmp40, i32 -16777216, i32 0
   %or = or i32 %conv48, %conv53
   %or52 = or i32 %or, %conv47
   %or55 = or i32 %or52, %conv50
   ret i32 %or55
 
 ; CHECK-LABEL: @test32p1
-; CHECK: li [[REG1:[0-9]+]], 0
 ; CHECK: cmpb [[REG4:[0-9]+]], 4, 3
-; CHECK: oris [[REG2:[0-9]+]], [[REG1]], 65287
-; CHECK: ori [[REG3:[0-9]+]], [[REG2]], 65535
-; CHECK: and 3, [[REG4]], [[REG3]]
+; CHECK: rlwinm 3, [[REG4]], 0, 13, 7 
 ; CHECK: blr
 }
 
 define zeroext i32 @test32p2(i32 zeroext %x, i32 zeroext %y) #0 {
 entry:
   %0 = xor i32 %y, %x
   %1 = and i32 %0, 255
   %cmp = icmp eq i32 %1, 0
   %2 = and i32 %0, 65280
   %cmp22 = icmp eq i32 %2, 0
   %cmp28 = icmp ult i32 %0, 16777216
   %conv32 = select i1 %cmp, i32 255, i32 0
   %conv33 = select i1 %cmp22, i32 65280, i32 0
   %conv35 = select i1 %cmp28, i32 -16777216, i32 0
   %or = or i32 %conv33, %conv35
   %or37 = or i32 %or, %conv32
   ret i32 %or37
 
 ; CHECK-LABEL: @test32p2
-; CHECK: li [[REG1:[0-9]+]], 0
 ; CHECK: cmpb [[REG4:[0-9]+]], 4, 3
-; CHECK: oris [[REG2:[0-9]+]], [[REG1]], 65280
-; CHECK: ori [[REG3:[0-9]+]], [[REG2]], 65535
-; CHECK: and 3, [[REG4]], [[REG3]]
+; CHECK: rlwinm 3, [[REG4]], 0, 16, 7 
 ; CHECK: blr
 }
 
 define i64 @test64(i64 %x, i64 %y) #0 {
 entry:
   %shr19 = lshr i64 %x, 56
   %conv21 = trunc i64 %shr19 to i32
   %shr43 = lshr i64 %y, 56

llvm/test/CodeGen/PowerPC/shift_mask.ll

; CHECK-NEXT:    blr
   %rem = and <2 x i64> %b, <i64 63, i64 63>
   %ashr = ashr <2 x i64> %a, %rem
   ret <2 x i64> %ashr
 }
 
 define i32 @test214(i32 %a) {
 ; CHECK-LABEL: test214:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lis 4, 32767
-; CHECK-NEXT:    ori 4, 4, 65535
-; CHECK-NEXT:    sldi 4, 4, 1
-; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    rlwinm 3, 3, 0, 0, 30
 ; CHECK-NEXT:    blr
   %and = and i32 %a, -2
   ret i32 %and
 }
 
 define i64 @test215(i64 %a) {
 ; CHECK-LABEL: test215:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, -7
 ; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    blr
   %and = and i64 %a, -7
   ret i64 %and
 }