[llvm-objdump] Print target address instead of call/j/br pc-rel immediate

[sperezglz]

Summary

binutils:
400436: 74 02 je 40043a <_init+0x12>

llvm-objdump currently :
400436: 74 02 je 0x2 <_init+0x12>

Even though the symbol + offset is printed with llvm-objdump I believe it is more intuitive to see the target address as well.

[jhenderson]

I have no issues with attempting to improve GNU compatibility, but please see my inline comments, as you appear to have degraded some of the experience for one feature that is not present in GNU objdump. Also, I'm somewhat surprised that this issue doesn't affect other targets. Do they already do the right thing?

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

1341–1342 ↗

(On Diff #233742)

Rather than removing this comment, I think you should change it to say why you do nothing here.

1344 ↗

(On Diff #233742)

Rather than removing the syntax highlighting, I think it would be preferable to keep it, but perhaps in a different colour? @seiya added this as part of the GSOC work last summer, so he may be best placed to suggest an alternative.

Same comment applies elsewhere.

[MaskRay]

This is basically the largest blocker that prevents me from using llvm-objdump regularly / or why I am still using powerpc-linux-gnu-objdump -d, objdump -d, etc... I thought about fixing this, but it would require a lot of test update.

If lld is in your -DLLVM_ENABLE_PROJECTS= list, try ninja check-lld, there should be lots of failures. There is an llvm-objdump option --print-imm-hex which is also used to decide whether an immediate should be printed in the hexadecimal form, but the target InstrPrinter code may not consistently respect it. (I've updated many lld tests to use --print-imm-hex, but I believe there are still lots of remaining issues... After --print-imm-hex becomes the default, we should probably do another clean-up to remove the option)

[sperezglz]

Thanks for the feedback @jhenderson @MaskRay I will do as suggested and first try to scope the effort of making this consistant for all the remaining targets and check failing tests in other tools. I will also investigate if it is possible to achieve this without touching the target's InstPrinters and maybe adding a clo, or any approach that would cause less disruption and/or less effort for fixing potentially impacted tests. Get back to you as soon as I have something.

[sperezglz]

I used a different approach in this update, adding a command line option and leaving the target's instruction printers untouched, now unless the CLO is used the output is the same as standard, that is friendlier with existing tests. The other thing I had to do was to create an "indirect call" property, only added it to x86 , this was needed because a target address shouldn't be calculated (or printed) for indirect calls and I needed a way to identify them.

[jhenderson]

llvm/include/llvm/MC/MCInstrDesc.h

280

Nit: missing trailing full stop.

llvm/tools/llvm-objdump/llvm-objdump.cpp

341

"tgt" is not an obvious abbreviation for "target" to me. I'd recommend just "print-target-addr" or "print-target-address".

680

This change seems unnecessary for the rest of the change?

1493

LLVM style is to use upper-case for variable names (i.e. splitInstStream -> SplitInstStream). It's also not immediately obvious what auto represents here, so consider replacing it with the full type.

That all being said, I'm not especially keen on this approach, as it seems to tie the code here to how the instructions are printed inside the corresponding instruction printer. It feels like something that could break very easily to me. That being said, I don't have a clear suggestion for an alternative at this point. @MaskRay might do.

1494–1498

You can reduce some of the duplication here by adding the comment and symbol details outside this if:

if (PrintTargetAddress) {
  auto splitInstStream = InstPrintStream.str().rsplit('\t');
  outs() << splitInstStream.first << '\t' << Twine::utohexstr(Target);
} else {
  outs() << InstPrintStream.str();
}
outs() << CommentStream.str() << SymbolDetailsStream.str();

1500

What's the point of this line? It's about to go out of scope.

1506

Same comment as above. InstPrinterBuffer is not going to be used again, so why clear it?

Note that the Comments string and stream are constructed outside the loop, so need to be cleared in order to be reused. You may wish to do the same thing with the other streams for performance reasons (though I don't know for sure).

[sperezglz]

llvm/include/llvm/MC/MCInstrDesc.h

280

Sure , I'll add it.

llvm/tools/llvm-objdump/llvm-objdump.cpp

341

Yes that makes sense.

680

This was necessary because this function is used in the Hexagon prettyPrinter and it was printing directly to "outs()" by default while I'm sending everything to a temporary buffer so I had to add a parameter to make it flexible, this came out on a couple of Hexagon tests failing, but with this change those work fine.

1493

Yes the variable name was a typo I'll change it and add explicit type to the variable.

About the approach, in my opinion the main advantage is that the core of changes is centralized to one file and does not involve changing every target Inst Printer, the hard requirement is that there is a "\t" between instruction and immediate.

I'll fix the stuff pointed out by the comments and leave it for discussion and reference in case other suggestions come up.

1494–1498

You are right , I'll clean it up.

1506

Yeah sorry about those two, I tried to keep it safe by clearing but lost track of the scope where they live.

[MaskRay]

MIPS beq $9, $6, 1332
RISCV: beqz x10, 512
PPC: bl .+offset [1]

These are examples that a direct call/jump instruction may take more than one operands, or have a custom target address printing method. They demonstrate that llvm-objdump just lacks target-specific knowledge to make the dump look good. Instead, I think we should

• Teach MCInstPrinter::printInst and MCInstrPrinter::printInstruction to take an extra parameter Address (D72172 D72180)
• Migrate targets's *InstrInfo.td files to use a different PrintMethod, say, printBranchOperand, instead of the default printOperand.
• In printInstruction (generated by tablegen), pass Address to printBranchOperand.

  case 1:
    // PseudoFLD, PseudoFLW, PseudoFSD, PseudoFSW, PseudoSB, PseudoSD, Pseudo...
-    printBranchOperand(MI, 1, STI, O);
+    printBranchOperand(MI, 1, Address, STI, O);
    return;
    break;

[1]: PPC currently prints bl .+offset

void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
                                        raw_ostream &O) {
  if (!MI->getOperand(OpNo).isImm())
    return printOperand(MI, OpNo, O);

  // Branches can take an immediate operand.  This is used by the branch
  // selection pass to print .+8, an eight byte displacement from the PC.
  O << ".";
  int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
  if (Imm >= 0)
    O << "+";
  O << Imm;
}

[sperezglz]

This comment was removed by sperezglz.

[sperezglz]

Oh ok, I was not aware of such examples, those cases make this approach invalid. Abandoning this, thanks for the reviews.

llvm/include/llvm/CodeGen/MachineInstr.h

public:
   bool isEHScopeReturn(QueryType Type = AnyInBundle) const {
     return hasProperty(MCID::EHScopeReturn, Type);
   }
 
   bool isCall(QueryType Type = AnyInBundle) const {
     return hasProperty(MCID::Call, Type);
   }
 
+  /// Return true if this is an indirect call
+  bool isIndirectCall(QueryType Type = AnyInBundle) const {
+    return hasProperty(MCID::IndirectCall, Type);
+  }
+
   /// Returns true if the specified instruction stops control flow
   /// from executing the instruction immediately following it.  Examples include
   /// unconditional branches and return instructions.
   bool isBarrier(QueryType Type = AnyInBundle) const {
     return hasProperty(MCID::Barrier, Type);
   }
 
   /// Returns true if this instruction part of the terminator for a basic block.

llvm/include/llvm/MC/MCInstrAnalysis.h

public:
   virtual bool isIndirectBranch(const MCInst &Inst) const {
     return Info->get(Inst.getOpcode()).isIndirectBranch();
   }
 
   virtual bool isCall(const MCInst &Inst) const {
     return Info->get(Inst.getOpcode()).isCall();
   }
 
+  virtual bool isIndirectCall(const MCInst &Inst) const {
+    return Info->get(Inst.getOpcode()).isIndirectCall();
+  }
+
   virtual bool isReturn(const MCInst &Inst) const {
     return Info->get(Inst.getOpcode()).isReturn();
   }
 
   virtual bool isTerminator(const MCInst &Inst) const {
     return Info->get(Inst.getOpcode()).isTerminator();
   }
 

llvm/include/llvm/MC/MCInstrDesc.h

enum Flag {
   ExtraDefRegAllocReq,
   RegSequence,
   ExtractSubreg,
   InsertSubreg,
   Convergent,
   Add,
   Trap,
   VariadicOpsAreDefs,
+  IndirectCall,
 };
 }
 
 /// Describe properties that are true of each instruction in the target
 /// description file.  This captures information about side effects, register
 /// use and many other things.  There is one instance of this struct for each
 /// target instruction class, and the MachineInstr class points to this struct
 /// directly to describe itself.
public:
   bool isTrap() const { return Flags & (1ULL << MCID::Trap); }
 
   /// Return true if the instruction is a register to register move.
   bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); }
 
   ///  Return true if the instruction is a call.
   bool isCall() const { return Flags & (1ULL << MCID::Call); }
 
+  /// Return true if this is an indirect call
+  bool isIndirectCall() const { return Flags & (1ULL << MCID::IndirectCall); }
+
   /// Returns true if the specified instruction stops control flow
   /// from executing the instruction immediately following it.  Examples include
   /// unconditional branches and return instructions.
   bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
 
   /// Returns true if this instruction part of the terminator for
   /// a basic block.  Typically this is things like return and branch
   /// instructions.

llvm/include/llvm/Target/Target.td

class Instruction : InstructionEncoding {
   bit isIndirectBranch = 0; // Is this instruction an indirect branch?
   bit isCompare    = 0;     // Is this instruction a comparison instruction?
   bit isMoveImm    = 0;     // Is this instruction a move immediate instruction?
   bit isMoveReg    = 0;     // Is this instruction a move register instruction?
   bit isBitcast    = 0;     // Is this instruction a bitcast instruction?
   bit isSelect     = 0;     // Is this instruction a select instruction?
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
+  bit isIndirectCall = 0;   // Is this instruction an indirect call?
   bit isAdd        = 0;     // Is this instruction an add instruction?
   bit isTrap       = 0;     // Is this instruction a trap instruction?
   bit canFoldAsLoad = 0;    // Can this be folded as a simple memory operand?
   bit mayLoad      = ?;     // Is it possible for this inst to read memory?
   bit mayStore     = ?;     // Is it possible for this inst to write memory?
   bit mayRaiseFPException = 0; // Can this raise a floating-point exception?
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?

llvm/lib/Target/X86/X86InstrControl.td

def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
                            (outs), (ins i32imm_pcrel:$dst),
                            "call{l}\t$dst", []>, OpSize32,
                       Requires<[Not64BitMode]>, Sched<[WriteJump]>;
     let hasSideEffects = 0 in
       def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
                              (outs), (ins i16imm_pcrel:$dst),
                              "call{w}\t$dst", []>, OpSize16,
                         Sched<[WriteJump]>;
+
+    let isIndirectCall = 1 in {
       def CALL16r     : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
                           "call{w}\t{*}$dst", [(X86call GR16:$dst)]>,
                         OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
       def CALL16m     : I<0xFF, MRM2m, (outs), (ins i16mem:$dst),
                           "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))]>,
                           OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>,
                           Sched<[WriteJumpLd]>;
       def CALL32r     : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
                           "call{l}\t{*}$dst", [(X86call GR32:$dst)]>, OpSize32,
                           Requires<[Not64BitMode,NotUseRetpolineIndirectCalls]>,
                           Sched<[WriteJump]>;
       def CALL32m     : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
                           "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>,
                           OpSize32,
                           Requires<[Not64BitMode,FavorMemIndirectCall,
                                     NotUseRetpolineIndirectCalls]>,
                           Sched<[WriteJumpLd]>;
 
       // Non-tracking calls for IBT, use with caution.
       let isCodeGenOnly = 1 in {
         def CALL16r_NT : I<0xFF, MRM2r, (outs), (ins GR16 : $dst),
                           "call{w}\t{*}$dst",[(X86NoTrackCall GR16 : $dst)]>,
                           OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK;
         def CALL16m_NT : I<0xFF, MRM2m, (outs), (ins i16mem : $dst),
                           "call{w}\t{*}$dst",[(X86NoTrackCall(loadi16 addr : $dst))]>,
                           OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>,
                           Sched<[WriteJumpLd]>, NOTRACK;
         def CALL32r_NT : I<0xFF, MRM2r, (outs), (ins GR32 : $dst),
                           "call{l}\t{*}$dst",[(X86NoTrackCall GR32 : $dst)]>,
                           OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK;
         def CALL32m_NT : I<0xFF, MRM2m, (outs), (ins i32mem : $dst),
                           "call{l}\t{*}$dst",[(X86NoTrackCall(loadi32 addr : $dst))]>,
                           OpSize32, Requires<[Not64BitMode,FavorMemIndirectCall]>,
                           Sched<[WriteJumpLd]>, NOTRACK;
       }
 
       let Predicates = [Not64BitMode], AsmVariantName = "att" in {
         def FARCALL16i  : Iseg16<0x9A, RawFrmImm16, (outs),
                                  (ins i16imm:$off, i16imm:$seg),
                                  "lcall{w}\t$seg, $off", []>,
                                  OpSize16, Sched<[WriteJump]>;
         def FARCALL32i  : Iseg32<0x9A, RawFrmImm16, (outs),
                                  (ins i32imm:$off, i16imm:$seg),
                                  "lcall{l}\t$seg, $off", []>,
                                  OpSize32, Sched<[WriteJump]>;
       }
 
       def FARCALL16m  : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
                           "lcall{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>;
       def FARCALL32m  : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
                           "{l}call{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>;
     }
+  }
 
 
 // Tail call stuff.
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
     isCodeGenOnly = 1, Uses = [ESP, SSP] in {
   def TCRETURNdi : PseudoI<(outs), (ins i32imm_pcrel:$dst, i32imm:$offset),
                            []>, Sched<[WriteJump]>, NotMemoryFoldable;
   def TCRETURNri : PseudoI<(outs), (ins ptr_rc_tailcall:$dst, i32imm:$offset),

 let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in {
   // NOTE: this pattern doesn't match "X86call imm", because we do not know
   // that the offset between an arbitrary immediate and the call will fit in
   // the 32-bit pcrel field that we have.
   def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
                         (outs), (ins i64i32imm_pcrel:$dst),
                         "call{q}\t$dst", []>, OpSize32,
                       Requires<[In64BitMode]>;
+  let isIndirectCall = 1 in {
     def CALL64r       : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
                           "call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
                         Requires<[In64BitMode,NotUseRetpolineIndirectCalls]>;
     def CALL64m       : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
                           "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
                         Requires<[In64BitMode,FavorMemIndirectCall,
                                   NotUseRetpolineIndirectCalls]>;
 
     // Non-tracking calls for IBT, use with caution.
     let isCodeGenOnly = 1 in {
       def CALL64r_NT : I<0xFF, MRM2r, (outs), (ins GR64 : $dst),
                         "call{q}\t{*}$dst",[(X86NoTrackCall GR64 : $dst)]>,
                         Requires<[In64BitMode]>, NOTRACK;
       def CALL64m_NT : I<0xFF, MRM2m, (outs), (ins i64mem : $dst),
                          "call{q}\t{*}$dst",
                          [(X86NoTrackCall(loadi64 addr : $dst))]>,
                          Requires<[In64BitMode,FavorMemIndirectCall]>, NOTRACK;
     }
-
+  }
   def FARCALL64   : RI<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
                        "lcall{q}\t{*}$dst", []>;
 }
 
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
     isCodeGenOnly = 1, Uses = [RSP, SSP] in {
   def TCRETURNdi64   : PseudoI<(outs),
                                (ins i64i32imm_pcrel:$dst, i32imm:$offset),

llvm/tools/llvm-objdump/llvm-objdump.cpp

 static cl::opt<bool>
     Wide("wide", cl::desc("Ignored for compatibility with GNU objdump"),
          cl::cat(ObjdumpCat));
 static cl::alias WideShort("w", cl::Grouping, cl::aliasopt(Wide));
 
 static cl::extrahelp
     HelpResponse("\nPass @FILE as argument to read options from FILE.\n");
 
+cl::opt<bool>
+    PrintTargetAddress("print-tgt-addr",
+                       cl::desc("Print target address instead of immediate "
+                                "value in pc-rel branches and calls"),
+                       cl::cat(ObjdumpCat));
+
 static StringSet<> DisasmFuncsSet;
 static StringSet<> FoundSectionSet;
 static StringRef ToolName;
 
 typedef std::vector<std::tuple<uint64_t, StringRef, uint8_t>> SectionSymbolsTy;
 
 namespace {
 struct FilterResult {
static bool isArmElf(const ObjectFile *Obj) {
   return Elf && Elf->getEMachine() == ELF::EM_ARM;
 }
 
 static bool hasMappingSymbols(const ObjectFile *Obj) {
   return isArmElf(Obj) || isAArch64Elf(Obj);
 }
 
 static void printRelocation(StringRef FileName, const RelocationRef &Rel,
-                            uint64_t Address, bool Is64Bits) {
+                            uint64_t Address, bool Is64Bits, raw_ostream &OS) {
   StringRef Fmt = Is64Bits ? "\t\t%016" PRIx64 ":  " : "\t\t\t%08" PRIx64 ":  ";
   SmallString<16> Name;
   SmallString<32> Val;
   Rel.getTypeName(Name);
   if (Error E = getRelocationValueString(Rel, Val))
     reportError(std::move(E), FileName);
-  outs() << format(Fmt.data(), Address) << Name << "\t" << Val << "\n";
+  OS << format(Fmt.data(), Address) << Name << "\t" << Val << "\n";
 }
 
 class PrettyPrinter {
 public:
   virtual ~PrettyPrinter() = default;
   virtual void printInst(MCInstPrinter &IP, const MCInst *MI,
                          ArrayRef<uint8_t> Bytes,
                          object::SectionedAddress Address, raw_ostream &OS,
void printInst(MCInstPrinter &IP, const MCInst *MI, ArrayRef<uint8_t> Bytes,
 
     // Hexagon's packets require relocations to be inline rather than
     // clustered at the end of the packet.
     std::vector<RelocationRef>::const_iterator RelCur = Rels->begin();
     std::vector<RelocationRef>::const_iterator RelEnd = Rels->end();
     auto PrintReloc = [&]() -> void {
       while ((RelCur != RelEnd) && (RelCur->getOffset() <= Address.Address)) {
         if (RelCur->getOffset() == Address.Address) {
-          printRelocation(ObjectFilename, *RelCur, Address.Address, false);
+          printRelocation(ObjectFilename, *RelCur, Address.Address, false, OS);
           return;
         }
         ++RelCur;
       }
     };
 
     while (!HeadTail.first.empty()) {
       OS << Separator;
#endif
             STI = PrimaryIsThumb ? PrimarySTI : SecondarySTI;
             DisAsm = PrimaryIsThumb ? PrimaryDisAsm : SecondaryDisAsm;
           }
         }
 
         // Disassemble a real instruction or a data when disassemble all is
         // provided
         MCInst Inst;
+        SmallString<90> InstPrinterBuffer;
+        raw_svector_ostream InstPrintStream(InstPrinterBuffer);
         bool Disassembled = DisAsm->getInstruction(
             Inst, Size, Bytes.slice(Index), SectionAddr + Index, DebugOut,
             CommentStream);
         if (Size == 0)
           Size = 1;
 
-        PIP.printInst(*IP, Disassembled ? &Inst : nullptr,
-                      Bytes.slice(Index, Size),
-                      {SectionAddr + Index + VMAAdjustment, Section.getIndex()},
-                      outs(), "", *STI, &SP, Obj->getFileName(), &Rels);
-        outs() << CommentStream.str();
-        Comments.clear();
+        PIP.printInst(
+            *IP, Disassembled ? &Inst : nullptr, Bytes.slice(Index, Size),
+            InstPrintStream, "", *STI, &SP, Obj->getFileName(), &Rels);
 
         // Try to resolve the target of a call, tail call, etc. to a specific
         // symbol.
-        if (MIA && (MIA->isCall(Inst) || MIA->isUnconditionalBranch(Inst) ||
+        if (MIA && ((MIA->isCall(Inst) && !MIA->isIndirectCall(Inst)) ||
+                    MIA->isUnconditionalBranch(Inst) ||
                     MIA->isConditionalBranch(Inst))) {
           uint64_t Target;
+          SmallString<50> TargetSymbolDetails;
+          raw_svector_ostream SymbolDetailsStream(TargetSymbolDetails);
           if (MIA->evaluateBranch(Inst, SectionAddr + Index, Size, Target)) {
             // In a relocatable object, the target's section must reside in
             // the same section as the call instruction or it is accessed
             // through a relocation.
             //
             // In a non-relocatable object, the target may be in any section.
             //
             // N.B. We don't walk the relocations in the relocatable case yet.
#endif
                   [=](const std::tuple<uint64_t, StringRef, uint8_t> &O) {
                     return std::get<0>(O) <= Target;
                   });
             }
             if (TargetSym != TargetSectionSymbols->begin()) {
               --TargetSym;
               uint64_t TargetAddress = std::get<0>(*TargetSym);
               StringRef TargetName = std::get<1>(*TargetSym);
-              outs() << " <" << TargetName;
+              SymbolDetailsStream << " <" << TargetName;
               uint64_t Disp = Target - TargetAddress;
               if (Disp)
-                outs() << "+0x" << Twine::utohexstr(Disp);
-              outs() << '>';
+                SymbolDetailsStream << "+0x" << Twine::utohexstr(Disp);
+              SymbolDetailsStream << '>';
             }
           }
+          if (PrintTargetAddress) {
+            auto splitInstStream = InstPrintStream.str().rsplit('\t');
+            outs() << splitInstStream.first << '\t' << Twine::utohexstr(Target)
+                   << CommentStream.str() << SymbolDetailsStream.str();
+          } else {
+            outs() << InstPrintStream.str() << CommentStream.str()
+                   << SymbolDetailsStream.str();
           }
+          TargetSymbolDetails.clear();
+        } else {
+          outs() << InstPrintStream.str() << CommentStream.str();
+        }
+
+        Comments.clear();
+        InstPrinterBuffer.clear();
         outs() << "\n";
 
         // Hexagon does this in pretty printer
         if (Obj->getArch() != Triple::hexagon) {
           // Print relocation for instruction.
           while (RelCur != RelEnd) {
             uint64_t Offset = RelCur->getOffset();
             // If this relocation is hidden, skip it.
#endif
               Expected<section_iterator> SymSI =
                   RelCur->getSymbol()->getSection();
               if (SymSI && *SymSI != Obj->section_end() &&
                   shouldAdjustVA(**SymSI))
                 Offset += AdjustVMA;
             }
 
             printRelocation(Obj->getFileName(), *RelCur, SectionAddr + Offset,
-                            Is64Bits);
+                            Is64Bits, outs());
             ++RelCur;
           }
         }
 
         Index += Size;
       }
     }
   }

llvm/utils/TableGen/CodeGenInstruction.h

public:
     bool isIndirectBranch : 1;
     bool isCompare : 1;
     bool isMoveImm : 1;
     bool isMoveReg : 1;
     bool isBitcast : 1;
     bool isSelect : 1;
     bool isBarrier : 1;
     bool isCall : 1;
+    bool isIndirectCall : 1;
     bool isAdd : 1;
     bool isTrap : 1;
     bool canFoldAsLoad : 1;
     bool mayLoad : 1;
     bool mayLoad_Unset : 1;
     bool mayStore : 1;
     bool mayStore_Unset : 1;
     bool mayRaiseFPException : 1;

llvm/utils/TableGen/CodeGenInstruction.cpp

CodeGenInstruction::CodeGenInstruction(Record *R)
   isIndirectBranch = R->getValueAsBit("isIndirectBranch");
   isCompare    = R->getValueAsBit("isCompare");
   isMoveImm    = R->getValueAsBit("isMoveImm");
   isMoveReg    = R->getValueAsBit("isMoveReg");
   isBitcast    = R->getValueAsBit("isBitcast");
   isSelect     = R->getValueAsBit("isSelect");
   isBarrier    = R->getValueAsBit("isBarrier");
   isCall       = R->getValueAsBit("isCall");
+  isIndirectCall = R->getValueAsBit("isIndirectCall");
   isAdd        = R->getValueAsBit("isAdd");
   isTrap       = R->getValueAsBit("isTrap");
   canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
   isPredicable = !R->getValueAsBit("isUnpredicable") && (
       Operands.isPredicable || R->getValueAsBit("isPredicable"));
   isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
   isCommutable = R->getValueAsBit("isCommutable");
   isTerminator = R->getValueAsBit("isTerminator");

llvm/utils/TableGen/InstrDocsEmitter.cpp

#define FLAG(f) if (II->f) { FlagStrings.push_back(str(f)); }
     FLAG(isBranch)
     FLAG(isIndirectBranch)
     FLAG(isCompare)
     FLAG(isMoveImm)
     FLAG(isBitcast)
     FLAG(isSelect)
     FLAG(isBarrier)
     FLAG(isCall)
+    FLAG(isIndirectCall)
     FLAG(isAdd)
     FLAG(isTrap)
     FLAG(canFoldAsLoad)
     FLAG(mayLoad)
     //FLAG(mayLoad_Unset) // Deliberately omitted.
     FLAG(mayStore)
     //FLAG(mayStore_Unset) // Deliberately omitted.
     FLAG(isPredicable)

llvm/utils/TableGen/InstrInfoEmitter.cpp

void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   if (Inst.isMoveReg)          OS << "|(1ULL<<MCID::MoveReg)";
   if (Inst.isBitcast)          OS << "|(1ULL<<MCID::Bitcast)";
   if (Inst.isAdd)              OS << "|(1ULL<<MCID::Add)";
   if (Inst.isTrap)             OS << "|(1ULL<<MCID::Trap)";
   if (Inst.isSelect)           OS << "|(1ULL<<MCID::Select)";
   if (Inst.isBarrier)          OS << "|(1ULL<<MCID::Barrier)";
   if (Inst.hasDelaySlot)       OS << "|(1ULL<<MCID::DelaySlot)";
   if (Inst.isCall)             OS << "|(1ULL<<MCID::Call)";
+  if (Inst.isIndirectCall)     OS << "|(1ULL<<MCID::IndirectCall)";
   if (Inst.canFoldAsLoad)      OS << "|(1ULL<<MCID::FoldableAsLoad)";
   if (Inst.mayLoad)            OS << "|(1ULL<<MCID::MayLoad)";
   if (Inst.mayStore)           OS << "|(1ULL<<MCID::MayStore)";
   if (Inst.mayRaiseFPException) OS << "|(1ULL<<MCID::MayRaiseFPException)";
   if (Inst.isPredicable)       OS << "|(1ULL<<MCID::Predicable)";
   if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)";
   if (Inst.isCommutable)       OS << "|(1ULL<<MCID::Commutable)";
   if (Inst.isTerminator)       OS << "|(1ULL<<MCID::Terminator)";