[PowerPC] support loop ds form prep for lwa

[shchenz]

Summary

This patch supports loop ds form prep for PPC instruction lwa.

[nemanjai]

Other than the minor nit about readability, LGTM.

llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp

850

This expression is quite unwieldy. The repeated calls to PtrValue->getType()->getPointerElementType() just look a bit messy. It would make sense to define a local variable to simplify this condition.

[shchenz]

llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp

850

will do this in commit patch.

llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp

if (PtrValue->getType()->getPointerElementType()->isIntegerTy(64)) {
       }
     }
     return true;
   };
   
   // Check if a load/store has DS form.
   auto isDSFormCandidate = [] (const Instruction *I, const Value *PtrValue) {
     assert((PtrValue && I) && "Invalid parameter!");
-    // FIXME: 32 bit instruction lwa is also DS form.
     return !isa<IntrinsicInst>(I) &&
            ((PtrValue->getType()->getPointerElementType()->isIntegerTy(64)) ||
             (PtrValue->getType()->getPointerElementType()->isFloatTy()) ||
-            (PtrValue->getType()->getPointerElementType()->isDoubleTy()));
+            (PtrValue->getType()->getPointerElementType()->isDoubleTy()) ||
+            (PtrValue->getType()->getPointerElementType()->isIntegerTy(32) &&
+             llvm::any_of(I->users(),
+                          [](const User *U) { return isa<SExtInst>(U); })));
   };
 
   // Check if a load/store has DQ form.
   auto isDQFormCandidate = [&] (const Instruction *I, const Value *PtrValue) {
     assert((PtrValue && I) && "Invalid parameter!");
     return !isa<IntrinsicInst>(I) && ST && ST->hasP9Vector() &&
            (PtrValue->getType()->getPointerElementType()->isVectorTy());
   };

llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll

 ;     long long x4 = *(int *)(p + i + DISP4);
 ;     res += x1*x2*x3*x4;
 ;   }
 ;   return res + count;
 ; }
 
 define i64 @test_ds_lwa_prep(i8* %0, i32 signext %1) {
 ; CHECK-LABEL: test_ds_lwa_prep:
-; CHECK:         li r6, 1
-; CHECK-NEXT:    li r7, 2
-; CHECK-NEXT:    li r8, 6
-; CHECK-NEXT:    li r9, 10
+; CHECK:         addi r5, r3, 2
+; CHECK:         li r6, -1
 ; CHECK:       .LBB9_2: #
-; CHECK-NEXT:    lwax r11, r3, r6
-; CHECK-NEXT:    lwax r12, r3, r7
-; CHECK-NEXT:    lwax r0, r3, r8
-; CHECK-NEXT:    addi r10, r3, 1
-; CHECK-NEXT:    mulld r11, r12, r11
-; CHECK-NEXT:    lwax r3, r3, r9
-; CHECK-NEXT:    mulld r11, r11, r0
-; CHECK-NEXT:    maddld r5, r11, r3, r5
-; CHECK-NEXT:    mr r3, r10
+; CHECK-NEXT:    lwax r7, r5, r6
+; CHECK-NEXT:    lwa r8, 0(r5)
+; CHECK-NEXT:    lwa r9, 4(r5)
+; CHECK-NEXT:    lwa r10, 8(r5)
+; CHECK-NEXT:    addi r5, r5, 1
+; CHECK-NEXT:    mulld r7, r8, r7
+; CHECK-NEXT:    mulld r7, r7, r9
+; CHECK-NEXT:    maddld r3, r7, r10, r3
 ; CHECK-NEXT:    bdnz .LBB9_2
 
   %3 = sext i32 %1 to i64
   %4 = icmp sgt i32 %1, 0
   br i1 %4, label %5, label %31
 
 5:                                                ; preds = %2, %5
   %6 = phi i64 [ %29, %5 ], [ 0, %2 ]
5:                                                ; preds = %2, %5
   %30 = icmp eq i64 %29, %3
   br i1 %30, label %31, label %5
 
 31:                                               ; preds = %5, %2
   %32 = phi i64 [ 0, %2 ], [ %28, %5 ]
   %33 = add nsw i64 %32, %3
   ret i64 %33
 }
+