[AArch64][SVE] Add patterns for scalable vselect

[cameron.mcinally]

Summary

This patch matches scalable vector selects to predicated move instructions.

[efriedma]

LGTM

On a sort of related note, AArch64ISelLowering.cpp says that MVT::nxv1f32 and MVT::nxv1f64 are also legal? Do we plan to implement isel patterns for them?

[c-rhodes]

In D71298#1778345, @efriedma wrote:

On a sort of related note, AArch64ISelLowering.cpp says that MVT::nxv1f32 and MVT::nxv1f64 are also legal? Do we plan to implement isel patterns for them?

nxv1f32 and nxv1f64 shouldn't be legal types, that was a mistake on my part
when implementing the initial calling convention for SVE. We avoid nxv1<eltty>
types as they can't be split if the element type is too big. We've also not had
to worry about these types from a vectorization point of view because the
vectorizer normally only generates VF=1 to indicate it wants to scalarize the
loop and in practice there is little value from vectorization when VF=vscale*1

MVT::nxv2f16 and MVT::nxv4f16 are legal types however so maybe it's worth
adding isel patterns for those in this patch?

I'll create a patch to remove nxv1f32 and nxv1f64 as legal types.

llvm/test/CodeGen/AArch64/sve-select.ll

1

Can this be removed? (I'm not sure if this test was generated?)

8–11

nit: can the CHECK lines be shifted down a couple of lines to the function body? It would be a little easier to read.

[sdesmalen]

Thanks for adding these patterns @cameron.mcinally !

llvm/test/CodeGen/AArch64/sve-select.ll

20

nit: the check for the basic-block seems unnecessary.

[cameron.mcinally]

llvm/test/CodeGen/AArch64/sve-select.ll

1

These were automatically generated...

8–11

And, yeah, I thought that was weird too. That's what update_llc_test_checks produced. I also see it in some other generated tests as well.

20

I can hand edit these if everyone wants that.

[cameron.mcinally]

llvm/test/CodeGen/AArch64/sve-select.ll

20

llvm-dev says that this is the intended behavior. The fix is to put the function declaration on one line. That seems a little excessive for a case like this though.

I'll manually edit the CHECK lines and remove the automatic header note...

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE] in {
   defm DUP_ZR  : sve_int_perm_dup_r<"dup", AArch64dup>;
   defm DUP_ZZI : sve_int_perm_dup_i<"dup">;
 
   // Splat scalar register (predicated)
   defm CPY_ZPmR : sve_int_perm_cpy_r<"cpy">;
   defm CPY_ZPmV : sve_int_perm_cpy_v<"cpy">;
 
   // Select elements from either vector (predicated)
-  defm SEL_ZPZZ    : sve_int_sel_vvv<"sel">;
+  defm SEL_ZPZZ    : sve_int_sel_vvv<"sel", vselect>;
 
   defm SPLICE_ZPZ : sve_int_perm_splice<"splice">;
   defm COMPACT_ZPZ : sve_int_perm_compact<"compact">;
   defm INSR_ZR : sve_int_perm_insrs<"insr", AArch64insr>;
   defm INSR_ZV : sve_int_perm_insrv<"insr", AArch64insr>;
   def  EXT_ZZI : sve_int_perm_extract_i<"ext">;
 
   defm RBIT_ZPmZ : sve_int_perm_rev_rbit<"rbit", int_aarch64_sve_rbit>;

llvm/lib/Target/AArch64/SVEInstrFormats.td

: I<(outs zprty:$Zd), (ins PPRAny:$Pg, zprty:$Zn, zprty:$Zm),
   let Inst{21}    = 0b1;
   let Inst{20-16} = Zm;
   let Inst{15-14} = 0b11;
   let Inst{13-10} = Pg;
   let Inst{9-5}   = Zn;
   let Inst{4-0}   = Zd;
 }
 
-multiclass sve_int_sel_vvv<string asm> {
+multiclass sve_int_sel_vvv<string asm, SDPatternOperator op> {
   def _B : sve_int_sel_vvv<0b00, asm, ZPR8>;
   def _H : sve_int_sel_vvv<0b01, asm, ZPR16>;
   def _S : sve_int_sel_vvv<0b10, asm, ZPR32>;
   def _D : sve_int_sel_vvv<0b11, asm, ZPR64>;
 
+  def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
+  def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1,  nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
+  def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1,  nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
+  def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1,  nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
+
+  def : SVE_3_Op_Pat<nxv8f16, op, nxv8i1,  nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
+  def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1,  nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
+  def : SVE_3_Op_Pat<nxv2f32, op, nxv2i1,  nxv2f32, nxv2f32, !cast<Instruction>(NAME # _D)>;
+  def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1,  nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
+
   def : InstAlias<"mov $Zd, $Pg/m, $Zn",
                   (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Zn",
                   (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Zn",
                   (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Zn",
                   (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd), 1>;

llvm/test/CodeGen/AArch64/sve-select.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+; Integer vector select
+
+define <vscale x 16 x i8> @sel_nxv16i8(<vscale x 16 x i1> %p,
+; CHECK-LABEL: sel_nxv16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.b, p0/m, z1.b
+; CHECK-NEXT:    ret
+                                       <vscale x 16 x i8> %dst,
+                                       <vscale x 16 x i8> %a) {
+  %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %dst
+  ret <vscale x 16 x i8> %sel
+}
+
+define <vscale x 8 x i16> @sel_nxv8i16(<vscale x 8 x i1> %p,
+; CHECK-LABEL: sel_nxv8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.h, p0/m, z1.h
+; CHECK-NEXT:    ret
+                                       <vscale x 8 x i16> %dst,
+                                       <vscale x 8 x i16> %a) {
+  %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %a, <vscale x 8 x i16> %dst
+  ret <vscale x 8 x i16> %sel
+}
+
+define <vscale x 4 x i32> @sel_nxv4i32(<vscale x 4 x i1> %p,
+; CHECK-LABEL: sel_nxv4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.s, p0/m, z1.s
+; CHECK-NEXT:    ret
+                                       <vscale x 4 x i32> %dst,
+                                       <vscale x 4 x i32> %a) {
+  %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %a, <vscale x 4 x i32> %dst
+  ret <vscale x 4 x i32> %sel
+}
+
+define <vscale x 2 x i64> @sel_nxv2i64(<vscale x 2 x i1> %p,
+; CHECK-LABEL: sel_nxv2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.d, p0/m, z1.d
+; CHECK-NEXT:    ret
+                                       <vscale x 2 x i64> %dst,
+                                       <vscale x 2 x i64> %a) {
+  %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %a, <vscale x 2 x i64> %dst
+  ret <vscale x 2 x i64> %sel
+}
+
+; Floating point vector select
+
+define <vscale x 8 x half> @sel_nxv8f16(<vscale x 8 x i1> %p,
+; CHECK-LABEL: sel_nxv8f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.h, p0/m, z1.h
+; CHECK-NEXT:    ret
+                                        <vscale x 8 x half> %dst,
+                                        <vscale x 8 x half> %a) {
+  %sel = select <vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %dst
+  ret <vscale x 8 x half> %sel
+}
+
+define <vscale x 4 x float> @sel_nxv4f32(<vscale x 4 x i1> %p,
+; CHECK-LABEL: sel_nxv4f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.s, p0/m, z1.s
+; CHECK-NEXT:    ret
+                                         <vscale x 4 x float> %dst,
+                                         <vscale x 4 x float> %a) {
+  %sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %dst
+  ret <vscale x 4 x float> %sel
+}
+
+define <vscale x 2 x float> @sel_nxv2f32(<vscale x 2 x i1> %p,
+; CHECK-LABEL: sel_nxv2f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.d, p0/m, z1.d
+; CHECK-NEXT:    ret
+                                         <vscale x 2 x float> %dst,
+                                         <vscale x 2 x float> %a) {
+  %sel = select <vscale x 2 x i1> %p, <vscale x 2 x float> %a, <vscale x 2 x float> %dst
+  ret <vscale x 2 x float> %sel
+}
+
+define <vscale x 2 x double> @sel_nxv8f64(<vscale x 2 x i1> %p,
+; CHECK-LABEL: sel_nxv8f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.d, p0/m, z1.d
+; CHECK-NEXT:    ret
+                                          <vscale x 2 x double> %dst,
+                                          <vscale x 2 x double> %a) {
+  %sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> %a, <vscale x 2 x double> %dst
+  ret <vscale x 2 x double> %sel
+}