This patch matches scalable vector selects to predicated move instructions.
nxv1f32 and nxv1f64 shouldn't be legal types, that was a mistake on my part
when implementing the initial calling convention for SVE. We avoid nxv1<eltty>
types as they can't be split if the element type is too big. We've also not had
to worry about these types from a vectorization point of view because the
vectorizer normally only generates VF=1 to indicate it wants to scalarize the
loop and in practice there is little value from vectorization when VF=vscale*1
MVT::nxv2f16 and MVT::nxv4f16 are legal types however so maybe it's worth
adding isel patterns for those in this patch?
I'll create a patch to remove nxv1f32 and nxv1f64 as legal types.
Can this be removed? (I'm not sure if this test was generated?)
nit: can the CHECK lines be shifted down a couple of lines to the function body? It would be a little easier to read.
llvm-dev says that this is the intended behavior. The fix is to put the function declaration on one line. That seems a little excessive for a case like this though.
I'll manually edit the CHECK lines and remove the automatic header note...