[PowerPC] Fix %llvm.ppc.altivec.vc* lowering

[vddvss]

Summary

r372285 changed LLVM to use a TargetConstant for parameters of intrinsics that are required to be immediates.

Since that commit, use of %llvm.ppc.altivec.vc{fsx,fux,tsxs,tuxs} intrinsics has not worked, and resulted in a LLVM ERROR: Cannot select: intrinsic %llvm.ppc.altivec.vc* error. The intrinsics' TableGen definitions matched on imm instead of timm.

This commit updates those definitions to use timm.

Fixes: https://llvm.org/PR44239

[Jim]

Link http://llvm.org/44239 is not available.

[qiucf]

In D71138#1782976, @Jim wrote:

Link http://llvm.org/44239 is not available.

That should be https://bugs.llvm.org/show_bug.cgi?id=44239 ?

[Jim]

LGTM, I have verified it.

[vddvss]

Oops, sorry about the typo in the URL. When ready, could someone please land for me? Thanks!

[Jim]

I have committed this patch for you.
If you are interested in obtaining the commit right. you can refer to https://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access.

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

 def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                      "vandc $vD, $vA, $vB", IIC_VecFP,
                      [(set v4i32:$vD, (and v4i32:$vA,
                                            (vnot_ppc v4i32:$vB)))]>;
 
 def VCFSX  : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
                       "vcfsx $vD, $vB, $UIMM", IIC_VecFP,
                       [(set v4f32:$vD,
-                             (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>;
+                             (int_ppc_altivec_vcfsx v4i32:$vB, timm:$UIMM))]>;
 def VCFUX  : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
                       "vcfux $vD, $vB, $UIMM", IIC_VecFP,
                       [(set v4f32:$vD,
-                             (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>;
+                             (int_ppc_altivec_vcfux v4i32:$vB, timm:$UIMM))]>;
 def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
                       "vctsxs $vD, $vB, $UIMM", IIC_VecFP,
                       [(set v4i32:$vD,
-                             (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>;
+                             (int_ppc_altivec_vctsxs v4f32:$vB, timm:$UIMM))]>;
 def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
                       "vctuxs $vD, $vB, $UIMM", IIC_VecFP,
                       [(set v4i32:$vD,
-                             (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>;
+                             (int_ppc_altivec_vctuxs v4f32:$vB, timm:$UIMM))]>;
 
 // Defines with the UIM field set to 0 for floating-point
 // to integer (fp_to_sint/fp_to_uint) conversions and integer
 // to floating-point (sint_to_fp/uint_to_fp) conversions.
 let isCodeGenOnly = 1, VA = 0 in {
 def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB),
                        "vcfsx $vD, $vB, 0", IIC_VecFP,
                        [(set v4f32:$vD,

llvm/test/CodeGen/PowerPC/pr44239.ll

+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s
+
+define <4 x float> @check_vcfsx(<4 x i32> %a) {
+entry:
+  %0 = tail call <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> %a, i32 1)
+  ret  <4 x float> %0
+; CHECK-LABEL: check_vcfsx
+; CHECK: vcfsx {{[0-9]+}}, {{[0-9]+}}, 1
+}
+
+define <4 x float> @check_vcfux(<4 x i32> %a) {
+entry:
+  %0 = tail call <4 x float> @llvm.ppc.altivec.vcfux(<4 x i32> %a, i32 1)
+  ret  <4 x float> %0
+; CHECK-LABEL: check_vcfux
+; CHECK: vcfux {{[0-9]+}}, {{[0-9]+}}, 1
+}
+
+define <4 x i32> @check_vctsxs(<4 x float> %a) {
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.altivec.vctsxs(<4 x float> %a, i32 1)
+  ret  <4 x i32> %0
+; CHECK-LABEL: check_vctsxs
+; CHECK: vctsxs {{[0-9]+}}, {{[0-9]+}}, 1
+}
+
+define <4 x i32> @check_vctuxs(<4 x float> %a) {
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.altivec.vctuxs(<4 x float> %a, i32 1)
+  ret  <4 x i32> %0
+; CHECK-LABEL: check_vctuxs
+; CHECK: vctuxs {{[0-9]+}}, {{[0-9]+}}, 1
+}
+
+declare <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32>, i32 immarg)
+declare <4 x float> @llvm.ppc.altivec.vcfux(<4 x i32>, i32 immarg)
+declare <4 x i32> @llvm.ppc.altivec.vctsxs(<4 x float>, i32 immarg)
+declare <4 x i32> @llvm.ppc.altivec.vctuxs(<4 x float>, i32 immarg)
+