[ARM][MVE] Fix copy-paste error in VQSHL instruction ids.

[simon_tatham]

Summary

The immediate forms of the MVE VQSHL instruction have MC names like
MVE_VSLIimms8 and MVE_VSLIimmu32. Those names are confusing,
because VSLI is a completely different shift instruction with no
semantic relation to VQSHL. But it just happens to be defined
immediately before VQSHL in ARMInstrMVE.td, so this looks like a
copy-paste error. Renamed the ids to match the instruction name.

llvm/lib/Target/ARM/ARMInstrMVE.td

: MVE_shift_with_imm<"vqshl", suffix, (outs MQPR:$Qd),
                        vpred_r, ""> {
   bits<6> imm;
 
   let Inst{25-24} = 0b11;
   let Inst{21-16} = imm;
   let Inst{10-8} = 0b111;
 }
 
-def MVE_VSLIimms8 : MVE_VQSHL_imm<"s8", (ins imm0_7:$imm)> {
+def MVE_VQSHLimms8 : MVE_VQSHL_imm<"s8", (ins imm0_7:$imm)> {
   let Inst{28} = 0b0;
   let Inst{21-19} = 0b001;
 }
 
-def MVE_VSLIimmu8 : MVE_VQSHL_imm<"u8", (ins imm0_7:$imm)> {
+def MVE_VQSHLimmu8 : MVE_VQSHL_imm<"u8", (ins imm0_7:$imm)> {
   let Inst{28} = 0b1;
   let Inst{21-19} = 0b001;
 }
 
-def MVE_VSLIimms16 : MVE_VQSHL_imm<"s16", (ins imm0_15:$imm)> {
+def MVE_VQSHLimms16 : MVE_VQSHL_imm<"s16", (ins imm0_15:$imm)> {
   let Inst{28} = 0b0;
   let Inst{21-20} = 0b01;
 }
 
-def MVE_VSLIimmu16 : MVE_VQSHL_imm<"u16", (ins imm0_15:$imm)> {
+def MVE_VQSHLimmu16 : MVE_VQSHL_imm<"u16", (ins imm0_15:$imm)> {
   let Inst{28} = 0b1;
   let Inst{21-20} = 0b01;
 }
 
-def MVE_VSLIimms32 : MVE_VQSHL_imm<"s32", (ins imm0_31:$imm)> {
+def MVE_VQSHLimms32 : MVE_VQSHL_imm<"s32", (ins imm0_31:$imm)> {
   let Inst{28} = 0b0;
   let Inst{21} = 0b1;
 }
 
-def MVE_VSLIimmu32 : MVE_VQSHL_imm<"u32", (ins imm0_31:$imm)> {
+def MVE_VQSHLimmu32 : MVE_VQSHL_imm<"u32", (ins imm0_31:$imm)> {
   let Inst{28} = 0b1;
   let Inst{21} = 0b1;
 }
 
 class MVE_VQSHLU_imm<string suffix, dag imm>
   : MVE_shift_with_imm<"vqshlu", suffix, (outs MQPR:$Qd),
                        !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
                        vpred_r, ""> {

llvm/unittests/Target/ARM/MachineInstrTest.cpp

auto IsValidTPOpcode = [](unsigned Opcode) {
     case MVE_VQRSHL_qrs32:
     case MVE_VQRSHL_qrs8:
     case MVE_VQRSHL_qru16:
     case MVE_VQRSHL_qru8:
     case MVE_VQRSHL_qru32:
     case MVE_VQSHLU_imms16:
     case MVE_VQSHLU_imms32:
     case MVE_VQSHLU_imms8:
+    case MVE_VQSHLimms16:
+    case MVE_VQSHLimms32:
+    case MVE_VQSHLimms8:
+    case MVE_VQSHLimmu16:
+    case MVE_VQSHLimmu32:
+    case MVE_VQSHLimmu8:
     case MVE_VQSHL_by_vecs16:
     case MVE_VQSHL_by_vecs32:
     case MVE_VQSHL_by_vecs8:
     case MVE_VQSHL_by_vecu16:
     case MVE_VQSHL_by_vecu32:
     case MVE_VQSHL_by_vecu8:
     case MVE_VQSHL_qrs16:
     case MVE_VQSHL_qrs32:
auto IsValidTPOpcode = [](unsigned Opcode) {
     case MVE_VSHR_imms32:
     case MVE_VSHR_imms8:
     case MVE_VSHR_immu16:
     case MVE_VSHR_immu32:
     case MVE_VSHR_immu8:
     case MVE_VSLIimm16:
     case MVE_VSLIimm32:
     case MVE_VSLIimm8:
-    case MVE_VSLIimms16:  
-    case MVE_VSLIimms32:
-    case MVE_VSLIimms8:
-    case MVE_VSLIimmu16:
-    case MVE_VSLIimmu32:
-    case MVE_VSLIimmu8:
     case MVE_VSRIimm16:
     case MVE_VSRIimm32:
     case MVE_VSRIimm8:
     case MVE_VSTRB16:
     case MVE_VSTRB16_post:
     case MVE_VSTRB16_pre:
     case MVE_VSTRB16_rq:
     case MVE_VSTRB32: