[PowerPC] Exploitate the Vector Integer Average Instructions

[steven.zhang]

Summary

PowerPC has instruction to do the semantics of this piece of code:

vector int foo(vector int m, vector int n) {
  return (m + n + 1) >> 1;
}

This patch is adding the match rule to select it.

[steven.zhang]

Gentle ping ...

[shchenz]

llvm/test/CodeGen/PowerPC/vavg.ll

4

It would be good if add some negative cases, like if the const operand is not splat of 1s.

[steven.zhang]

Add the negative tests.

[shchenz]

LGTM. Thanks for exploiting these instructions.

[lkail]

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

1102

nit: We'd better place pattern and result in different lines considering there might be many brackets.

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
   return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
 }]>;
 def vecspltisw : PatLeaf<(build_vector), [{
   return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != nullptr;
 }], VSPLTISW_get_imm>;
 
+def immEQOneV : PatLeaf<(build_vector), [{
+  if (ConstantSDNode *C = cast<BuildVectorSDNode>(N)->getConstantSplatNode())
+    return C->isOne();
+  return false;
+}]>;
 //===----------------------------------------------------------------------===//
 // Helpers for defining instructions that directly correspond to intrinsics.
 
 // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
   : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
               !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
                        [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>;
def : Pat<(v4i32 (vselect v4i32:$vA, v4i32:$vB, v4i32:$vC)),
           (VSEL $vC, $vB, $vA)>;
 def : Pat<(v2i64 (vselect v2i64:$vA, v2i64:$vB, v2i64:$vC)),
           (VSEL $vC, $vB, $vA)>;
 def : Pat<(v4f32 (vselect v4i32:$vA, v4f32:$vB, v4f32:$vC)),
           (VSEL $vC, $vB, $vA)>;
 def : Pat<(v2f64 (vselect v2i64:$vA, v2f64:$vB, v2f64:$vC)),
           (VSEL $vC, $vB, $vA)>;
 
+// Vector Integer Average Instructions
+def : Pat<(v4i32 (sra (sub v4i32:$vA, (vnot_ppc v4i32:$vB)),
+          (v4i32 (immEQOneV)))), (v4i32 (VAVGSW $vA, $vB))>;
+def : Pat<(v8i16 (sra (sub v8i16:$vA, (v8i16 (bitconvert(vnot_ppc v4i32:$vB)))),
+          (v8i16 (immEQOneV)))), (v8i16 (VAVGSH $vA, $vB))>;
+def : Pat<(v16i8 (sra (sub v16i8:$vA, (v16i8 (bitconvert(vnot_ppc v4i32:$vB)))),
+          (v16i8 (immEQOneV)))), (v16i8 (VAVGSB $vA, $vB))>;
+def : Pat<(v4i32 (srl (sub v4i32:$vA, (vnot_ppc v4i32:$vB)),
+          (v4i32 (immEQOneV)))), (v4i32 (VAVGUW $vA, $vB))>;
+def : Pat<(v8i16 (srl (sub v8i16:$vA, (v8i16 (bitconvert(vnot_ppc v4i32:$vB)))),
+          (v8i16 (immEQOneV)))), (v8i16 (VAVGUH $vA, $vB))>;
+def : Pat<(v16i8 (srl (sub v16i8:$vA, (v16i8 (bitconvert(vnot_ppc v4i32:$vB)))),
+          (v16i8 (immEQOneV)))), (v16i8 (VAVGUB $vA, $vB))>;
+
 } // end HasAltivec
 
 def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">;
 def HasP8Crypto : Predicate<"PPCSubTarget->hasP8Crypto()">;
 let Predicates = [HasP8Altivec] in {
 
 let isCommutable = 1 in {
 def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw,

llvm/test/CodeGen/PowerPC/vavg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-P9 %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck -check-prefix=CHECK-P8 %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-P7 %s
 define <8 x i16> @test_v8i16(<8 x i16> %m, <8 x i16> %n) {
 ; CHECK-P9-LABEL: test_v8i16:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    xxlnor 34, 34, 34
-; CHECK-P9-NEXT:    vspltish 4, 1
-; CHECK-P9-NEXT:    vsubuhm 2, 3, 2
-; CHECK-P9-NEXT:    vsrh 2, 2, 4
+; CHECK-P9-NEXT:    vavguh 2, 3, 2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_v8i16:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    xxlnor 34, 34, 34
-; CHECK-P8-NEXT:    vspltish 4, 1
-; CHECK-P8-NEXT:    vsubuhm 2, 3, 2
-; CHECK-P8-NEXT:    vsrh 2, 2, 4
+; CHECK-P8-NEXT:    vavguh 2, 3, 2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: test_v8i16:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    xxlnor 34, 34, 34
-; CHECK-P7-NEXT:    vspltish 4, 1
-; CHECK-P7-NEXT:    vsubuhm 2, 3, 2
-; CHECK-P7-NEXT:    vsrh 2, 2, 4
+; CHECK-P7-NEXT:    vavguh 2, 3, 2
 ; CHECK-P7-NEXT:    blr
 entry:
   %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %add1 = add <8 x i16> %add, %n
   %shr = lshr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   ret <8 x i16> %shr
 }
 
 define <8 x i16> @test_v8i16_sign(<8 x i16> %m, <8 x i16> %n) {
 ; CHECK-P9-LABEL: test_v8i16_sign:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    xxlnor 34, 34, 34
-; CHECK-P9-NEXT:    vspltish 4, 1
-; CHECK-P9-NEXT:    vsubuhm 2, 3, 2
-; CHECK-P9-NEXT:    vsrah 2, 2, 4
+; CHECK-P9-NEXT:    vavgsh 2, 3, 2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_v8i16_sign:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    xxlnor 34, 34, 34
-; CHECK-P8-NEXT:    vspltish 4, 1
-; CHECK-P8-NEXT:    vsubuhm 2, 3, 2
-; CHECK-P8-NEXT:    vsrah 2, 2, 4
+; CHECK-P8-NEXT:    vavgsh 2, 3, 2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: test_v8i16_sign:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    xxlnor 34, 34, 34
-; CHECK-P7-NEXT:    vspltish 4, 1
-; CHECK-P7-NEXT:    vsubuhm 2, 3, 2
-; CHECK-P7-NEXT:    vsrah 2, 2, 4
+; CHECK-P7-NEXT:    vavgsh 2, 3, 2
 ; CHECK-P7-NEXT:    blr
 entry:
   %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %add1 = add <8 x i16> %add, %n
   %shr = ashr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   ret <8 x i16> %shr
 }
 
 define <4 x i32> @test_v4i32(<4 x i32> %m, <4 x i32> %n) {
 ; CHECK-P9-LABEL: test_v4i32:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    xxlnor 34, 34, 34
-; CHECK-P9-NEXT:    vspltisw 4, 1
-; CHECK-P9-NEXT:    vsubuwm 2, 3, 2
-; CHECK-P9-NEXT:    vsrw 2, 2, 4
+; CHECK-P9-NEXT:    vavguw 2, 3, 2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_v4i32:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    xxlnor 34, 34, 34
-; CHECK-P8-NEXT:    vspltisw 4, 1
-; CHECK-P8-NEXT:    vsubuwm 2, 3, 2
-; CHECK-P8-NEXT:    vsrw 2, 2, 4
+; CHECK-P8-NEXT:    vavguw 2, 3, 2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: test_v4i32:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    xxlnor 34, 34, 34
-; CHECK-P7-NEXT:    vspltisw 4, 1
-; CHECK-P7-NEXT:    vsubuwm 2, 3, 2
-; CHECK-P7-NEXT:    vsrw 2, 2, 4
+; CHECK-P7-NEXT:    vavguw 2, 3, 2
 ; CHECK-P7-NEXT:    blr
 entry:
   %add = add <4 x i32> %m, <i32 1, i32 1, i32 1, i32 1>
   %add1 = add <4 x i32> %add, %n
   %shr = lshr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1>
   ret <4 x i32> %shr
 }
 
 define <4 x i32> @test_v4i32_sign(<4 x i32> %m, <4 x i32> %n) {
 ; CHECK-P9-LABEL: test_v4i32_sign:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    xxlnor 34, 34, 34
-; CHECK-P9-NEXT:    vspltisw 4, 1
-; CHECK-P9-NEXT:    vsubuwm 2, 3, 2
-; CHECK-P9-NEXT:    vsraw 2, 2, 4
+; CHECK-P9-NEXT:    vavgsw 2, 3, 2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_v4i32_sign:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    xxlnor 34, 34, 34
-; CHECK-P8-NEXT:    vspltisw 4, 1
-; CHECK-P8-NEXT:    vsubuwm 2, 3, 2
-; CHECK-P8-NEXT:    vsraw 2, 2, 4
+; CHECK-P8-NEXT:    vavgsw 2, 3, 2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: test_v4i32_sign:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    xxlnor 34, 34, 34
-; CHECK-P7-NEXT:    vspltisw 4, 1
-; CHECK-P7-NEXT:    vsubuwm 2, 3, 2
-; CHECK-P7-NEXT:    vsraw 2, 2, 4
+; CHECK-P7-NEXT:    vavgsw 2, 3, 2
 ; CHECK-P7-NEXT:    blr
 entry:
   %add = add <4 x i32> %m, <i32 1, i32 1, i32 1, i32 1>
   %add1 = add <4 x i32> %add, %n
   %shr = ashr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1>
   ret <4 x i32> %shr
 }
 
 define <16 x i8> @test_v16i8(<16 x i8> %m, <16 x i8> %n) {
 ; CHECK-P9-LABEL: test_v16i8:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    xxlnor 34, 34, 34
-; CHECK-P9-NEXT:    xxspltib 36, 1
-; CHECK-P9-NEXT:    vsububm 2, 3, 2
-; CHECK-P9-NEXT:    vsrb 2, 2, 4
+; CHECK-P9-NEXT:    vavgub 2, 3, 2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_v16i8:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    xxlnor 34, 34, 34
-; CHECK-P8-NEXT:    vspltisb 4, 1
-; CHECK-P8-NEXT:    vsububm 2, 3, 2
-; CHECK-P8-NEXT:    vsrb 2, 2, 4
+; CHECK-P8-NEXT:    vavgub 2, 3, 2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: test_v16i8:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    xxlnor 34, 34, 34
-; CHECK-P7-NEXT:    vspltisb 4, 1
-; CHECK-P7-NEXT:    vsububm 2, 3, 2
-; CHECK-P7-NEXT:    vsrb 2, 2, 4
+; CHECK-P7-NEXT:    vavgub 2, 3, 2
 ; CHECK-P7-NEXT:    blr
 entry:
   %add = add <16 x i8> %m, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %add1 = add <16 x i8> %add, %n
   %shr = lshr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   ret <16 x i8> %shr
 }
 
 define <16 x i8> @test_v16i8_sign(<16 x i8> %m, <16 x i8> %n) {
 ; CHECK-P9-LABEL: test_v16i8_sign:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    xxlnor 34, 34, 34
-; CHECK-P9-NEXT:    xxspltib 36, 1
-; CHECK-P9-NEXT:    vsububm 2, 3, 2
-; CHECK-P9-NEXT:    vsrab 2, 2, 4
+; CHECK-P9-NEXT:    vavgsb 2, 3, 2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_v16i8_sign:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    xxlnor 34, 34, 34
-; CHECK-P8-NEXT:    vspltisb 4, 1
-; CHECK-P8-NEXT:    vsububm 2, 3, 2
-; CHECK-P8-NEXT:    vsrab 2, 2, 4
+; CHECK-P8-NEXT:    vavgsb 2, 3, 2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: test_v16i8_sign:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    xxlnor 34, 34, 34
-; CHECK-P7-NEXT:    vspltisb 4, 1
-; CHECK-P7-NEXT:    vsububm 2, 3, 2
-; CHECK-P7-NEXT:    vsrab 2, 2, 4
+; CHECK-P7-NEXT:    vavgsb 2, 3, 2
 ; CHECK-P7-NEXT:    blr
 entry:
   %add = add <16 x i8> %m, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %add1 = add <16 x i8> %add, %n
   %shr = ashr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   ret <16 x i8> %shr
 }
+
+define <8 x i16> @test_v8i16_sign_negative(<8 x i16> %m, <8 x i16> %n) {
+; CHECK-P9-LABEL: test_v8i16_sign_negative:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
+; CHECK-P9-NEXT:    addi 3, 3, .LCPI6_0@toc@l
+; CHECK-P9-NEXT:    vadduhm 2, 2, 3
+; CHECK-P9-NEXT:    lxvx 35, 0, 3
+; CHECK-P9-NEXT:    vadduhm 2, 2, 3
+; CHECK-P9-NEXT:    vspltish 3, 1
+; CHECK-P9-NEXT:    vsrah 2, 2, 3
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: test_v8i16_sign_negative:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
+; CHECK-P8-NEXT:    vadduhm 2, 2, 3
+; CHECK-P8-NEXT:    vspltish 4, 1
+; CHECK-P8-NEXT:    addi 3, 3, .LCPI6_0@toc@l
+; CHECK-P8-NEXT:    lvx 3, 0, 3
+; CHECK-P8-NEXT:    vadduhm 2, 2, 3
+; CHECK-P8-NEXT:    vsrah 2, 2, 4
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P7-LABEL: test_v8i16_sign_negative:
+; CHECK-P7:       # %bb.0: # %entry
+; CHECK-P7-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
+; CHECK-P7-NEXT:    vadduhm 2, 2, 3
+; CHECK-P7-NEXT:    vspltish 4, 1
+; CHECK-P7-NEXT:    addi 3, 3, .LCPI6_0@toc@l
+; CHECK-P7-NEXT:    lvx 3, 0, 3
+; CHECK-P7-NEXT:    vadduhm 2, 2, 3
+; CHECK-P7-NEXT:    vsrah 2, 2, 4
+; CHECK-P7-NEXT:    blr
+entry:
+  %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 -1, i16 1, i16 1, i16 1, i16 1>
+  %add1 = add <8 x i16> %add, %n
+  %shr = ashr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %shr
+}
+
+define <4 x i32> @test_v4i32_negative(<4 x i32> %m, <4 x i32> %n) {
+; CHECK-P9-LABEL: test_v4i32_negative:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    xxlnor 34, 34, 34
+; CHECK-P9-NEXT:    vsubuwm 2, 3, 2
+; CHECK-P9-NEXT:    vspltisw 3, 2
+; CHECK-P9-NEXT:    vsrw 2, 2, 3
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: test_v4i32_negative:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    xxlnor 34, 34, 34
+; CHECK-P8-NEXT:    vspltisw 4, 2
+; CHECK-P8-NEXT:    vsubuwm 2, 3, 2
+; CHECK-P8-NEXT:    vsrw 2, 2, 4
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P7-LABEL: test_v4i32_negative:
+; CHECK-P7:       # %bb.0: # %entry
+; CHECK-P7-NEXT:    xxlnor 34, 34, 34
+; CHECK-P7-NEXT:    vspltisw 4, 2
+; CHECK-P7-NEXT:    vsubuwm 2, 3, 2
+; CHECK-P7-NEXT:    vsrw 2, 2, 4
+; CHECK-P7-NEXT:    blr
+entry:
+  %add = add <4 x i32> %m, <i32 1, i32 1, i32 1, i32 1>
+  %add1 = add <4 x i32> %add, %n
+  %shr = lshr <4 x i32> %add1, <i32 2, i32 2, i32 2, i32 2>
+  ret <4 x i32> %shr
+}
+
+define <4 x i32> @test_v4i32_sign_negative(<4 x i32> %m, <4 x i32> %n) {
+; CHECK-P9-LABEL: test_v4i32_sign_negative:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    vadduwm 2, 2, 3
+; CHECK-P9-NEXT:    xxleqv 35, 35, 35
+; CHECK-P9-NEXT:    vadduwm 2, 2, 3
+; CHECK-P9-NEXT:    vspltisw 3, 1
+; CHECK-P9-NEXT:    vsraw 2, 2, 3
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: test_v4i32_sign_negative:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    xxleqv 36, 36, 36
+; CHECK-P8-NEXT:    vadduwm 2, 2, 3
+; CHECK-P8-NEXT:    vspltisw 3, 1
+; CHECK-P8-NEXT:    vadduwm 2, 2, 4
+; CHECK-P8-NEXT:    vsraw 2, 2, 3
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P7-LABEL: test_v4i32_sign_negative:
+; CHECK-P7:       # %bb.0: # %entry
+; CHECK-P7-NEXT:    vspltisb 4, -1
+; CHECK-P7-NEXT:    vadduwm 2, 2, 3
+; CHECK-P7-NEXT:    vspltisw 3, 1
+; CHECK-P7-NEXT:    vadduwm 2, 2, 4
+; CHECK-P7-NEXT:    vsraw 2, 2, 3
+; CHECK-P7-NEXT:    blr
+entry:
+  %add = add <4 x i32> %m, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %add1 = add <4 x i32> %add, %n
+  %shr = ashr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %shr
+}