[Power8] Add the MacroFusion support for Power8

[steven.zhang]

Summary

Power8 User's Manual Section 10.1.12 Instruction Fusion

There are two fuse types:
  {addi} followed by one of these {lxvd2x, lxvw4x, lxvdsx, lvebx, lvehx, lvewx, lvx, lxsdx}
  Requirements:
    addi(rt) = lxvd2x(rb)
    lxvd2x(ra) cannot be ‘0’
  Result:
    addi - no changelxvd2x gets the immed field from addi., rb is not used.This effectively provides a d-form version for the vector loads.The dependency between the two operations is removed.
  {addis) followed by one of these {ld, lbz, lhz, lwz}
  Requirements:
    addis(rt) = ld(ra) = ld(rt) - (cannot be ‘0’)
    addis(SI) first 12 bits must be all 0’s or all 1’sTA = 0 for this fusion to occur and if SI = 111111111110000 and the msb of the d/ds field of the load equals ‘1’, then fusion does not occur.
  Result:addis gets changed to a NOP. (It still takes up a dispatch slot, but is sent directly to completion.)The last 5 bits of addis(SI) are sent with the ld (information from the addis is passed to the ld).The addis is removed from execution.

This patch is intend to implement the missing P8 MacroFusion for LLVM.

[jsji]

Looks mostly good to me. But maybe we should seperate a new NFC patch before this.
Also can we get some testcases?

llvm/lib/Target/PowerPC/PPC.td

170

No . for others, why we need one here? :)

257

I like the idea of separating the inheritable feature and sub-target specific feature.
However, I think this should be done in an NFC patch before this.

And it looks confusing to me about having Power8SpecificFeatures and Power8OnlyFeature,
are P8 specific feature supposed to be P8 only?

Maybe we should align with X86, name them: P8InheritableFeatures , P*AdditionalFeatures , P*SpecificFeatures/P*OnlyFeatures?

llvm/lib/Target/PowerPC/PPCMacroFusion.cpp

21

Is it better to put this into PPC namespace instead of anonymous namespace?

[steven.zhang]

llvm/lib/Target/PowerPC/PPC.td

257

Good point.

[steven.zhang]

https://reviews.llvm.org/D70768 is created for the NFC patch.

llvm/lib/Target/PowerPC/PPC.td

170

It is typo.

llvm/lib/Target/PowerPC/PPCMacroFusion.cpp

21

As it is used internally and I don't want to pollute the PPC namespace. Anonymous namespace is fine from what I think.

[steven.zhang]

Update the patch according to Jinsong's comments.

[kbarton]

llvm/lib/Target/PowerPC/PPCMacroFusion.cpp

64

function names should be verb phrases (e.g., getKind()).
https://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly

80

Could you document what the return type means?

137

From reading the code, it seems like returning true from this function means that they should be scheduled together.
Thus, this function defaults to fusing instructions if it comes across something it doesn't understand (and asserts are not enabled). Would it not be better to return false here, and let the existing scheduling heuristics decide whether to make the instructions adjacent?

140

The preference is to not use \brief, and instead use a single sentence for the abstract and then follow-on details in a separate paragraph:

The first sentence (or a paragraph beginning with \brief) is used as an abstract. Try to use a single sentence as the \brief adds visual clutter. Put detailed discussion into separate paragraphs.

(https://llvm.org/docs/CodingStandards.html#doxygen-use-in-documentation-comments)

160

Unless I'm missing something, for each call to shouldScheduleAdjacent for a given pair of instructions, we are going to walk all features in the FusionFeatures list. Is that correct?
If that's the case, I think this could be problematic (N*M where N is the number of pairs we want to check and M is the number of fusion features we have).

Is it possible to change the FusionFeatures list to use a map instead of an array, and use one of the instructions as a key into the map?

Also, how often do we want to check if the SecondMI is fusable without specifying a FirstMI? Is this a common case or an exceptional case?

161

I don't consider this an early return, this is just skipping it if it is not supported.

162

Is it possible to check for this earlier (e.g., when creating the FusionFeatures structure) and if it is not supported simply do not add it into the structure?

[steven.zhang]

Update the patch according to Kit's comments. Thank you!

llvm/lib/Target/PowerPC/PPCMacroFusion.cpp

64

Done.

80

Done

137

When the checkOpConstraints() is called, we have got the fusion pair(FirstMI and SecondMI are fusion pair according to opcode). What we need to do is to kick some situation that we are sure that, it is NOT a fusion pair according to the spec. So, we have to return true by default unless we have the reason(i.e. the switch case) to say, it is NOT a fusion pair, as this is the last check.

140

Good catch. Done.

160

You are completely correct and yes, we need N*M complexity as you point out. However, this is NOT a 1:1 map, because, one instruction could be fused by multiple fusion pair. i.e. ( addi + load, addi + addis).

And in fact, it is a map between two groups. { inst1, inst2, inst3, ... } and { inst4, inst 6, ...}. Any instructions in group 1 is fused with any instructions in group2. And the FusionFeature is the data structure to map these two group. And we have an array of these maps. So, we have to walk all the element to find out all the maps with the instruction as the key. It would be great if we can reduce the complexity with better data structure.

For the case that without specifying the FirstMI, it is used to find the anchor instruction that we want to fuse. Then, MacroFusion will walk all the instructions pred that anchor instruction to check if they can be fused. It is not special case but the way that MacroFusion used to get the FirstMI.

• List Item

161

Good catch.

162

We cannot, as we need to enable/disable each feature at runtime by option -mattr=[feature].

[qiucf]

llvm/lib/Target/PowerPC/PPCMacroFusion.cpp

160

I think it's feasible to build a radix tree instead of array of sets for better performance, which can be done by either using helper methods (like defineRule(definePattern(...), definePattern(...))) or using tblgen. But since the number of patterns here aren't so large, this looks fine to me.

178

I think we still need some comments here explaining what would be checked in the mutation if we provide a negative depOpIdx. It might confuse someone to think here we have NO checks on registers at all.

[steven.zhang]

The best way to do this is to add a tblgen backend which consume the TD that describe the fused instruction and produce a table that has 1:1 map for all the fused instruction pair. However, it is overkill I think. And in fact, we could add a multiple map to map one opcode with several fusion candidates but I don't think it is a good idea as we only have small groups of fusion candidates.

[steven.zhang]

Hi, Kit @kbarton I have addressed your comments, would you please continue the review now ? Thank you!

[kbarton]

Could you please rebase this patch?
It no longer applies cleanly, since you committed https://reviews.llvm.org/D70768.

llvm/lib/Target/PowerPC/PPCMacroFusion.cpp

137

Could you please explain this in the comments to the function?

Also, is it possible to add an assert at the checking that FirstMI and SecondMI are a valid fusion pair? This will validate your assumption, and also prevent the function from being used erroneously in the future.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCMacroFusion.cpp

137

ok, I will do it.

[steven.zhang]

Address comments.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCMacroFusion.cpp

137

I have added the comments in the default case to explain why it returns true. Regarding to the assertion you mentioned, it is not easy to add it as all other conditions are within shouldScheduleAdjacent() and we are called by it also. I think, as this is a static function and we have the context of the call, it is not a big issue if we didn't add the assertion. This is the context of this call:

shouldScheduleAdjacent() {

 foreach fusion candidates {
   if (cannot fuse)
       continue
    
    if (checkOpConstraints(...))
        return true;
}
}

[steven.zhang]

Ping...

[steven.zhang]

ping

[kbarton]

LGTM.
I apologize for the delay in getting to this.

llvm/lib/Target/PowerPC/CMakeLists.txt

add_llvm_target(PowerPCCodeGen
   PPCISelLowering.cpp
   PPCEarlyReturn.cpp
   PPCFastISel.cpp
   PPCFrameLowering.cpp
   PPCLoopInstrFormPrep.cpp
   PPCMCInstLower.cpp
   PPCMachineFunctionInfo.cpp
   PPCMachineScheduler.cpp
+  PPCMacroFusion.cpp
   PPCMIPeephole.cpp
   PPCRegisterInfo.cpp
   PPCQPXLoadSplat.cpp
   PPCSubtarget.cpp
   PPCTargetMachine.cpp
   PPCTargetObjectFile.cpp
   PPCTargetTransformInfo.cpp
   PPCTOCRegDeps.cpp

llvm/lib/Target/PowerPC/PPC.td

SubtargetFeature<"invariant-function-descriptors",
                    "HasInvariantFunctionDescriptors", "true",
                    "Assume function descriptors are invariant">;
 def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
                                        "Always use indirect calls">;
 def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
                                   "Enable Hardware Transactional Memory instructions">;
 def FeatureMFTB   : SubtargetFeature<"", "FeatureMFTB", "true",
                                         "Implement mftb using the mfspr instruction">;
+def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
+                                     "Target supports instruction fusion">;
+def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load",
+                                             "HasAddiLoadFusion", "true",
+                                             "Power8 Addi-Load fusion",
+                                             [FeatureFusion]>;
+def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load",
+                                              "HasAddisLoadFusion", "true",
+                                              "Power8 Addis-Load fusion",
+                                              [FeatureFusion]>;
 def FeatureUnalignedFloats :
   SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
                    "true", "CPU does not trap on unaligned FP access">;
 def FeaturePPCPreRASched:
   SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
                    "Use PowerPC pre-RA scheduling strategy">;
 def FeaturePPCPostRASched:
   SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",

 // used elsewhere.
 def ProcessorFeatures {
   // Power7
   list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7,
                                                   FeatureAltivec,
                                                   FeatureVSX,
                                                   FeatureMFOCRF,
                                                   FeatureFCPSGN,
                                                   FeatureFSqrt,
                                                   FeatureFRE,
                                                   FeatureFRES,
                                                   FeatureFRSQRTE,
                                                   FeatureFRSQRTES,
                                                   FeatureRecipPrec,
                                                   FeatureSTFIWX,
                                                   FeatureLFIWAX,
                                                   FeatureFPRND,
def ProcessorFeatures {
   list<SubtargetFeature> P8AdditionalFeatures = [DirectivePwr8,
                                                  FeatureP8Altivec,
                                                  FeatureP8Vector,
                                                  FeatureP8Crypto,
                                                  FeatureHTM,
                                                  FeatureDirectMove,
                                                  FeatureICBT,
                                                  FeaturePartwordAtomic];
-  list<SubtargetFeature> P8SpecificFeatures = [];
+  list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion,
+                                               FeatureAddisLoadFusion];
   list<SubtargetFeature> P8InheritableFeatures =
     !listconcat(P7InheritableFeatures, P8AdditionalFeatures);
   list<SubtargetFeature> P8Features =
     !listconcat(P8InheritableFeatures, P8SpecificFeatures);
 
   // Power9
   list<SubtargetFeature> P9AdditionalFeatures = [DirectivePwr9,
                                                  FeatureP9Altivec,

llvm/lib/Target/PowerPC/PPCMacroFusion.h

+//===- PPCMacroFusion.h - PowerPC Macro Fusion ----------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file This file contains the PowerPC definition of the DAG scheduling
+/// mutation to pair instructions back to back.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/MachineScheduler.h"
+
+namespace llvm {
+
+/// Note that you have to add:
+///   DAG.addMutation(createPowerPCMacroFusionDAGMutation());
+/// to PPCPassConfig::createMachineScheduler() to have an effect.
+std::unique_ptr<ScheduleDAGMutation> createPowerPCMacroFusionDAGMutation();
+} // llvm

llvm/lib/Target/PowerPC/PPCMacroFusion.cpp

+//===- PPCMacroFusion.cpp - PowerPC Macro Fusion --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file This file contains the PowerPC implementation of the DAG scheduling
+///  mutation to pair instructions back to back.
+//
+//===----------------------------------------------------------------------===//
+
+#include "PPC.h"
+#include "PPCSubtarget.h"
+#include "llvm/ADT/DenseSet.h"
+#include "llvm/CodeGen/MacroFusion.h"
+
+using namespace llvm;
+namespace {
+
+class FusionFeature {
+public:
+  typedef SmallDenseSet<unsigned> FusionOpSet;
+
+  enum FusionKind {
+  #define FUSION_KIND(KIND) FK_##KIND
+  #define FUSION_FEATURE(KIND, HAS_FEATURE, DEP_OP_IDX, OPSET1, OPSET2) \
+    FUSION_KIND(KIND),
+  #include "PPCMacroFusion.def"
+  FUSION_KIND(END)
+  };
+private:
+  // Each fusion feature is assigned with one fusion kind. All the
+  // instructions with the same fusion kind have the same fusion characteristic.
+  FusionKind Kd;
+  // True if this feature is enabled.
+  bool Supported;
+  // li rx, si
+  // load rt, ra, rx
+  // The dependent operand index in the second op(load). And the negative means
+  // it could be any one. 
+  int DepOpIdx;
+  // The first fusion op set.
+  FusionOpSet OpSet1;
+  // The second fusion op set.
+  FusionOpSet OpSet2;
+public:
+  FusionFeature(FusionKind Kind, bool HasFeature, int Index,
+                const FusionOpSet &First, const FusionOpSet &Second) :
+    Kd(Kind), Supported(HasFeature), DepOpIdx(Index), OpSet1(First), 
+    OpSet2(Second) {}
+
+  bool hasOp1(unsigned Opc) const { return OpSet1.count(Opc) != 0; }
+  bool hasOp2(unsigned Opc) const { return OpSet2.count(Opc) != 0; }
+  bool isSupported() const { return Supported; }
+  Optional<unsigned> depOpIdx() const {
+    if (DepOpIdx < 0)
+      return None;
+    return DepOpIdx;
+  }
+
+  FusionKind getKind() const { return Kd; }
+};
+
+static bool matchingRegOps(const MachineInstr &FirstMI,
+                           int FirstMIOpIndex,
+                           const MachineInstr &SecondMI,
+                           int SecondMIOpIndex) {
+  const MachineOperand &Op1 = FirstMI.getOperand(FirstMIOpIndex);
+  const MachineOperand &Op2 = SecondMI.getOperand(SecondMIOpIndex);
+  if (!Op1.isReg() || !Op2.isReg())
+    return false;
+
+  return Op1.getReg() == Op2.getReg();
+}
+
+// Return true if the FirstMI meets the constraints of SecondMI according to
+// fusion specification.
+static bool checkOpConstraints(FusionFeature::FusionKind Kd,
+                               const MachineInstr &FirstMI,
+                               const MachineInstr &SecondMI) {
+  switch (Kd) {
+  // The hardware didn't require any specific check for the fused instructions'
+  // operands. Therefore, return true to indicate that, it is fusable.
+  default: return true;
+  // [addi rt,ra,si - lxvd2x xt,ra,rb] etc.
+  case FusionFeature::FK_AddiLoad: {
+    // lxvd2x(ra) cannot be zero
+    const MachineOperand &RA = SecondMI.getOperand(1);
+    if (!RA.isReg())
+      return true;
+
+    return Register::isVirtualRegister(RA.getReg()) ||
+      (RA.getReg() != PPC::ZERO && RA.getReg() != PPC::ZERO8);
+  }
+  // [addis rt,ra,si - ld rt,ds(ra)] etc.
+  case FusionFeature::FK_AddisLoad: {
+    const MachineOperand &RT = SecondMI.getOperand(0);
+    if (!RT.isReg())
+      return true;
+
+    // Only check it for non-virtual register.
+    if (!Register::isVirtualRegister(RT.getReg()))
+      // addis(rt) = ld(ra) = ld(rt)
+      // ld(rt) cannot be zero
+      if (!matchingRegOps(SecondMI, 0, SecondMI, 2) ||
+          (RT.getReg() == PPC::ZERO || RT.getReg() == PPC::ZERO8))
+          return false;
+
+    // addis(si) first 12 bits must be all 1s or all 0s
+    const MachineOperand &SI = FirstMI.getOperand(2);
+    if (!SI.isImm())
+      return true;
+    int64_t Imm = SI.getImm();
+    if (((Imm & 0xFFF0) != 0) || ((Imm & 0xFFF0) != 0xFFF0)) 
+      return false;
+
+    // If si = 1111111111110000 and the msb of the d/ds field of the load equals 
+    // 1, then fusion does not occur.
+    if ((Imm & 0xFFF0) == 0xFFF0) {
+      const MachineOperand &D = SecondMI.getOperand(1);
+      if (!D.isImm())
+        return true;
+
+      // 14 bit for DS field, while 16 bit for D field.
+      int MSB = 15;
+      if (SecondMI.getOpcode() == PPC::LD)
+        MSB = 13;
+
+      return (D.getImm() & (1ULL << MSB)) == 0;
+    }
+    return true;
+  }
+  }
+
+  llvm_unreachable("All the cases should have been handled");
+  return true;
+}
+
+/// Check if the instr pair, FirstMI and SecondMI, should be fused together.
+/// Given SecondMI, when FirstMI is unspecified, then check if SecondMI may be
+/// part of a fused pair at all.
+static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
+                                   const TargetSubtargetInfo &TSI,
+                                   const MachineInstr *FirstMI,
+                                   const MachineInstr &SecondMI) {
+  // We use the PPC namespace to avoid the need to prefix opcodes with PPC:: in
+  // the def file.
+  using namespace PPC;
+
+  const PPCSubtarget &ST = static_cast<const PPCSubtarget&>(TSI);
+  static const FusionFeature FusionFeatures[] = {
+  #define FUSION_FEATURE(KIND, HAS_FEATURE, DEP_OP_IDX, OPSET1, OPSET2) { \
+    FusionFeature::FUSION_KIND(KIND), ST.HAS_FEATURE(), DEP_OP_IDX, { OPSET1 },\
+    { OPSET2 } },
+   #include "PPCMacroFusion.def"
+  };
+  #undef FUSION_KIND
+
+  for (auto &Feature : FusionFeatures) {
+    // Skip if the feature is not supported.
+    if (!Feature.isSupported())
+      continue;
+
+    // Only when the SecondMI is fusable, we are starting to look for the
+    // fusable FirstMI.
+    if (Feature.hasOp2(SecondMI.getOpcode())) {
+      // If FirstMI == nullptr, that means, we're only checking whether SecondMI
+      // can be fused at all.
+      if (!FirstMI)
+        return true;
+
+      // Checking if the FirstMI is fusable with the SecondMI.
+      if (!Feature.hasOp1(FirstMI->getOpcode()))
+        continue;
+
+      auto DepOpIdx = Feature.depOpIdx();
+      if (DepOpIdx.hasValue()) {
+        // Checking if the result of the FirstMI is the desired operand of the
+        // SecondMI if the DepOpIdx is set. Otherwise, ignore it.
+        if (!matchingRegOps(*FirstMI, 0, SecondMI, *DepOpIdx))
+          return false;
+      }
+  
+      // Checking more on the instruction operands.
+      if (checkOpConstraints(Feature.getKind(), *FirstMI, SecondMI))
+        return true;
+    }
+  }
+
+  return false;
+}
+
+} // end anonymous namespace
+
+namespace llvm {
+
+std::unique_ptr<ScheduleDAGMutation> createPowerPCMacroFusionDAGMutation () {
+  return createMacroFusionDAGMutation(shouldScheduleAdjacent);
+}
+
+} // end namespace llvm

llvm/lib/Target/PowerPC/PPCMacroFusion.def

+//=== ---- PPCMacroFusion.def - PowerPC MacroFuson Candidates -v-*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https)//llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier) Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains descriptions of the macro-fusion pair for PowerPC.
+//
+//===----------------------------------------------------------------------===//
+
+// NOTE: NO INCLUDE GUARD DESIRED!
+
+#ifndef FUSION_FEATURE
+
+// Each FUSION_FEATURE is assigned with one TYPE, and can be enabled/disabled
+// by HAS_FEATURE. The instructions pair is fusable only when the opcode
+// of the first instruction is in OPSET1, and the second instruction opcode is
+// in OPSET2. And if DEP_OP_IDX >=0, we will check the result of first OP is  
+// the operand of the second op with DEP_OP_IDX as its operand index. We assume
+// that the result of the first op is its operand zero. 
+#define FUSION_FEATURE(TYPE, HAS_FEATURE, DEP_OP_IDX, OPSET1, OPSET2)
+
+#endif
+
+#ifndef FUSION_OP_SET
+#define FUSION_OP_SET(...) __VA_ARGS__ 
+#endif
+
+// Power8 User Manual Section 10.1.12, Instruction Fusion 
+// {addi} followed by one of these {lxvd2x, lxvw4x, lxvdsx, lvebx, lvehx,
+// lvewx, lvx, lxsdx}
+FUSION_FEATURE(AddiLoad, hasAddiLoadFusion, 2, \
+               FUSION_OP_SET(ADDI, ADDI8, ADDItocL), \
+               FUSION_OP_SET(LXVD2X, LXVW4X, LXVDSX, LVEBX, LVEHX, LVEWX, \
+                             LVX, LXSDX))
+
+// {addis) followed by one of these {ld, lbz, lhz, lwz}
+FUSION_FEATURE(AddisLoad, hasAddisLoadFusion, 2, \
+               FUSION_OP_SET(ADDIS, ADDIS8, ADDIStocHA8), \
+               FUSION_OP_SET(LD, LBZ, LBZ8, LHZ, LHZ8, LWZ, LWZ8))
+
+#undef FUSION_FEATURE
+#undef FUSION_OP_SET

llvm/lib/Target/PowerPC/PPCSubtarget.h

protected:
   bool DeprecatedDST;
   bool IsLittleEndian;
   bool HasICBT;
   bool HasInvariantFunctionDescriptors;
   bool HasPartwordAtomics;
   bool HasDirectMove;
   bool HasHTM;
   bool HasFloat128;
+  bool HasFusion;
+  bool HasAddiLoadFusion;
+  bool HasAddisLoadFusion;
   bool IsISA3_0;
   bool UseLongCalls;
   bool SecurePlt;
   bool VectorsUseTwoUnits;
   bool UsePPCPreRASchedStrategy;
   bool UsePPCPostRASchedStrategy;
 
   POPCNTDKind HasPOPCNTD;
unsigned  getRedZoneSize() const {
     // PPC32 SVR4ABI has no redzone.
     return isAIXABI() ? 220 : 0;
   }
 
   bool hasHTM() const { return HasHTM; }
   bool hasFloat128() const { return HasFloat128; }
   bool isISA3_0() const { return IsISA3_0; }
   bool useLongCalls() const { return UseLongCalls; }
+  bool hasFusion() const { return HasFusion; }
+  bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
+  bool hasAddisLoadFusion() const { return HasAddisLoadFusion; }
   bool needsSwapsForVSXMemOps() const {
     return hasVSX() && isLittleEndian() && !hasP9Vector();
   }
 
   POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
 
   const Triple &getTargetTriple() const { return TargetTriple; }
 

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

void PPCSubtarget::initializeEnvironment() {
   DeprecatedDST = false;
   HasICBT = false;
   HasInvariantFunctionDescriptors = false;
   HasPartwordAtomics = false;
   HasDirectMove = false;
   IsQPXStackUnaligned = false;
   HasHTM = false;
   HasFloat128 = false;
+  HasFusion = false;
+  HasAddiLoadFusion = false;
+  HasAddisLoadFusion = false;
   IsISA3_0 = false;
   UseLongCalls = false;
   SecurePlt = false;
   VectorsUseTwoUnits = false;
   UsePPCPreRASchedStrategy = false;
   UsePPCPostRASchedStrategy = false;
 
   HasPOPCNTD = POPCNTD_Unavailable;

llvm/lib/Target/PowerPC/PPCTargetMachine.cpp

 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // Top-level implementation for the PowerPC target.
 //
 //===----------------------------------------------------------------------===//
 
 #include "PPCTargetMachine.h"
 #include "MCTargetDesc/PPCMCTargetDesc.h"
 #include "PPC.h"
 #include "PPCMachineScheduler.h"
+#include "PPCMacroFusion.h"
 #include "PPCSubtarget.h"
 #include "PPCTargetObjectFile.h"
 #include "PPCTargetTransformInfo.h"
 #include "TargetInfo/PowerPCTargetInfo.h"
 #include "llvm/ADT/Optional.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Triple.h"

 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
   ScheduleDAGMILive *DAG =
     new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
                           std::make_unique<PPCPreRASchedStrategy>(C) :
                           std::make_unique<GenericScheduler>(C));
   // add DAG Mutations here.
   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
+  if (ST.hasFusion())
+    DAG->addMutation(createPowerPCMacroFusionDAGMutation());
+
   return DAG;
 }
 
 static ScheduleDAGInstrs *createPPCPostMachineScheduler(
   MachineSchedContext *C) {
   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
   ScheduleDAGMI *DAG =
     new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
                       std::make_unique<PPCPostRASchedStrategy>(C) :
                       std::make_unique<PostGenericScheduler>(C), true);
   // add DAG Mutations here.
+  if (ST.hasFusion())
+    DAG->addMutation(createPowerPCMacroFusionDAGMutation());
   return DAG;
 }
 
 // The FeatureString here is a little subtle. We are modifying the feature
 // string with what are (currently) non-function specific overrides as it goes
 // into the LLVMTargetMachine constructor and then using the stored value in the
 // Subtarget constructor below it.
 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,

llvm/test/CodeGen/PowerPC/macro-fusion.ll

+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-misched -debug-only=machine-scheduler \
+; RUN:  -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK-P8
+
+@m = local_unnamed_addr global i64 0, align 8
+
+define i64 @fuse_addis_ld() {
+entry:
+; CHECK-P8: ********** MI Scheduling **********
+; CHECK-P8-LABEL: fuse_addis_ld:%bb.0 entry
+; CHECK-P8: Macro fuse: SU([[SU0:[0-9]+]]) - SU([[SU1:[0-9]+]]) /  ADDIStocHA8 - LD
+; CHECK-P8: SU([[SU0]]):   %[[REG3:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @m
+; CHECK-P8: SU([[SU1]]):   %{{[0-9]+}}:g8rc = LD target-flags(ppc-toc-lo) @m, %[[REG3]]
+; CHECK-P8: ********** MI Scheduling **********
+; CHECK-P8-LABEL: fuse_addis_ld:%bb.0 entry
+; CHECK-P8: Macro fuse: SU([[SU0:[0-9]+]]) - SU([[SU1:[0-9]+]]) /  ADDIStocHA8 - LD
+; CHECK-P8: SU([[SU0]]):   renamable $x[[REG3:[0-9]+]] = ADDIStocHA8 $x2, @m
+; CHECK-P8: SU([[SU1]]):   renamable $x[[REG3]] = LD target-flags(ppc-toc-lo) @m, renamable $x[[REG3]]
+  %0 = load i64, i64* @m, align 8
+  ret i64 %0
+}