[mips] Add a 'generic' Mips CPU

[mstojanovic]

Summary

Having a generic CPU removes a warning when creating a subtarget without the CPU being explicitly specified.

[atanasyan]

removes a warning when creating a subtarget without the CPU being explicitly specified

Without this patch llc -mtriple=mips -filetype=obj < cpus.ll shows no error for me. How reproduce the initial problem?

llvm/lib/Target/Mips/Mips.td

235

I think we need to explicitly specify a feature set enabled by default. In our case it's FeatureMips32. Otherwise it looks like the "generic" CPU has no features.

[mstojanovic]

Added FeatureMips32 feature.

I came across this while running llvm-exegesis on a mips board, e.g.:

llvm-exegesis -mode latency -snippets-file /dev/null

It gets the 'generic' CPU name with sys::getHostCPUName() and calls createTargetMachine(), which then emits a warning:

'generic' is not a recognized processor for this target (ignoring processor)

Should I add a unittest that recreates this process?

[atanasyan]

In D70490#1754970, @mstojanovic wrote:

It gets the 'generic' CPU name with sys::getHostCPUName() and calls createTargetMachine(), which then emits a warning:

'generic' is not a recognized processor for this target (ignoring processor)

Should I add a unittest that recreates this process?

Is it possible already to add any useful test case to the llvm/test/tools/llvm-exegesis/Mips? If so, let's add. Otherwise changes in the cpus.ll are good enough.

[mstojanovic]

It's possible to run some tests manually but the test mentioned above, which will be part of lit.local.cfg and which checks whether lit can run llvm-exegesis tests on Mips, is encountering a segfault so I'm working on fixing that first.

[atanasyan]

LGTM

Thanks.

llvm/lib/Target/Mips/Mips.td

 
 def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
                                  "MipsSubtarget::CPU::P5600",
                                  "The P5600 Processor", [FeatureMips32r5]>;
 
 class Proc<string Name, list<SubtargetFeature> Features>
  : ProcessorModel<Name, MipsGenericModel, Features>;
 
+def : Proc<"generic", [FeatureMips32]>;
 def : Proc<"mips1", [FeatureMips1]>;
 def : Proc<"mips2", [FeatureMips2]>;
 def : Proc<"mips32", [FeatureMips32]>;
 def : Proc<"mips32r2", [FeatureMips32r2]>;
 def : Proc<"mips32r3", [FeatureMips32r3]>;
 def : Proc<"mips32r5", [FeatureMips32r5]>;
 def : Proc<"mips32r6", [FeatureMips32r6]>;
 

llvm/test/CodeGen/Mips/cpus.ll

 ; Check that the CPU names work.
 
+; RUN: llc -mtriple=mips -mcpu=generic -filetype=obj < %s \
+; RUN:   | llvm-readelf -A | FileCheck %s --check-prefix=GENERIC
+; GENERIC: ISA: MIPS32
+
 ; RUN: llc -mtriple=mips -mcpu=mips2 -filetype=obj < %s \
 ; RUN:   | llvm-readelf -A | FileCheck %s --check-prefix=MIPS2
 ; MIPS2: ISA: MIPS2
 ; RUN: llc -mtriple=mips64 -mcpu=mips3 -filetype=obj < %s \
 ; RUN:   | llvm-readelf -A | FileCheck %s --check-prefix=MIPS3
 ; MIPS3: ISA: MIPS3
 ; RUN: llc -mtriple=mips64 -mcpu=mips4 -filetype=obj < %s \
 ; RUN:   | llvm-readelf -A | FileCheck %s --check-prefix=MIPS4