[AMDGPU][DPP] Corrected DPP combiner

[dp]

Summary

Added a check to make sure that the selected dpp opcode is supported by target.

[vpykhtin]

LGTM.

llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

public:
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   StringRef getPassName() const override { return "GCN DPP Combine"; }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
+
+private:
+  int getDPPOp(unsigned Op) const;
 };
 
 } // end anonymous namespace
 
 INITIALIZE_PASS(GCNDPPCombine, DEBUG_TYPE, "GCN DPP Combine", false, false)
 
 char GCNDPPCombine::ID = 0;
 
 char &llvm::GCNDPPCombineID = GCNDPPCombine::ID;
 
 FunctionPass *llvm::createGCNDPPCombinePass() {
   return new GCNDPPCombine();
 }
 
-static int getDPPOp(unsigned Op) {
+int GCNDPPCombine::getDPPOp(unsigned Op) const {
   auto DPP32 = AMDGPU::getDPPOp32(Op);
-  if (DPP32 != -1)
-    return DPP32;
-
+  if (DPP32 == -1) {
     auto E32 = AMDGPU::getVOPe32(Op);
-  return E32 != -1 ? AMDGPU::getDPPOp32(E32) : -1;
+    DPP32 = (E32 == -1)? -1 : AMDGPU::getDPPOp32(E32);
+  }
+  return (DPP32 == -1 || TII->pseudoToMCOpcode(DPP32) == -1) ? -1 : DPP32;
 }
 
 // tracks the register operand definition and returns:
 //   1. immediate operand used to initialize the register if found
 //   2. nullptr if the register operand is undef
 //   3. the operand itself otherwise
 MachineOperand *GCNDPPCombine::getOldOpndValue(MachineOperand &OldOpnd) const {
   auto *Def = getVRegSubRegDef(getRegSubRegPair(OldOpnd), *MRI);