These opcodes use indirect register addressing so they need special handling by codegen (currently missing).
I thought about it. Yes, it is possible, but that will not make code more readable overall.
Overall I think that this case is very special and requires a special solution. If we face similar issues in the future (that need more cases in the switch below), we may create a flag for this purpose. I'm not sure it is necessary for MOVREL*.
Is it the same as isAsmParserOnly in td? If so shouldn't it be easy to mark it there?
Actually what makes them risky is impuse of M0, so it can be folded around M0 definition. Isn't it cleaner to check for impuse in the SDWA and DPP combiner and disable the combining on these grounds rather than excluding it from codegen completely?
Maybe. But I do not understand how codegen can handle these instructions without knowing actual dst and src registers. To support _dpp and _sdwa variants codegen needs the same (or similar) hacks as those implemented for v_movreld_b32.
Hmm. I think you are right:
v1 = v_and_b32 v2, 0xf v3 = v_movrels_b32 v1
Means: v3 = v1[m0], same as v3 = (v1 & 0xf)[m0]
After sdwa conversion it would be: v3 = v2[m0] & 0xf
Not exactly the same thing.