[ARM] -mfpu=*-sp-d16 should imply that D registers are available

[miyuki]

Summary

When using e.g. the following arch/fpu:

-march=armv8-m.main -mfpu=fpv5-sp-d16

the target feature fpregs64 is not enabled, i.e. D registers are not
allowed in any instruction. Even though 64-bit FP operations are not
available with such FPU option, the 64-bit D registers must still be
accessible (d16 implies that there are 16 D registers). This should
be the case for any *-sp-d16 FPU.

This change also adjusts one MVE test.

[simon_tatham]

As I understand it, this has the effect of making the VMOVD and VMOVDcc instructions (e.g. vmov.f64 d0,d1) legal on targets with single-precision only FP, such as Cortex-M4. But by my reading of the 7-M ARMARM, I don't believe that instruction actually is legal on Cortex-M4.

llvm/lib/Target/ARM/ARM.td

multiclass VFPver<string name, string query, string description,
                   list<SubtargetFeature> prev,
                   list<SubtargetFeature> otherimplies,
                   list<SubtargetFeature> vfp2prev = []> {
   def _D16_SP: SubtargetFeature<
     name#"d16sp", query#"D16SP", "true",
     description#" with only 16 d-registers and no double precision",
     !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) #
       !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) #
-      otherimplies>;
+      otherimplies # [FeatureFPRegs64]>;
   def _SP: SubtargetFeature<
     name#"sp", query#"SP", "true",
     description#" with no double precision",
     !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) #
       otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;
   def _D16: SubtargetFeature<
     name#"d16", query#"D16", "true",
     description#" with only 16 d-registers",

llvm/test/MC/ARM/mve-fp-registers.s

 
 // The v8.2A FP16 extension added loads, stores and moves for FP16.
 // RUN: llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+fp-armv8,+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 --check-prefix=FP32 --check-prefix=FP64
 
 // M-profile FPUs (e.g. Cortex-M4/M7/M33) do not have FP16 instructions, and
 // the FP64 instructions are optional. They are also limited to 16 D registers,
 // but we don't test that here.
 // RUN: not llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+vfp4d16sp 2>%t < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP32
-// RUN: FileCheck %s < %t --check-prefix=NOFP16 --check-prefix=NOFP64
+// RUN: FileCheck %s < %t --check-prefix=NOFP16
 // RUN: not llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+vfp4,-d32 2>%t < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP32 --check-prefix=FP64
 // RUN: FileCheck %s < %t --check-prefix=NOFP16
 
 // Integer-only MVE, which can be combined with different options for scalar
 // FPU (or lack thereof), and has all of the move and store instructions
 // regardless of the scalar FPU.
 // RUN: llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+mve 2>%t < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 --check-prefix=FP32 --check-prefix=FP64
 // RUN: llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+mve,+fp-armv8-sp,+fullfp16 2>%t < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 --check-prefix=FP32 --check-prefix=FP64