Add support for lowering 32-bit/64-bit pointers

[akhuang]

Summary

This follows a previous patch that changes the X86 datalayout to represent
mixed size pointers (32-bit sext, 32-bit zext, and 64-bit) with address spaces
(https://reviews.llvm.org/D64931)

This patch implements the address space cast lowering to the corresponding
sign extension, zero extension, or truncate instructions.

Related to https://bugs.llvm.org/show_bug.cgi?id=42359

[arsenm]

llvm/lib/Target/X86/X86ISelLowering.cpp

2396–2397

These look redundant with the size check to me

llvm/test/CodeGen/X86/mixed-ptr-sizes.ll

36–37

Don't need this

108

Should add some tests with the recognized address spaces and an arbitrary number

110

All the metadata should be removed

[akhuang]

llvm/lib/Target/X86/X86ISelLowering.cpp

2396–2397

Good point - I guess removing the address space check would allow casting from arbitrary address spaces to ptr32/ptr64, which makes sense.

[akhuang]

-Edit logic for when to do address space casts to allow for casting
between ptr32/ptr64 and arbitrary other address spaces; add tests
-Remove unnecessary stuff from test

[RKSimon]

llvm/lib/Target/X86/X86.h

156

use regular X86 namespace and name the enum?

namespace X86 {
enum class AddressSpace : unsigned {

[akhuang]

llvm/lib/Target/X86/X86.h

156

I tried using an enum class but since address spaces are ints it is a bit inconvenient to convert them to enum types. is it better to not have different namespaces?

[akhuang]

ping!

[rnk]

lgtm

llvm/lib/Target/X86/X86.h

156

Most code treats address spaces as unsigned integers, I'd leave it as a regular enum for now.

llvm/lib/Target/X86/X86ISelLowering.cpp

27636

This value will appear to be unused in a build without assertions, which will create warnings. The simplest fix would be to skip the local and move this call into the assert.

28599

ditto

[akhuang]

Address comment

llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

unsigned FastISel::materializeConstant(const Value *V, MVT VT) {
   if (const auto *CI = dyn_cast<ConstantInt>(V)) {
     if (CI->getValue().getActiveBits() <= 64)
       Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
   } else if (isa<AllocaInst>(V))
     Reg = fastMaterializeAlloca(cast<AllocaInst>(V));
   else if (isa<ConstantPointerNull>(V))
     // Translate this as an integer zero so that it can be
     // local-CSE'd with actual integer zeros.
-    Reg = getRegForValue(
-        Constant::getNullValue(DL.getIntPtrType(V->getContext())));
+    Reg =
+        getRegForValue(Constant::getNullValue(DL.getIntPtrType(V->getType())));
   else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
     if (CF->isNullValue())
       Reg = fastMaterializeFloatZero(CF);
     else
       // Try to emit the constant directly.
       Reg = fastEmit_f(VT, VT, ISD::ConstantFP, CF);
 
     if (!Reg) {

llvm/lib/Target/X86/X86.h

 void initializeX86DomainReassignmentPass(PassRegistry &);
 void initializeX86ExecutionDomainFixPass(PassRegistry &);
 void initializeX86ExpandPseudoPass(PassRegistry &);
 void initializeX86FlagsCopyLoweringPassPass(PassRegistry &);
 void initializeX86OptimizeLEAPassPass(PassRegistry &);
 void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &);
 } // End llvm namespace
 
+namespace X86AS {
+enum : unsigned {
+  GS = 256,
+  FS = 257,
+  SS = 258,
+  PTR32_SPTR = 270,
+  PTR32_UPTR = 271,
+  PTR64 = 272
+};
+}
+
 #endif

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

bool X86DAGToDAGISel::selectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
                                        SDValue &Scale, SDValue &Index,
                                        SDValue &Disp, SDValue &Segment) {
   X86ISelAddressMode AM;
   auto *Mgs = cast<X86MaskedGatherScatterSDNode>(Parent);
   AM.IndexReg = Mgs->getIndex();
   AM.Scale = cast<ConstantSDNode>(Mgs->getScale())->getZExtValue();
 
   unsigned AddrSpace = cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
-  // AddrSpace 256 -> GS, 257 -> FS, 258 -> SS.
-  if (AddrSpace == 256)
+  if (AddrSpace == X86AS::GS)
     AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
-  if (AddrSpace == 257)
+  if (AddrSpace == X86AS::FS)
     AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
-  if (AddrSpace == 258)
+  if (AddrSpace == X86AS::SS)
     AM.Segment = CurDAG->getRegister(X86::SS, MVT::i16);
 
   SDLoc DL(N);
   MVT VT = N.getSimpleValueType();
 
   // Try to match into the base and displacement fields.
   if (matchVectorAddress(N, AM))
     return false;

llvm/lib/Target/X86/X86ISelLowering.cpp

X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
   setOperationAction(ISD::FP_TO_UINT       , MVT::i8   , Promote);
   setOperationAction(ISD::FP_TO_UINT       , MVT::i16  , Promote);
 
   if (!Subtarget.useSoftFloat()) {
     setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
   }
 
+  // Handle address space casts between mixed sized pointers.
+  setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
+  setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
+
   // TODO: when we have SSE, these could be more efficient, by using movd/movq.
   if (!X86ScalarSSEf64) {
     setOperationAction(ISD::BITCAST        , MVT::f32  , Expand);
     setOperationAction(ISD::BITCAST        , MVT::i32  , Expand);
     if (Subtarget.is64Bit()) {
       setOperationAction(ISD::BITCAST      , MVT::f64  , Expand);
       // Without SSE, i64->f64 goes through memory.
       setOperationAction(ISD::BITCAST      , MVT::i64  , Expand);
Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
   if (Subtarget.isTargetFuchsia()) {
     // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
     return SegmentOffset(IRB, 0x18, getAddressSpace());
   }
 
   return TargetLowering::getSafeStackPointerLocation(IRB);
 }
 
+static bool isPtrSizeOrDefaultAddrSpace(unsigned AS) {
+  return (AS == 0 || AS == X86AS::PTR32_SPTR || AS == X86AS::PTR32_UPTR ||
+          AS == X86AS::PTR64);
+}
+
 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
                                             unsigned DestAS) const {
   assert(SrcAS != DestAS && "Expected different address spaces!");
 
+  const TargetMachine &TM = getTargetMachine();
+  if ((isPtrSizeOrDefaultAddrSpace(SrcAS) &&
+       isPtrSizeOrDefaultAddrSpace(DestAS)) &&
+      TM.getPointerSize(SrcAS) != TM.getPointerSize(DestAS))
+    return false;
+
   return SrcAS < 256 && DestAS < 256;
 }
 
 //===----------------------------------------------------------------------===//
 //               Return Value Calling Convention Implementation
 //===----------------------------------------------------------------------===//
 
 bool X86TargetLowering::CanLowerReturn(
static SDValue LowerMGATHER(SDValue Op, const X86Subtarget &Subtarget,
   SDValue NewGather = DAG.getTargetMemSDNode<X86MaskedGatherSDNode>(
       DAG.getVTList(VT, MaskVT, MVT::Other), Ops, dl, N->getMemoryVT(),
       N->getMemOperand());
   SDValue Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OrigVT,
                                 NewGather, DAG.getIntPtrConstant(0, dl));
   return DAG.getMergeValues({Extract, NewGather.getValue(2)}, dl);
 }
 
+static SDValue LowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) {
+  SDLoc dl(Op);
+  SDValue Src = Op.getOperand(0);
+  MVT DstVT = Op.getSimpleValueType();
+
+  AddrSpaceCastSDNode *N = cast<AddrSpaceCastSDNode>(Op.getNode());
+  unsigned SrcAS = N->getSrcAddressSpace();
+  unsigned DstAS = N->getDestAddressSpace();
+
+  assert(SrcAS != DstAS &&
+         "addrspacecast must be between different address spaces");
+
+  if (isPtrSizeOrDefaultAddrSpace(SrcAS) &&
+      isPtrSizeOrDefaultAddrSpace(DstAS)) {
+    if (SrcAS == X86AS::PTR32_UPTR && DstVT == MVT::i64) {
+      Op = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Src);
+    } else if (DstVT == MVT::i64) {
+      Op = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Src);
+    } else if (DstVT == MVT::i32) {
+      Op = DAG.getNode(ISD::TRUNCATE, dl, DstVT, Src);
+    }
+  } else {
+    report_fatal_error("Bad address space in addrspacecast");
+  }
+  return Op;
+}
+
 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
                                                     SelectionDAG &DAG) const {
   // TODO: Eventually, the lowering of these nodes should be informed by or
   // deferred to the GC strategy for the function in which they appear. For
   // now, however, they must be lowered to something. Since they are logically
   // no-ops in the case of a null GC strategy (or a GC strategy which does not
   // require special handling for these nodes), lower them as literal NOOPs for
   // the time being.
SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::FSINCOS:            return LowerFSINCOS(Op, Subtarget, DAG);
   case ISD::MLOAD:              return LowerMLOAD(Op, Subtarget, DAG);
   case ISD::MSTORE:             return LowerMSTORE(Op, Subtarget, DAG);
   case ISD::MGATHER:            return LowerMGATHER(Op, Subtarget, DAG);
   case ISD::MSCATTER:           return LowerMSCATTER(Op, Subtarget, DAG);
   case ISD::GC_TRANSITION_START:
                                 return LowerGC_TRANSITION_START(Op, DAG);
   case ISD::GC_TRANSITION_END:  return LowerGC_TRANSITION_END(Op, DAG);
+  case ISD::ADDRSPACECAST:
+    return LowerADDRSPACECAST(Op, DAG);
   }
 }
 
 /// Places new result values for the node in Results (their number
 /// and types must exactly match those of the original return values of
 /// the node), or leaves Results empty, which indicates that the node is not
 /// to be custom lowered after all.
 void X86TargetLowering::LowerOperationWrapper(SDNode *N,
case ISD::LOAD: {
     SDVTList Tys = DAG.getVTList(MVT::v4f32, MVT::Other);
     SDValue Ops[] = {Ld->getChain(), Ld->getBasePtr()};
     SDValue Res = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
                                           MVT::i64, Ld->getMemOperand());
     Results.push_back(Res);
     Results.push_back(Res.getValue(1));
     return;
   }
+  case ISD::ADDRSPACECAST: {
+    SDValue Src = N->getOperand(0);
+    EVT DstVT = N->getValueType(0);
+    AddrSpaceCastSDNode *CastN = cast<AddrSpaceCastSDNode>(N);
+    unsigned SrcAS = CastN->getSrcAddressSpace();
+    unsigned DstAS = CastN->getDestAddressSpace();
+
+    assert(SrcAS != DstAS &&
+           "addrspacecast must be between different address spaces");
+
+    SDValue Res;
+    if (isPtrSizeOrDefaultAddrSpace(SrcAS) &&
+        isPtrSizeOrDefaultAddrSpace(DstAS)) {
+      if (SrcAS == X86AS::PTR32_UPTR && DstVT == MVT::i64)
+        Res = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Src);
+      else if (DstVT == MVT::i64)
+        Res = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Src);
+      else
+        Res = DAG.getNode(ISD::TRUNCATE, dl, DstVT, Src);
+    } else {
+      report_fatal_error("Unrecognized addrspacecast type legalization");
+    }
+
+    Results.push_back(Res);
+    return;
+  }
   }
 }
 
 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((X86ISD::NodeType)Opcode) {
   case X86ISD::FIRST_NUMBER:       break;
   case X86ISD::BSF:                return "X86ISD::BSF";
   case X86ISD::BSR:                return "X86ISD::BSR";

llvm/test/CodeGen/X86/mixed-ptr-sizes.ll

+; RUN: llc < %s | FileCheck --check-prefixes=CHECK %s
+; RUN: llc -O0 < %s | FileCheck --check-prefixes=CHECK %s
+
+; Source to regenerate:
+; struct Foo {
+;   int * __ptr32 p32;
+;   int * __ptr64 p64;
+; };
+; void use_foo(Foo *f);
+; void test_sign_ext(Foo *f, int * __ptr32 __sptr i) {
+;   f->p64 = i;
+;   use_foo(f);
+; }
+; void test_zero_ext(Foo *f, int * __ptr32 __uptr i) {
+;   f->p64 = i;
+;   use_foo(f);
+; }
+; void test_trunc(Foo *f, int * __ptr64 i) {
+;   f->p32 = i;
+;   use_foo(f);
+; }
+; void test_noop1(Foo *f, int * __ptr32 i) {
+;   f->p32 = i;
+;   use_foo(f);
+; }
+; void test_noop2(Foo *f, int * __ptr64 i) {
+;   f->p64 = i;
+;   use_foo(f);
+; }
+; void test_null_arg(Foo *f, void * __ptr32 i) {
+;   test_noop1(f, 0);
+; }
+;
+; $ clang -cc1 -triple x86_64-windows-msvc -fms-extensions -O2 -S t.cpp
+
+; ModuleID = 't.cpp'
+source_filename = "t.cpp"
+target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-windows-msvc"
+
+%struct.Foo = type { i32 addrspace(270)*, i32* }
+declare dso_local void @use_foo(%struct.Foo*)
+
+; Function Attrs: nounwind
+define dso_local void @test_sign_ext(%struct.Foo* %f, i32 addrspace(270)* %i) {
+; CHECK-LABEL: {{.*}}test_sign_ext{{.*}}
+; CHECK:       movslq %edx, %rax
+entry:
+  %0 = addrspacecast i32 addrspace(270)* %i to i32*
+  %p64 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i64 0, i32 1
+  store i32* %0, i32** %p64, align 8, !tbaa !2
+  tail call void @use_foo(%struct.Foo* %f)
+  ret void
+}
+
+; Function Attrs: nounwind
+define dso_local void @test_zero_ext(%struct.Foo* %f, i32 addrspace(271)* %i) {
+; CHECK-LABEL: {{.*}}test_zero_ext{{.*}}
+; CHECK:       movl %edx, %eax
+entry:
+  %0 = addrspacecast i32 addrspace(271)* %i to i32*
+  %p64 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i64 0, i32 1
+  store i32* %0, i32** %p64, align 8, !tbaa !2
+  tail call void @use_foo(%struct.Foo* %f)
+  ret void
+}
+
+; Function Attrs: nounwind
+define dso_local void @test_trunc(%struct.Foo* %f, i32* %i) {
+; CHECK-LABEL: {{.*}}test_trunc{{.*}}
+; CHECK:       movl %edx, (%rcx)
+entry:
+  %0 = addrspacecast i32* %i to i32 addrspace(270)*
+  %p32 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i64 0, i32 0
+  store i32 addrspace(270)* %0, i32 addrspace(270)** %p32, align 8, !tbaa !7
+  tail call void @use_foo(%struct.Foo* %f)
+  ret void
+}
+
+; Function Attrs: nounwind
+define dso_local void @test_noop1(%struct.Foo* %f, i32 addrspace(270)* %i) {
+; CHECK-LABEL: {{.*}}test_noop1{{.*}}
+; CHECK:       movl %edx, (%rcx)
+entry:
+  %p32 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i64 0, i32 0
+  store i32 addrspace(270)* %i, i32 addrspace(270)** %p32, align 8, !tbaa !7
+  tail call void @use_foo(%struct.Foo* %f)
+  ret void
+}
+
+; Function Attrs: nounwind
+define dso_local void @test_noop2(%struct.Foo* %f, i32* %i) {
+; CHECK-LABEL: {{.*}}test_noop2{{.*}}
+; CHECK:       movq %rdx, 8(%rcx)
+entry:
+  %p64 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i64 0, i32 1
+  store i32* %i, i32** %p64, align 8, !tbaa !2
+  tail call void @use_foo(%struct.Foo* %f)
+  ret void
+}
+
+; Test that null can be passed as a 32-bit pointer.
+define dso_local void @test_null_arg(%struct.Foo* %f) {
+entry:
+  call void @test_noop1(%struct.Foo* %f, i32 addrspace(270)* null)
+  ret void
+}
+
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 2}
+!1 = !{!"clang version 10.0.0 (https://github.com/llvm/llvm-project.git e7b4a1629519fc9910b49e59ea4b13040631b2b5)"}
+!2 = !{!3, !4, i64 8}
+!3 = !{!"?AUFoo@@", !4, i64 0, !4, i64 8}
+!4 = !{!"any pointer", !5, i64 0}
+!5 = !{!"omnipotent char", !6, i64 0}
+!6 = !{!"Simple C++ TBAA"}
+!7 = !{!3, !4, i64 0}