[X86] Lower frame references with large offsets

[greened]

Summary

Handle offsets > 32 bits by using the register scavenger to find a register to
hold the large offset and change the frame index reference to use SIB
addressing.

[greened]

This likely needs some work. I wanted to get it up early because it includes a rather significant change, the first use of register scavenging in the X86 backend as far as I'm aware. If there is a better way to do this I'm all ears.

[greened]

This causes a couple of tests to fail due to the X86 backend not keeping liveness information up-to-date. My understanding is that the liveness bits should go away. Currently PEI uses RegisterScavenging::forward which is commented as being not preferred. The better option is to use RegisterScavenging::backward which doesn't need to rely on liveness information. However, PEI iterates through the basic block in a forward manner, so using RegisterScavenging::backward could be expensive.

Other targets like AArch64 use register scavenging so they are already relying on an interface that is essentially marked deprecated. What should be the solution here? Fixing up the couple of places in the X86 codegen to properly update liveness isn't too bad but I wonder about other lurking issues. Is it time to rework PEI so that RegisterScavenging::backward can be used?

[greened]

This revision avoids the more general use of register scavenging, opting instead for a local register scavenger which can operate in backward mode, which doesn't need up-to-date liveness information. This seems safer to me, avoiding lots of potentially unknown pitfalls in the X86 backend.

I am not sure whether the FIXME actually applies. If the scavenger is guaranteed to return a stack slot with a small offset, then we can lift the spilling restriction.

[arsenm]

llvm/lib/Target/X86/X86RegisterInfo.cpp

795

I think this is redundant with passing the iterator to scavengeRegisterBackwards but I could be misremembering

[greened]

llvm/lib/Target/X86/X86RegisterInfo.cpp

795

It's actually not. I thought the same but the way scavengeRegisterBackward works is it tries to find a free register over the entire range of the current position and the iterator passed to it. So if you don't call backward() ahead of time you end up saying you require a register free from the passed iterator to the end of the block, which is not likely to be available. :) . I found that out the hard way.

[greened]

Ping.

[arsenm]

llvm/test/CodeGen/X86/large-stack-offset.ll

6–8

These can be dropped

9

Should be moved to -mtriple argument

27

Use named values

34–35

Attributes can probably be removed

[arsenm]

Is this still relevant?

llvm/test/CodeGen/X86/large-stack-offset.ll

28

Use opaque pointers in new tests

llvm/lib/Target/X86/X86RegisterInfo.h

getPointerRegClass(const MachineFunction &MF,
                      unsigned Kind = 0) const override;
 
   /// getCrossCopyRegClass - Returns a legal register class to copy a register
   /// in the specified class to or from. Returns NULL if it is possible to copy
   /// between a two registers of the specified class.
   const TargetRegisterClass *
   getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
 
+  /// Return whether this function requires register scavenging.
+  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
+
   /// getGPRsForTailCall - Returns a register class with registers that can be
   /// used in forming tail calls.
   const TargetRegisterClass *
   getGPRsForTailCall(const MachineFunction &MF) const;
 
   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
                                MachineFunction &MF) const override;
 

llvm/lib/Target/X86/X86RegisterInfo.cpp

 #include "X86MachineFunctionInfo.h"
 #include "X86Subtarget.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/Type.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Target/TargetMachine.h"
if (RC == &X86::CCRRegClass) {
     if (Is64Bit)
       return &X86::GR64RegClass;
     else
       return &X86::GR32RegClass;
   }
   return RC;
 }
 
+bool X86RegisterInfo::requiresRegisterScavenging(
+    const MachineFunction &MF) const {
+  return true;
+}
+
 unsigned
 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
                                      MachineFunction &MF) const {
   const X86FrameLowering *TFI = getFrameLowering(MF);
 
   unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
   switch (RC->getID()) {
   default:
X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
     assert(BasePtr == FramePtr && "Expected the FP as base register");
     int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
     return;
   }
 
   if (MI.getOperand(FIOperandNum+3).isImm()) {
-    // Offset is a 32-bit integer.
     int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
     int Offset = FIOffset + Imm;
-    assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
-           "Requesting 64-bit offset in 32-bit immediate!");
+    if (!isInt<32>((long long)FIOffset + Imm)) {
+      // Load the immediate into a register and use SIB addressing.
+      assert(Is64Bit && "Need 64-bit frame offset in 32-bit mode!");
+
+      assert(MI.getOperand(FIOperandNum + X86::AddrIndexReg).getReg() == 0 &&
+             "Index register already in use with large frame offset!");
+
+      assert(RS && "Register scavenger not available for large frame offset!");
+
+      assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
+             "No emergency spill slot for large frame offset!");
+
+      // WARNING: This API is deprecated but PrologEpilogInserter uses forward()
+      // so we have to use this here.
+      Register OffsetReg = RS->scavengeRegister(getRegClass(BasePtr), II,
+                                                SPAdj);
+
+      const X86InstrInfo *TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
+
+      BuildMI(MBB, II, MI.getDebugLoc(), TII->get(X86::MOV64ri), OffsetReg).
+          addImm((long long)FIOffset + Imm);
+      MI.getOperand(FIOperandNum + X86::AddrIndexReg).setReg(OffsetReg);
+      MI.getOperand(FIOperandNum + X86::AddrIndexReg).setIsKill();
+      MI.getOperand(FIOperandNum + X86::AddrDisp).setImm(0);
+      return;
+    }
+
     if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
       MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
   } else {
     // Offset is symbolic. This is extremely rare.
     uint64_t Offset = FIOffset +
       (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
     MI.getOperand(FIOperandNum + 3).setOffset(Offset);
   }

llvm/test/CodeGen/X86/large-stack-offset.ll

+; Test that we can support a large immediate offset on the stack.
+;
+; RUN: llc %s -o - | FileCheck %s
+;
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+source_filename = "test.c"
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+@.str.7 = external dso_local unnamed_addr constant [73 x i8], align 1
+
+; Function Attrs: noinline optnone
+define dso_local void @main() local_unnamed_addr #0 {
+entry:
+  %result = alloca [1048576000 x double], align 16
+  br i1 undef, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  unreachable
+
+if.end:                                           ; preds = %entry
+  %arrayidx34 = getelementptr inbounds [1048576000 x double], [1048576000 x double]* %result, i64 0, i64 262143999
+; CHECK: movabsq $2298478584, [[INDEX:%[a-z]+]]       # imm = 0x88FFFFF8
+; CHECK-NEXT: movsd (%rbp,[[INDEX]]), {{[a-z0-9]+}}
+
+  %0 = load double, double* %arrayidx34, align 8
+  call void (i8*, ...) @printf(i8* getelementptr inbounds ([73 x i8], [73 x i8]* @.str.7, i64 0, i64 0), i32 undef, i32 262143999, double %0, i32 524287999, double undef, i32 786431999, double undef, i32 1048575999, double undef)
+  ret void
+}
+
+declare dso_local void @printf(i8*, ...) local_unnamed_addr #1
+
+attributes #0 = { noinline optnone "frame-pointer"="all" "no-infs-fp-math"="false" }
+attributes #1 = { "use-soft-float"="false" }