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Differential D69348

[AMDGPU][MC][GFX10] Added v_interp_[p1/p2/mov]_f32_e64
ClosedPublic

Authored by dp on Oct 23 2019, 10:03 AM.

Details

Reviewers
rampitec
arsenm
Commits
rGb8042dbe2bbf: [AMDGPU][MC][GFX10] Added v_interp_[p1/p2/mov]_f32_e64
Summary

The following VOP3 variants of v_interp_*_f32 opcodes are defined for gfx8 and gfx9 but missing in gfx10:

v_interp_p1_f32_e64
v_interp_p2_f32_e64
v_interp_mov_f32_e64

See https://bugs.llvm.org/show_bug.cgi?id=43747

Diff Detail

Event Timeline

dp created this revision.Oct 23 2019, 10:03 AM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptOct 23 2019, 10:03 AM
rampitec accepted this revision.Oct 23 2019, 1:12 PM

LGTM

This revision is now accepted and ready to land.Oct 23 2019, 1:12 PM
Closed by commit rGb8042dbe2bbf: [AMDGPU][MC][GFX10] Added v_interp_[p1/p2/mov]_f32_e64 (authored by dp). · Explain WhyOct 28 2019, 5:16 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptOct 28 2019, 5:16 AM
Herald added subscribers: llvm-commits, hiraditya. · View Herald Transcript

Revision Contents

PathSize
lib/
Target/
AMDGPU/
8 lines
test/
MC/
AMDGPU/
132 lines
Disassembler/
AMDGPU/
132 lines

Diff 226161

lib/Target/AMDGPU/VOP3Instructions.td

Show First 20 Lines • Show All 491 Lines • ▼ Show 20 Linesdef V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>,
(i32 timm:$src2_modifiers), (i32 timm:$src2_modifiers),
(i1 timm:$high), (i1 timm:$high),
(i1 timm:$clamp), (i1 timm:$clamp),
(i32 timm:$omod)))]>; (i32 timm:$omod)))]>;
} // End Uses = [M0, EXEC], FPDPRounding = 1 } // End Uses = [M0, EXEC], FPDPRounding = 1
} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1 } // End SubtargetPredicate = Has16BitInsts, isCommutable = 1
let SubtargetPredicate = isGFX8GFX9 in { let SubtargetPredicate = isGFX8Plus, Uses = [M0, EXEC] in {
def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>; def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>; def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>; def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
} // End SubtargetPredicate = isGFX8GFX9 } // End SubtargetPredicate = isGFX8Plus, Uses = [M0, EXEC]
let Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] in { let Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] in {
multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2, multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,
Instruction inst, SDPatternOperator op3> { Instruction inst, SDPatternOperator op3> {
def : GCNPat < def : GCNPat <
(op2 (op1 i16:$src0, i16:$src1), i16:$src2), (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
(inst i16:$src0, i16:$src1, i16:$src2, (i1 0)) (inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
▲ Show 20 Lines • Show All 252 Lines • ▼ Show 20 Linesdefm V_ADD_NC_I16 :
VOP3OpSel_Real_gfx10_with_name<0x30d, "V_ADD_I16", "v_add_nc_i16">; VOP3OpSel_Real_gfx10_with_name<0x30d, "V_ADD_I16", "v_add_nc_i16">;
defm V_SUB_NC_I16 : defm V_SUB_NC_I16 :
VOP3OpSel_Real_gfx10_with_name<0x30e, "V_SUB_I16", "v_sub_nc_i16">; VOP3OpSel_Real_gfx10_with_name<0x30e, "V_SUB_I16", "v_sub_nc_i16">;
defm V_SUB_NC_I32 : defm V_SUB_NC_I32 :
VOP3_Real_gfx10_with_name<0x376, "V_SUB_I32_gfx9", "v_sub_nc_i32">; VOP3_Real_gfx10_with_name<0x376, "V_SUB_I32_gfx9", "v_sub_nc_i32">;
defm V_ADD_NC_I32 : defm V_ADD_NC_I32 :
VOP3_Real_gfx10_with_name<0x37f, "V_ADD_I32_gfx9", "v_add_nc_i32">; VOP3_Real_gfx10_with_name<0x37f, "V_ADD_I32_gfx9", "v_add_nc_i32">;
defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_gfx10<0x200>;
defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_gfx10<0x201>;
defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_gfx10<0x202>;
defm V_INTERP_P1LL_F16 : VOP3Interp_Real_gfx10<0x342>; defm V_INTERP_P1LL_F16 : VOP3Interp_Real_gfx10<0x342>;
defm V_INTERP_P1LV_F16 : VOP3Interp_Real_gfx10<0x343>; defm V_INTERP_P1LV_F16 : VOP3Interp_Real_gfx10<0x343>;
defm V_INTERP_P2_F16 : VOP3Interp_Real_gfx10<0x35a>; defm V_INTERP_P2_F16 : VOP3Interp_Real_gfx10<0x35a>;
defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx10<0x311>; defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx10<0x311>;
defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx10<0x312>; defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx10<0x312>;
defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx10<0x313>; defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx10<0x313>;
▲ Show 20 Lines • Show All 351 Lines • Show Last 20 Lines

test/MC/AMDGPU/gfx10_asm_all.s

Context not available.
v_cmp_tru_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD v_cmp_tru_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x26] // W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x26]
// W64-ERR: error: {{instruction not supported on this GPU|invalid operand for instruction}} // W64-ERR: error: {{instruction not supported on this GPU|invalid operand for instruction}}
v_interp_p1_f32_e64 v5, v2, attr0.x
// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x00]
v_interp_p1_f32_e64 v255, v2, attr0.x
// GFX10: v_interp_p1_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x00,0xd6,0x00,0x04,0x02,0x00]
v_interp_p1_f32_e64 v5, v2, attr1.x
// GFX10: v_interp_p1_f32_e64 v5, v2, attr1.x ; encoding: [0x05,0x00,0x00,0xd6,0x01,0x04,0x02,0x00]
v_interp_p1_f32_e64 v5, v2, attr31.x
// GFX10: v_interp_p1_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x00,0xd6,0x1f,0x04,0x02,0x00]
v_interp_p1_f32_e64 v5, v2, attr32.x
// GFX10: v_interp_p1_f32_e64 v5, v2, attr32.x ; encoding: [0x05,0x00,0x00,0xd6,0x20,0x04,0x02,0x00]
v_interp_p1_f32_e64 v5, v255, attr0.x
// GFX10: v_interp_p1_f32_e64 v5, v255, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0xfe,0x03,0x00]
v_interp_p1_f32_e64 v5, -v2, attr0.x
// GFX10: v_interp_p1_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x40]
v_interp_p1_f32_e64 v5, |v2|, attr0.x
// GFX10: v_interp_p1_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x00,0xd6,0x00,0x04,0x02,0x00]
v_interp_p1_f32_e64 v5, v2, attr0.y
// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x00,0xd6,0x40,0x04,0x02,0x00]
v_interp_p1_f32_e64 v5, v2, attr0.z
// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.z ; encoding: [0x05,0x00,0x00,0xd6,0x80,0x04,0x02,0x00]
v_interp_p1_f32_e64 v5, v2, attr0.w
// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.w ; encoding: [0x05,0x00,0x00,0xd6,0xc0,0x04,0x02,0x00]
v_interp_p1_f32_e64 v5, v2, attr0.x clamp
// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x00,0xd6,0x00,0x04,0x02,0x00]
v_interp_p1_f32_e64 v5, v2, attr0.x mul:2
// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x08]
v_interp_p1_f32_e64 v5, v2, attr0.x mul:4
// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x10]
v_interp_p1_f32_e64 v5, v2, attr0.x div:2
// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x18]
v_interp_p2_f32_e64 v5, v2, attr0.x
// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x00]
v_interp_p2_f32_e64 v255, v2, attr0.x
// GFX10: v_interp_p2_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x01,0xd6,0x00,0x04,0x02,0x00]
v_interp_p2_f32_e64 v5, v2, attr1.x
// GFX10: v_interp_p2_f32_e64 v5, v2, attr1.x ; encoding: [0x05,0x00,0x01,0xd6,0x01,0x04,0x02,0x00]
v_interp_p2_f32_e64 v5, v2, attr31.x
// GFX10: v_interp_p2_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x01,0xd6,0x1f,0x04,0x02,0x00]
v_interp_p2_f32_e64 v5, v2, attr32.x
// GFX10: v_interp_p2_f32_e64 v5, v2, attr32.x ; encoding: [0x05,0x00,0x01,0xd6,0x20,0x04,0x02,0x00]
v_interp_p2_f32_e64 v5, v255, attr0.x
// GFX10: v_interp_p2_f32_e64 v5, v255, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0xfe,0x03,0x00]
v_interp_p2_f32_e64 v5, -v2, attr0.x
// GFX10: v_interp_p2_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x40]
v_interp_p2_f32_e64 v5, |v2|, attr0.x
// GFX10: v_interp_p2_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x01,0xd6,0x00,0x04,0x02,0x00]
v_interp_p2_f32_e64 v5, v2, attr0.y
// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x01,0xd6,0x40,0x04,0x02,0x00]
v_interp_p2_f32_e64 v5, v2, attr0.z
// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.z ; encoding: [0x05,0x00,0x01,0xd6,0x80,0x04,0x02,0x00]
v_interp_p2_f32_e64 v5, v2, attr0.w
// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.w ; encoding: [0x05,0x00,0x01,0xd6,0xc0,0x04,0x02,0x00]
v_interp_p2_f32_e64 v5, v2, attr0.x clamp
// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x01,0xd6,0x00,0x04,0x02,0x00]
v_interp_p2_f32_e64 v5, v2, attr0.x mul:2
// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x08]
v_interp_p2_f32_e64 v5, v2, attr0.x mul:4
// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x10]
v_interp_p2_f32_e64 v5, v2, attr0.x div:2
// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x18]
v_interp_mov_f32_e64 v5, p10, attr0.x
// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x00]
v_interp_mov_f32_e64 v255, p10, attr0.x
// GFX10: v_interp_mov_f32_e64 v255, p10, attr0.x ; encoding: [0xff,0x00,0x02,0xd6,0x00,0x00,0x00,0x00]
v_interp_mov_f32_e64 v5, p10, attr1.x
// GFX10: v_interp_mov_f32_e64 v5, p10, attr1.x ; encoding: [0x05,0x00,0x02,0xd6,0x01,0x00,0x00,0x00]
v_interp_mov_f32_e64 v5, p10, attr31.x
// GFX10: v_interp_mov_f32_e64 v5, p10, attr31.x ; encoding: [0x05,0x00,0x02,0xd6,0x1f,0x00,0x00,0x00]
v_interp_mov_f32_e64 v5, p10, attr32.x
// GFX10: v_interp_mov_f32_e64 v5, p10, attr32.x ; encoding: [0x05,0x00,0x02,0xd6,0x20,0x00,0x00,0x00]
v_interp_mov_f32_e64 v5, p20, attr0.x
// GFX10: v_interp_mov_f32_e64 v5, p20, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x02,0x00,0x00]
v_interp_mov_f32_e64 v5, p0, attr0.x
// GFX10: v_interp_mov_f32_e64 v5, p0, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x04,0x00,0x00]
v_interp_mov_f32_e64 v5, p10, attr0.y
// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.y ; encoding: [0x05,0x00,0x02,0xd6,0x40,0x00,0x00,0x00]
v_interp_mov_f32_e64 v5, p10, attr0.z
// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.z ; encoding: [0x05,0x00,0x02,0xd6,0x80,0x00,0x00,0x00]
v_interp_mov_f32_e64 v5, p10, attr0.w
// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.w ; encoding: [0x05,0x00,0x02,0xd6,0xc0,0x00,0x00,0x00]
v_interp_mov_f32_e64 v5, p10, attr0.x clamp
// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x02,0xd6,0x00,0x00,0x00,0x00]
v_interp_mov_f32_e64 v5, p10, attr0.x mul:2
// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x08]
v_interp_mov_f32_e64 v5, p10, attr0.x mul:4
// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x10]
v_interp_mov_f32_e64 v5, p10, attr0.x div:2
// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x18]
Context not available.

test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

Context not available.
# GFX10: v_xor_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x3a,0x6a,0x06,0x86,0x06] # GFX10: v_xor_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x3a,0x6a,0x06,0x86,0x06]
0xf9,0x04,0x0a,0x3a,0x6a,0x06,0x86,0x06 0xf9,0x04,0x0a,0x3a,0x6a,0x06,0x86,0x06
# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x00]
0x05 0x00 0x00 0xd6 0x00 0x04 0x02 0x00
# GFX10: v_interp_p1_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x00,0xd6,0x00,0x04,0x02,0x00]
0xff 0x00 0x00 0xd6 0x00 0x04 0x02 0x00
# GFX10: v_interp_p1_f32_e64 v5, v2, attr1.x ; encoding: [0x05,0x00,0x00,0xd6,0x01,0x04,0x02,0x00]
0x05 0x00 0x00 0xd6 0x01 0x04 0x02 0x00
# GFX10: v_interp_p1_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x00,0xd6,0x1f,0x04,0x02,0x00]
0x05 0x00 0x00 0xd6 0x1f 0x04 0x02 0x00
# GFX10: v_interp_p1_f32_e64 v5, v2, attr32.x ; encoding: [0x05,0x00,0x00,0xd6,0x20,0x04,0x02,0x00]
0x05 0x00 0x00 0xd6 0x20 0x04 0x02 0x00
# GFX10: v_interp_p1_f32_e64 v5, v255, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0xfe,0x03,0x00]
0x05 0x00 0x00 0xd6 0x00 0xfe 0x03 0x00
# GFX10: v_interp_p1_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x40]
0x05 0x00 0x00 0xd6 0x00 0x04 0x02 0x40
# GFX10: v_interp_p1_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x00,0xd6,0x00,0x04,0x02,0x00]
0x05 0x02 0x00 0xd6 0x00 0x04 0x02 0x00
# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x00,0xd6,0x40,0x04,0x02,0x00]
0x05 0x00 0x00 0xd6 0x40 0x04 0x02 0x00
# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.z ; encoding: [0x05,0x00,0x00,0xd6,0x80,0x04,0x02,0x00]
0x05 0x00 0x00 0xd6 0x80 0x04 0x02 0x00
# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.w ; encoding: [0x05,0x00,0x00,0xd6,0xc0,0x04,0x02,0x00]
0x05 0x00 0x00 0xd6 0xc0 0x04 0x02 0x00
# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x00,0xd6,0x00,0x04,0x02,0x00]
0x05 0x80 0x00 0xd6 0x00 0x04 0x02 0x00
# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x08]
0x05 0x00 0x00 0xd6 0x00 0x04 0x02 0x08
# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x10]
0x05 0x00 0x00 0xd6 0x00 0x04 0x02 0x10
# GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x18]
0x05 0x00 0x00 0xd6 0x00 0x04 0x02 0x18
# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x00]
0x05 0x00 0x01 0xd6 0x00 0x04 0x02 0x00
# GFX10: v_interp_p2_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x01,0xd6,0x00,0x04,0x02,0x00]
0xff 0x00 0x01 0xd6 0x00 0x04 0x02 0x00
# GFX10: v_interp_p2_f32_e64 v5, v2, attr1.x ; encoding: [0x05,0x00,0x01,0xd6,0x01,0x04,0x02,0x00]
0x05 0x00 0x01 0xd6 0x01 0x04 0x02 0x00
# GFX10: v_interp_p2_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x01,0xd6,0x1f,0x04,0x02,0x00]
0x05 0x00 0x01 0xd6 0x1f 0x04 0x02 0x00
# GFX10: v_interp_p2_f32_e64 v5, v2, attr32.x ; encoding: [0x05,0x00,0x01,0xd6,0x20,0x04,0x02,0x00]
0x05 0x00 0x01 0xd6 0x20 0x04 0x02 0x00
# GFX10: v_interp_p2_f32_e64 v5, v255, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0xfe,0x03,0x00]
0x05 0x00 0x01 0xd6 0x00 0xfe 0x03 0x00
# GFX10: v_interp_p2_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x40]
0x05 0x00 0x01 0xd6 0x00 0x04 0x02 0x40
# GFX10: v_interp_p2_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x01,0xd6,0x00,0x04,0x02,0x00]
0x05 0x02 0x01 0xd6 0x00 0x04 0x02 0x00
# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x01,0xd6,0x40,0x04,0x02,0x00]
0x05 0x00 0x01 0xd6 0x40 0x04 0x02 0x00
# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.z ; encoding: [0x05,0x00,0x01,0xd6,0x80,0x04,0x02,0x00]
0x05 0x00 0x01 0xd6 0x80 0x04 0x02 0x00
# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.w ; encoding: [0x05,0x00,0x01,0xd6,0xc0,0x04,0x02,0x00]
0x05 0x00 0x01 0xd6 0xc0 0x04 0x02 0x00
# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x01,0xd6,0x00,0x04,0x02,0x00]
0x05 0x80 0x01 0xd6 0x00 0x04 0x02 0x00
# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x08]
0x05 0x00 0x01 0xd6 0x00 0x04 0x02 0x08
# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x10]
0x05 0x00 0x01 0xd6 0x00 0x04 0x02 0x10
# GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x18]
0x05 0x00 0x01 0xd6 0x00 0x04 0x02 0x18
# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x00]
0x05 0x00 0x02 0xd6 0x00 0x00 0x00 0x00
# GFX10: v_interp_mov_f32_e64 v255, p10, attr0.x ; encoding: [0xff,0x00,0x02,0xd6,0x00,0x00,0x00,0x00]
0xff 0x00 0x02 0xd6 0x00 0x00 0x00 0x00
# GFX10: v_interp_mov_f32_e64 v5, p10, attr1.x ; encoding: [0x05,0x00,0x02,0xd6,0x01,0x00,0x00,0x00]
0x05 0x00 0x02 0xd6 0x01 0x00 0x00 0x00
# GFX10: v_interp_mov_f32_e64 v5, p10, attr31.x ; encoding: [0x05,0x00,0x02,0xd6,0x1f,0x00,0x00,0x00]
0x05 0x00 0x02 0xd6 0x1f 0x00 0x00 0x00
# GFX10: v_interp_mov_f32_e64 v5, p10, attr32.x ; encoding: [0x05,0x00,0x02,0xd6,0x20,0x00,0x00,0x00]
0x05 0x00 0x02 0xd6 0x20 0x00 0x00 0x00
# GFX10: v_interp_mov_f32_e64 v5, p20, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x02,0x00,0x00]
0x05 0x00 0x02 0xd6 0x00 0x02 0x00 0x00
# GFX10: v_interp_mov_f32_e64 v5, p0, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x04,0x00,0x00]
0x05 0x00 0x02 0xd6 0x00 0x04 0x00 0x00
# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.y ; encoding: [0x05,0x00,0x02,0xd6,0x40,0x00,0x00,0x00]
0x05 0x00 0x02 0xd6 0x40 0x00 0x00 0x00
# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.z ; encoding: [0x05,0x00,0x02,0xd6,0x80,0x00,0x00,0x00]
0x05 0x00 0x02 0xd6 0x80 0x00 0x00 0x00
# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.w ; encoding: [0x05,0x00,0x02,0xd6,0xc0,0x00,0x00,0x00]
0x05 0x00 0x02 0xd6 0xc0 0x00 0x00 0x00
# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x02,0xd6,0x00,0x00,0x00,0x00]
0x05 0x80 0x02 0xd6 0x00 0x00 0x00 0x00
# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x08]
0x05 0x00 0x02 0xd6 0x00 0x00 0x00 0x08
# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x10]
0x05 0x00 0x02 0xd6 0x00 0x00 0x00 0x10
# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x18]
0x05 0x00 0x02 0xd6 0x00 0x00 0x00 0x18
Context not available.