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Differential D68787

[AMDGPU][MC][GFX9][GFX10] Corrected number of src operands for ds_[read/write]_addtid_b32
ClosedPublic

Authored by dp on Oct 10 2019, 6:10 AM.

Details

Reviewers
arsenm
rampitec
Commits
rL374561: [AMDGPU][MC][GFX9][GFX10] Corrected number of src operands for ds_…
rGc4995076c6bd: [AMDGPU][MC][GFX9][GFX10] Corrected number of src operands for ds_…
Summary

LLVM AMDGPU assembler defines ds_read_addtid_b32 and ds_write_addtid_b32 as follows:

  • they have 2 register operands (address + src/dst);
  • they do not read M0.

An example:

ds_read_addtid_b32 v0, v1 offset:65535

This is different from how they are defined in SP3 assembler and how they are described in spec.

GFX9/10 Spec states explicitly that:

  • "no part of the address comes from a VGPR";
  • "M0 is used for: ds_read_addtid_b32, ds_write_addtid_b32".

See GFX10_shader_programming.pdf (pp 62-63).

This is in line with how SP3 assembler handles these opcodes. Here is an example of ds_read_addtid_b32 decoded by SP3 assembler:

ds_read_addtid_b32 v0 offset:65535

See https://bugs.llvm.org/show_bug.cgi?id=37941

Diff Detail

Event Timeline

dp created this revision.Oct 10 2019, 6:10 AM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptOct 10 2019, 6:10 AM
rampitec accepted this revision.Oct 10 2019, 8:02 AM

LGTM

This revision is now accepted and ready to land.Oct 10 2019, 8:02 AM
Closed by commit rGc4995076c6bd: [AMDGPU][MC][GFX9][GFX10] Corrected number of src operands for ds_… (authored by dp). · Explain WhyOct 11 2019, 7:55 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptOct 11 2019, 7:55 AM
Herald added subscribers: llvm-commits, hiraditya. · View Herald Transcript

Revision Contents

PathSize
lib/
Target/
AMDGPU/
23 lines
test/
MC/
AMDGPU/
8 lines
56 lines
4 lines
Disassembler/
AMDGPU/
48 lines

Diff 224321

lib/Target/AMDGPU/DSInstructions.td

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Linesclass DS_Real <DS_Pseudo ds> :
bits<16> offset; bits<16> offset;
let offset0 = !if(ds.has_offset, offset{7-0}, ?); let offset0 = !if(ds.has_offset, offset{7-0}, ?);
let offset1 = !if(ds.has_offset, offset{15-8}, ?); let offset1 = !if(ds.has_offset, offset{15-8}, ?);
} }
// DS Pseudo instructions // DS Pseudo instructions
class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName,
(outs),
(ins rc:$data0, offset:$offset, gds:$gds),
"$data0$offset$gds"> {
let has_addr = 0;
let has_data1 = 0;
let has_vdst = 0;
}
class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32> class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName, : DS_Pseudo<opName,
(outs), (outs),
(ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds), (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
"$addr, $data0$offset$gds"> { "$addr, $data0$offset$gds"> {
let has_data1 = 0; let has_data1 = 0;
let has_vdst = 0; let has_vdst = 0;
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let has_m0_read = 0 in { let has_m0_read = 0 in {
let SubtargetPredicate = HasD16LoadStore in { let SubtargetPredicate = HasD16LoadStore in {
def DS_WRITE_B8_D16_HI : DS_1A1D_NORET<"ds_write_b8_d16_hi">; def DS_WRITE_B8_D16_HI : DS_1A1D_NORET<"ds_write_b8_d16_hi">;
def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">; def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">;
} }
} // End has_m0_read = 0
let SubtargetPredicate = HasDSAddTid in { let SubtargetPredicate = HasDSAddTid in {
def DS_WRITE_ADDTID_B32 : DS_1A1D_NORET<"ds_write_addtid_b32">; def DS_WRITE_ADDTID_B32 : DS_0A1D_NORET<"ds_write_addtid_b32">;
} }
} // End has_m0_read = 0
} // End mayLoad = 0 } // End mayLoad = 0
defm DS_MSKOR_B32 : DS_1A2D_NORET_mc<"ds_mskor_b32">; defm DS_MSKOR_B32 : DS_1A2D_NORET_mc<"ds_mskor_b32">;
defm DS_CMPST_B32 : DS_1A2D_NORET_mc<"ds_cmpst_b32">; defm DS_CMPST_B32 : DS_1A2D_NORET_mc<"ds_cmpst_b32">;
defm DS_CMPST_F32 : DS_1A2D_NORET_mc<"ds_cmpst_f32">; defm DS_CMPST_F32 : DS_1A2D_NORET_mc<"ds_cmpst_f32">;
defm DS_ADD_U64 : DS_1A1D_NORET_mc<"ds_add_u64", VReg_64>; defm DS_ADD_U64 : DS_1A1D_NORET_mc<"ds_add_u64", VReg_64>;
defm DS_SUB_U64 : DS_1A1D_NORET_mc<"ds_sub_u64", VReg_64>; defm DS_SUB_U64 : DS_1A1D_NORET_mc<"ds_sub_u64", VReg_64>;
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let SubtargetPredicate = HasD16LoadStore in { let SubtargetPredicate = HasD16LoadStore in {
def DS_READ_U8_D16 : DS_1A_RET_Tied<"ds_read_u8_d16">; def DS_READ_U8_D16 : DS_1A_RET_Tied<"ds_read_u8_d16">;
def DS_READ_U8_D16_HI : DS_1A_RET_Tied<"ds_read_u8_d16_hi">; def DS_READ_U8_D16_HI : DS_1A_RET_Tied<"ds_read_u8_d16_hi">;
def DS_READ_I8_D16 : DS_1A_RET_Tied<"ds_read_i8_d16">; def DS_READ_I8_D16 : DS_1A_RET_Tied<"ds_read_i8_d16">;
def DS_READ_I8_D16_HI : DS_1A_RET_Tied<"ds_read_i8_d16_hi">; def DS_READ_I8_D16_HI : DS_1A_RET_Tied<"ds_read_i8_d16_hi">;
def DS_READ_U16_D16 : DS_1A_RET_Tied<"ds_read_u16_d16">; def DS_READ_U16_D16 : DS_1A_RET_Tied<"ds_read_u16_d16">;
def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">; def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">;
} }
} // End has_m0_read = 0
let SubtargetPredicate = HasDSAddTid in { let SubtargetPredicate = HasDSAddTid in {
def DS_READ_ADDTID_B32 : DS_1A_RET<"ds_read_addtid_b32">; def DS_READ_ADDTID_B32 : DS_0A_RET<"ds_read_addtid_b32">;
}
} // End has_m0_read = 0
} }
} // End mayStore = 0
def DS_CONSUME : DS_0A_RET<"ds_consume">; def DS_CONSUME : DS_0A_RET<"ds_consume">;
def DS_APPEND : DS_0A_RET<"ds_append">; def DS_APPEND : DS_0A_RET<"ds_append">;
def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">; def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction definitions for CI and newer. // Instruction definitions for CI and newer.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
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test/MC/AMDGPU/ds-gfx9.s

Show All 27 Lines
ds_write_b8_d16_hi v8, v2 ds_write_b8_d16_hi v8, v2
// VI-ERR: error: instruction not supported on this GPU // VI-ERR: error: instruction not supported on this GPU
// GFX9: ds_write_b8_d16_hi v8, v2 ; encoding: [0x00,0x00,0xa8,0xd8,0x08,0x02,0x00,0x00] // GFX9: ds_write_b8_d16_hi v8, v2 ; encoding: [0x00,0x00,0xa8,0xd8,0x08,0x02,0x00,0x00]
ds_write_b16_d16_hi v8, v2 ds_write_b16_d16_hi v8, v2
// VI-ERR: error: instruction not supported on this GPU // VI-ERR: error: instruction not supported on this GPU
// GFX9: ds_write_b16_d16_hi v8, v2 ; encoding: [0x00,0x00,0xaa,0xd8,0x08,0x02,0x00,0x00] // GFX9: ds_write_b16_d16_hi v8, v2 ; encoding: [0x00,0x00,0xaa,0xd8,0x08,0x02,0x00,0x00]
ds_write_addtid_b32 v8, v2 ds_write_addtid_b32 v8
// VI-ERR: error: instruction not supported on this GPU // VI-ERR: error: instruction not supported on this GPU
// GFX9: ds_write_addtid_b32 v8, v2 ; encoding: [0x00,0x00,0x3a,0xd8,0x08,0x02,0x00,0x00] // GFX9: ds_write_addtid_b32 v8 ; encoding: [0x00,0x00,0x3a,0xd8,0x00,0x08,0x00,0x00]
ds_read_addtid_b32 v8, v2 ds_read_addtid_b32 v8
// VI-ERR: error: instruction not supported on this GPU // VI-ERR: error: instruction not supported on this GPU
// GFX9: ds_read_addtid_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd9,0x02,0x00,0x00,0x08] // GFX9: ds_read_addtid_b32 v8 ; encoding: [0x00,0x00,0x6c,0xd9,0x00,0x00,0x00,0x08]

test/MC/AMDGPU/gfx10_asm_all.s

Context not available.
ds_read_u16_d16_hi v5, v1 offset:65535 gds ds_read_u16_d16_hi v5, v1 offset:65535 gds
// GFX10: encoding: [0xff,0xff,0x9e,0xda,0x01,0x00,0x00,0x05] // GFX10: encoding: [0xff,0xff,0x9e,0xda,0x01,0x00,0x00,0x05]
ds_write_addtid_b32 v5, v1 offset:65535 ds_write_addtid_b32 v5 offset:65535
// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x05,0x01,0x00,0x00] // GFX10: encoding: [0xff,0xff,0xc0,0xda,0x00,0x05,0x00,0x00]
ds_write_addtid_b32 v255, v1 offset:65535 ds_write_addtid_b32 v255 offset:65535
// GFX10: encoding: [0xff,0xff,0xc0,0xda,0xff,0x01,0x00,0x00] // GFX10: encoding: [0xff,0xff,0xc0,0xda,0x00,0xff,0x00,0x00]
ds_write_addtid_b32 v5, v255 offset:65535 ds_write_addtid_b32 v5 offset:65535
// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x05,0xff,0x00,0x00] // GFX10: encoding: [0xff,0xff,0xc0,0xda,0x00,0x05,0x00,0x00]
ds_write_addtid_b32 v5, v1 ds_write_addtid_b32 v5
// GFX10: encoding: [0x00,0x00,0xc0,0xda,0x05,0x01,0x00,0x00] // GFX10: encoding: [0x00,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
ds_write_addtid_b32 v5, v1 offset:0 ds_write_addtid_b32 v5 offset:0
// GFX10: encoding: [0x00,0x00,0xc0,0xda,0x05,0x01,0x00,0x00] // GFX10: encoding: [0x00,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
ds_write_addtid_b32 v5, v1 offset:4 ds_write_addtid_b32 v5 offset:4
// GFX10: encoding: [0x04,0x00,0xc0,0xda,0x05,0x01,0x00,0x00] // GFX10: encoding: [0x04,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
ds_write_addtid_b32 v5, v1 offset:65535 gds ds_write_addtid_b32 v5 offset:65535 gds
// GFX10: encoding: [0xff,0xff,0xc2,0xda,0x05,0x01,0x00,0x00] // GFX10: encoding: [0xff,0xff,0xc2,0xda,0x00,0x05,0x00,0x00]
ds_read_addtid_b32 v5, v1 offset:65535 ds_read_addtid_b32 v5 offset:65535
// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x01,0x00,0x00,0x05] // GFX10: encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0x05]
ds_read_addtid_b32 v255, v1 offset:65535 ds_read_addtid_b32 v255 offset:65535
// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x01,0x00,0x00,0xff] // GFX10: encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0xff]
ds_read_addtid_b32 v5, v255 offset:65535 ds_read_addtid_b32 v5 offset:65535
// GFX10: encoding: [0xff,0xff,0xc4,0xda,0xff,0x00,0x00,0x05] // GFX10: encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0x05]
ds_read_addtid_b32 v5, v1 ds_read_addtid_b32 v5
// GFX10: encoding: [0x00,0x00,0xc4,0xda,0x01,0x00,0x00,0x05] // GFX10: encoding: [0x00,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
ds_read_addtid_b32 v5, v1 offset:0 ds_read_addtid_b32 v5 offset:0
// GFX10: encoding: [0x00,0x00,0xc4,0xda,0x01,0x00,0x00,0x05] // GFX10: encoding: [0x00,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
ds_read_addtid_b32 v5, v1 offset:4 ds_read_addtid_b32 v5 offset:4
// GFX10: encoding: [0x04,0x00,0xc4,0xda,0x01,0x00,0x00,0x05] // GFX10: encoding: [0x04,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
ds_read_addtid_b32 v5, v1 offset:65535 gds ds_read_addtid_b32 v5 offset:65535 gds
// GFX10: encoding: [0xff,0xff,0xc6,0xda,0x01,0x00,0x00,0x05] // GFX10: encoding: [0xff,0xff,0xc6,0xda,0x00,0x00,0x00,0x05]
ds_permute_b32 v0, v1, v2 ds_permute_b32 v0, v1, v2
// GFX10: encoding: [0x00,0x00,0xc8,0xda,0x01,0x02,0x00,0x00] // GFX10: encoding: [0x00,0x00,0xc8,0xda,0x01,0x02,0x00,0x00]
Context not available.

test/MC/AMDGPU/gfx10_asm_err.s

Show All 29 Lines
// GFX6-8: error: instruction not supported on this GPU // GFX6-8: error: instruction not supported on this GPU
ds_read_u16_d16 v5, v1 ds_read_u16_d16 v5, v1
// GFX6-8: error: instruction not supported on this GPU // GFX6-8: error: instruction not supported on this GPU
ds_read_u16_d16_hi v5, v1 ds_read_u16_d16_hi v5, v1
// GFX6-8: error: instruction not supported on this GPU // GFX6-8: error: instruction not supported on this GPU
ds_write_addtid_b32 v5, v1 ds_write_addtid_b32 v5
// GFX6-8: error: instruction not supported on this GPU // GFX6-8: error: instruction not supported on this GPU
ds_read_addtid_b32 v5, v1 ds_read_addtid_b32 v5
// GFX6-8: error: instruction not supported on this GPU // GFX6-8: error: instruction not supported on this GPU
// GFX8+. // GFX8+.
ds_add_src2_f32 v1 ds_add_src2_f32 v1
// GFX6-7: error: instruction not supported on this GPU // GFX6-7: error: instruction not supported on this GPU
ds_add_f32 v0, v1 ds_add_f32 v0, v1
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test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

Context not available.
# GFX10: ds_read2st64_b64 v[5:8], v255 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0xe0,0xd9,0xff,0x00,0x00,0x05] # GFX10: ds_read2st64_b64 v[5:8], v255 offset0:127 offset1:255 ; encoding: [0x7f,0xff,0xe0,0xd9,0xff,0x00,0x00,0x05]
0x7f,0xff,0xe0,0xd9,0xff,0x00,0x00,0x05 0x7f,0xff,0xe0,0xd9,0xff,0x00,0x00,0x05
# GFX10: ds_read_addtid_b32 v255, v1 offset:65535 ; encoding: [0xff,0xff,0xc4,0xda,0x01,0x00,0x00,0xff] # GFX10: ds_read_addtid_b32 v255 offset:65535 ; encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0xff]
0xff,0xff,0xc4,0xda,0x01,0x00,0x00,0xff 0xff 0xff 0xc4 0xda 0x00 0x00 0x00 0xff
# GFX10: ds_read_addtid_b32 v5, v1 ; encoding: [0x00,0x00,0xc4,0xda,0x01,0x00,0x00,0x05] # GFX10: ds_read_addtid_b32 v5 ; encoding: [0x00,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
0x00,0x00,0xc4,0xda,0x01,0x00,0x00,0x05 0x00 0x00 0xc4 0xda 0x00 0x00 0x00 0x05
# GFX10: ds_read_addtid_b32 v5, v1 offset:4 ; encoding: [0x04,0x00,0xc4,0xda,0x01,0x00,0x00,0x05] # GFX10: ds_read_addtid_b32 v5 offset:4 ; encoding: [0x04,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
0x04,0x00,0xc4,0xda,0x01,0x00,0x00,0x05 0x04 0x00 0xc4 0xda 0x00 0x00 0x00 0x05
# GFX10: ds_read_addtid_b32 v5, v1 offset:65535 ; encoding: [0xff,0xff,0xc4,0xda,0x01,0x00,0x00,0x05] # GFX10: ds_read_addtid_b32 v5 offset:65535 ; encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0x05]
0xff,0xff,0xc4,0xda,0x01,0x00,0x00,0x05 0xff 0xff 0xc4 0xda 0x00 0x00 0x00 0x05
# GFX10: ds_read_addtid_b32 v5, v1 offset:65535 gds ; encoding: [0xff,0xff,0xc6,0xda,0x01,0x00,0x00,0x05] # GFX10: ds_read_addtid_b32 v5 offset:65535 gds ; encoding: [0xff,0xff,0xc6,0xda,0x00,0x00,0x00,0x05]
0xff,0xff,0xc6,0xda,0x01,0x00,0x00,0x05 0xff 0xff 0xc6 0xda 0x00 0x00 0x00 0x05
# GFX10: ds_read_addtid_b32 v5, v255 offset:65535 ; encoding: [0xff,0xff,0xc4,0xda,0xff,0x00,0x00,0x05] # GFX10: ds_read_addtid_b32 v5 offset:65535 ; encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0x05]
0xff,0xff,0xc4,0xda,0xff,0x00,0x00,0x05 0xff 0xff 0xc4 0xda 0x00 0x00 0x00 0x05
# GFX10: ds_read_b128 v[252:255], v1 offset:65535 ; encoding: [0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0xfc] # GFX10: ds_read_b128 v[252:255], v1 offset:65535 ; encoding: [0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0xfc]
0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0xfc 0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0xfc
Context not available.
# GFX10: ds_write2st64_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255 ; encoding: [0x7f,0xff,0x3c,0xd9,0xff,0x02,0x03,0x00] # GFX10: ds_write2st64_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255 ; encoding: [0x7f,0xff,0x3c,0xd9,0xff,0x02,0x03,0x00]
0x7f,0xff,0x3c,0xd9,0xff,0x02,0x03,0x00 0x7f,0xff,0x3c,0xd9,0xff,0x02,0x03,0x00
# GFX10: ds_write_addtid_b32 v255, v1 offset:65535 ; encoding: [0xff,0xff,0xc0,0xda,0xff,0x01,0x00,0x00] # GFX10: ds_write_addtid_b32 v255 offset:65535 ; encoding: [0xff,0xff,0xc0,0xda,0x00,0xff,0x00,0x00]
0xff,0xff,0xc0,0xda,0xff,0x01,0x00,0x00 0xff 0xff 0xc0 0xda 0x00 0xff 0x00 0x00
# GFX10: ds_write_addtid_b32 v5, v1 ; encoding: [0x00,0x00,0xc0,0xda,0x05,0x01,0x00,0x00] # GFX10: ds_write_addtid_b32 v5 ; encoding: [0x00,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
0x00,0x00,0xc0,0xda,0x05,0x01,0x00,0x00 0x00 0x00 0xc0 0xda 0x00 0x05 0x00 0x00
# GFX10: ds_write_addtid_b32 v5, v1 offset:4 ; encoding: [0x04,0x00,0xc0,0xda,0x05,0x01,0x00,0x00] # GFX10: ds_write_addtid_b32 v5 offset:4 ; encoding: [0x04,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
0x04,0x00,0xc0,0xda,0x05,0x01,0x00,0x00 0x04 0x00 0xc0 0xda 0x00 0x05 0x00 0x00
# GFX10: ds_write_addtid_b32 v5, v1 offset:65535 ; encoding: [0xff,0xff,0xc0,0xda,0x05,0x01,0x00,0x00] # GFX10: ds_write_addtid_b32 v5 offset:65535 ; encoding: [0xff,0xff,0xc0,0xda,0x00,0x05,0x00,0x00]
0xff,0xff,0xc0,0xda,0x05,0x01,0x00,0x00 0xff 0xff 0xc0 0xda 0x00 0x05 0x00 0x00
# GFX10: ds_write_addtid_b32 v5, v1 offset:65535 gds ; encoding: [0xff,0xff,0xc2,0xda,0x05,0x01,0x00,0x00] # GFX10: ds_write_addtid_b32 v5 offset:65535 gds ; encoding: [0xff,0xff,0xc2,0xda,0x00,0x05,0x00,0x00]
0xff,0xff,0xc2,0xda,0x05,0x01,0x00,0x00 0xff 0xff 0xc2 0xda 0x00 0x05 0x00 0x00
# GFX10: ds_write_addtid_b32 v5, v255 offset:65535 ; encoding: [0xff,0xff,0xc0,0xda,0x05,0xff,0x00,0x00] # GFX10: ds_write_addtid_b32 v5 offset:65535 ; encoding: [0xff,0xff,0xc0,0xda,0x00,0x05,0x00,0x00]
0xff,0xff,0xc0,0xda,0x05,0xff,0x00,0x00 0xff 0xff 0xc0 0xda 0x00 0x05 0x00 0x00
# GFX10: ds_write_b128 v1, v[252:255] offset:65535 ; encoding: [0xff,0xff,0x7c,0xdb,0x01,0xfc,0x00,0x00] # GFX10: ds_write_b128 v1, v[252:255] offset:65535 ; encoding: [0xff,0xff,0x7c,0xdb,0x01,0xfc,0x00,0x00]
0xff,0xff,0x7c,0xdb,0x01,0xfc,0x00,0x00 0xff,0xff,0x7c,0xdb,0x01,0xfc,0x00,0x00
Context not available.