LiveIntervals: Split live intervals on multiple dead defs

[kparzysz]

Summary

This is a follow-up to D67448.

Split live intervals with multiple dead defs during the initial execution of the live interval analysis, but do it outside of the function createAndComputeVirtRegInterval.

[arsenm]

LGTM

include/llvm/CodeGen/LiveIntervals.h

private:
 
     static LiveInterval* createInterval(unsigned Reg);
 
     void printInstrs(raw_ostream &O) const;
     void dumpInstrs() const;
 
     void computeLiveInRegUnits();
     void computeRegUnitRange(LiveRange&, unsigned Unit);
-    void computeVirtRegInterval(LiveInterval&);
+    bool computeVirtRegInterval(LiveInterval&);
 
     using ShrinkToUsesWorkList = SmallVector<std::pair<SlotIndex, VNInfo*>, 16>;
     void extendSegmentsToUses(LiveRange &Segments,
                               ShrinkToUsesWorkList &WorkList, unsigned Reg,
                               LaneBitmask LaneMask);
 
     /// Helper function for repairIntervalsInRange(), walks backwards and
     /// creates/modifies live segments in \p LR to match the operands found.

lib/CodeGen/LiveIntervals.cpp

 #endif
 
 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
   float Weight = Register::isPhysicalRegister(reg) ? huge_valf : 0.0F;
   return new LiveInterval(reg, Weight);
 }
 
 /// Compute the live interval of a virtual register, based on defs and uses.
-void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
+bool LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
   assert(LRCalc && "LRCalc not initialized.");
   assert(LI.empty() && "Should only compute empty intervals.");
   LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
   LRCalc->calculate(LI, MRI->shouldTrackSubRegLiveness(LI.reg));
-  computeDeadValues(LI, nullptr);
+  return computeDeadValues(LI, nullptr);
 }
 
 void LiveIntervals::computeVirtRegs() {
   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
     unsigned Reg = Register::index2VirtReg(i);
     if (MRI->reg_nodbg_empty(Reg))
       continue;
-    createAndComputeVirtRegInterval(Reg);
+    LiveInterval &LI = createEmptyInterval(Reg);
+    bool NeedSplit = computeVirtRegInterval(LI);
+    if (NeedSplit) {
+      SmallVector<LiveInterval*, 8> SplitLIs;
+      splitSeparateComponents(LI, SplitLIs);
+    }
   }
 }
 
 void LiveIntervals::computeRegMasks() {
   RegMaskBlocks.resize(MF->getNumBlockIDs());
 
   // Find all instructions with regmask operands.
   for (const MachineBasicBlock &MBB : *MF) {
bool LiveIntervals::shrinkToUses(LiveInterval *li,
   bool CanSeparate = computeDeadValues(*li, dead);
   LLVM_DEBUG(dbgs() << "Shrunk: " << *li << '\n');
   return CanSeparate;
 }
 
 bool LiveIntervals::computeDeadValues(LiveInterval &LI,
                                       SmallVectorImpl<MachineInstr*> *dead) {
   bool MayHaveSplitComponents = false;
+  bool HaveDeadDef = false;
+
   for (VNInfo *VNI : LI.valnos) {
     if (VNI->isUnused())
       continue;
     SlotIndex Def = VNI->def;
     LiveRange::iterator I = LI.FindSegmentContaining(Def);
     assert(I != LI.end() && "Missing segment for VNI");
 
     // Is the register live before? Otherwise we may have to add a read-undef
if (VNI->isPHIDef()) {
       LI.removeSegment(I);
       LLVM_DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n");
       MayHaveSplitComponents = true;
     } else {
       // This is a dead def. Make sure the instruction knows.
       MachineInstr *MI = getInstructionFromIndex(Def);
       assert(MI && "No instruction defining live value");
       MI->addRegisterDead(LI.reg, TRI);
+      if (HaveDeadDef)
+        MayHaveSplitComponents = true;
+      HaveDeadDef = true;
+
       if (dead && MI->allDefsAreDead()) {
         LLVM_DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);
         dead->push_back(MI);
       }
     }
   }
   return MayHaveSplitComponents;
 }

test/CodeGen/AMDGPU/live-intervals-multiple-dead-defs.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
+
+# There are multiple dead defs of the same virtual register. Make sure
+# the intervals are split during the initial live range computation.
+
+---
+name:            multiple_connected_components_dead
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: multiple_connected_components_dead
+    ; CHECK: dead %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; CHECK: dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    dead %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+
+...
+

test/DebugInfo/WebAssembly/dbg-value-move-reg-stackify.mir

 # RUN: llc < %s -run-pass=wasm-reg-stackify -x=mir 2>&1 | FileCheck %s
 
 # CHECK: body:
-# CHECK: %1:i32 = I32_WRAP_I64 %0,
-# CHECK-NEXT: DBG_VALUE %1,
-# CHECK-NEXT: %1:i32 = CALL_i32 @bar,
-# CHECK-NEXT: DBG_VALUE %1,
+# CHECK: dead %3:i32 = I32_WRAP_I64 %0,
+# CHECK-NEXT: DBG_VALUE %1:i32
+# CHECK-NEXT: dead %2:i32 = CALL_i32 @bar,
+# CHECK-NEXT: DBG_VALUE %1:i32,
 # CHECK-NEXT: %[[NEWREG:.*]]:i32 = CALL_i32 @bar,
 # CHECK-NEXT: DBG_VALUE %[[NEWREG]],
 # CHECK-NEXT: CALL_VOID @foo, %[[NEWREG]],
 
 --- |
   target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
   target triple = "wasm32-unknown-unknown"
 

test/DebugInfo/X86/live-debug-vars-discard-invalid.mir

-# FIXME: Fix machine verifier issues and remove -verify-machineinstrs=0. PR39481.
-# RUN: llc -mtriple=x86_64-linux-gnu -start-before greedy -stop-after virtregrewriter -o - -verify-machineinstrs=0 %s | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -start-before greedy -stop-after virtregrewriter -o - -verify-machineinstrs %s | FileCheck %s
 
 --- |
   ; ModuleID = '<stdin>'
   source_filename = "test/DebugInfo/X86/dbg-value-inlined-parameter.ll"
   target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
   target triple = "x86_64-apple-darwin"
 
   %struct.S1 = type { float*, i32 }

 # CHECK:        DBG_VALUE $noreg
 
 # CHECK-LABEL: bb.2:
 # CHECK:        DBG_VALUE $noreg
 # CHECK-NEXT:   dead renamable $rcx = IMPLICIT_DEF
 # CHECK-NEXT:   dead renamable $rcx = IMPLICIT_DEF
 # CHECK-NEXT:   dead renamable $rcx = IMPLICIT_DEF
 # CHECK-NEXT:   dead renamable $rcx = IMPLICIT_DEF
-# CHECK-NEXT:   DBG_VALUE $rcx, $noreg, !18, !DIExpression()
+# CHECK-NEXT:   DBG_VALUE $noreg, $noreg, !18, !DIExpression()
 
 # CHECK-LABEL: bb.3:
 # CHECK:        dead renamable $rcx = IMPLICIT_DEF
 # CHECK-NEXT:   DBG_VALUE 0, $noreg, !23, !DIExpression()
 # CHECK-NEXT:   DBG_VALUE $rcx, $noreg, !18, !DIExpression()
 
 # CHECK-LABEL: bb.4:
 # CHECK:        liveins: $rax