LiveIntervals: Split live intervals on multiple dead defs

[arsenm]

Summary

If there are multiple dead defs of the same virtual register, these
are required to be split into multiple virtual registers with separate
live intervals to avoid a verifier error.

[qcolombet]

LGTM

[arsenm]

r371640

lib/CodeGen/LiveIntervals.cpp

 }
 
 /// Compute the live interval of a virtual register, based on defs and uses.
 void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
   assert(LRCalc && "LRCalc not initialized.");
   assert(LI.empty() && "Should only compute empty intervals.");
   LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
   LRCalc->calculate(LI, MRI->shouldTrackSubRegLiveness(LI.reg));
-  computeDeadValues(LI, nullptr);
+
+  if (computeDeadValues(LI, nullptr)) {
+    SmallVector<LiveInterval *, 4> SplitIntervals;
+    splitSeparateComponents(LI, SplitIntervals);
+  }
 }
 
 void LiveIntervals::computeVirtRegs() {
   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
     unsigned Reg = Register::index2VirtReg(i);
     if (MRI->reg_nodbg_empty(Reg))
       continue;
     createAndComputeVirtRegInterval(Reg);
bool LiveIntervals::shrinkToUses(LiveInterval *li,
   bool CanSeparate = computeDeadValues(*li, dead);
   LLVM_DEBUG(dbgs() << "Shrunk: " << *li << '\n');
   return CanSeparate;
 }
 
 bool LiveIntervals::computeDeadValues(LiveInterval &LI,
                                       SmallVectorImpl<MachineInstr*> *dead) {
   bool MayHaveSplitComponents = false;
+  bool HaveDeadDef = false;
+
   for (VNInfo *VNI : LI.valnos) {
     if (VNI->isUnused())
       continue;
     SlotIndex Def = VNI->def;
     LiveRange::iterator I = LI.FindSegmentContaining(Def);
     assert(I != LI.end() && "Missing segment for VNI");
 
     // Is the register live before? Otherwise we may have to add a read-undef
if (VNI->isPHIDef()) {
       LI.removeSegment(I);
       LLVM_DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n");
       MayHaveSplitComponents = true;
     } else {
       // This is a dead def. Make sure the instruction knows.
       MachineInstr *MI = getInstructionFromIndex(Def);
       assert(MI && "No instruction defining live value");
       MI->addRegisterDead(LI.reg, TRI);
+      if (HaveDeadDef)
+        MayHaveSplitComponents = true;
+      HaveDeadDef = true;
+
       if (dead && MI->allDefsAreDead()) {
         LLVM_DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);
         dead->push_back(MI);
       }
     }
   }
   return MayHaveSplitComponents;
 }

test/CodeGen/AMDGPU/live-intervals-multiple-dead-defs.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
+
+# There are multiple dead defs of the same virtual register. Make sure
+# the intervals are split during the initial live range computation.
+
+---
+name:            multiple_connected_components_dead
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: multiple_connected_components_dead
+    ; CHECK: dead %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; CHECK: dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    dead %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+
+...