[PowerPC] Fix VSX clobbers of CSR registers

[nemanjai]

Summary

If an inline asm statement clobbers a VSX register that overlaps with a callee-saved Altivec register or FPR, we will not record the clobber and will therefore violate the ABI. This is clearly a bug so this patch fixes it.

[amyk]

test/CodeGen/PowerPC/inline-asm-vsx-clobbers.ll

2 ↗

(On Diff #223596)

Should we add -verify-machineinstrs to the test case?

[nemanjai]

test/CodeGen/PowerPC/inline-asm-vsx-clobbers.ll

2 ↗

(On Diff #223596)

Yup. We should. I'll add it on the next revision.

[lei]

LGTM.
Please address Amy's comment on commit.

[jsji]

LGTM as well.

lib/Target/PowerPC/PPCISelLowering.cpp

14320 ↗

(On Diff #223596)

Do we need to consider 32 or 64 bits regclass here? If not, maybe we should add some comments to explain?

test/CodeGen/PowerPC/inline-asm-vsx-clobbers.ll

3 ↗

(On Diff #223596)

Why we need -enable-ppc-quad-precision here?

[nemanjai]

Thanks for your comments. I'll address them and commit this.

lib/Target/PowerPC/PPCISelLowering.cpp

14320 ↗

(On Diff #223596)

I believe you mean VSSRC/VSFRC (i.e. the scalar VSX registers). I believe those have to be named as f<N> or vs<N> in the clobbers list so we should still handle them correctly.

test/CodeGen/PowerPC/inline-asm-vsx-clobbers.ll

3 ↗

(On Diff #223596)

Ha ha, good catch. That's just an errant option. I'll remove it on the commit.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (Constraint.size() == 1) {
     return std::make_pair(0U, &PPC::VSRCRegClass);
   } else if ((Constraint == "ws" || Constraint == "ww") && Subtarget.hasVSX()) {
     if (VT == MVT::f32 && Subtarget.hasP8Vector())
       return std::make_pair(0U, &PPC::VSSRCRegClass);
     else
       return std::make_pair(0U, &PPC::VSFRCRegClass);
   }
 
+  // If we name a VSX register, we can't defer to the base class because it
+  // will not recognize the correct register (their names will be VSL{0-31}
+  // and V{0-31} so they won't match). So we match them here.
+  if (Constraint.size() > 3 && Constraint[1] == 'v' && Constraint[2] == 's') {
+    int VSNum = atoi(Constraint.data() + 3);
+    assert(VSNum >= 0 && VSNum <= 63 &&
+           "Attempted to access a vsr out of range");
+    if (VSNum < 32)
+      return std::make_pair(PPC::VSL0 + VSNum, &PPC::VSRCRegClass);
+    return std::make_pair(PPC::V0 + VSNum - 32, &PPC::VSRCRegClass);
+  }
   std::pair<unsigned, const TargetRegisterClass *> R =
       TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
 
   // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
   // (which we call X[0-9]+). If a 64-bit value has been requested, and a
   // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
   // register.
   // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use

llvm/test/CodeGen/PowerPC/CSR-fit.ll

entry:
   ret i32 %call
 }
 
 define dso_local signext i32 @caller4(i32 signext %a, i32 signext %b) local_unnamed_addr {
 ; CHECK-PWR8-LABEL: caller4:
 ; CHECK-PWR8:       # %bb.0: # %entry
 ; CHECK-PWR8-NEXT:    mflr r0
 ; CHECK-PWR8-NEXT:    std r0, 16(r1)
-; CHECK-PWR8-NEXT:    stdu r1, -32(r1)
-; CHECK-PWR8-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-PWR8-NEXT:    stdu r1, -240(r1)
+; CHECK-PWR8-NEXT:    .cfi_def_cfa_offset 240
 ; CHECK-PWR8-NEXT:    .cfi_offset lr, 16
+; CHECK-PWR8-NEXT:    .cfi_offset v20, -192
+; CHECK-PWR8-NEXT:    .cfi_offset v21, -176
+; CHECK-PWR8-NEXT:    li r5, 48
+; CHECK-PWR8-NEXT:    stxvd2x v20, r1, r5 # 16-byte Folded Spill
+; CHECK-PWR8-NEXT:    li r5, 64
+; CHECK-PWR8-NEXT:    stxvd2x v21, r1, r5 # 16-byte Folded Spill
 ; CHECK-PWR8-NEXT:    #APP
 ; CHECK-PWR8-NEXT:    add r3, r3, r4
 ; CHECK-PWR8-NEXT:    #NO_APP
 ; CHECK-PWR8-NEXT:    extsw r3, r3
 ; CHECK-PWR8-NEXT:    bl callee
 ; CHECK-PWR8-NEXT:    nop
-; CHECK-PWR8-NEXT:    addi r1, r1, 32
+; CHECK-PWR8-NEXT:    li r4, 64
+; CHECK-PWR8-NEXT:    lxvd2x v21, r1, r4 # 16-byte Folded Reload
+; CHECK-PWR8-NEXT:    li r4, 48
+; CHECK-PWR8-NEXT:    lxvd2x v20, r1, r4 # 16-byte Folded Reload
+; CHECK-PWR8-NEXT:    addi r1, r1, 240
 ; CHECK-PWR8-NEXT:    ld r0, 16(r1)
 ; CHECK-PWR8-NEXT:    mtlr r0
 ; CHECK-PWR8-NEXT:    blr
 ;
 ; CHECK-PWR9-LABEL: caller4:
 ; CHECK-PWR9:       # %bb.0: # %entry
 ; CHECK-PWR9-NEXT:    mflr r0
 ; CHECK-PWR9-NEXT:    std r0, 16(r1)
-; CHECK-PWR9-NEXT:    stdu r1, -32(r1)
-; CHECK-PWR9-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-PWR9-NEXT:    stdu r1, -224(r1)
+; CHECK-PWR9-NEXT:    .cfi_def_cfa_offset 224
 ; CHECK-PWR9-NEXT:    .cfi_offset lr, 16
+; CHECK-PWR9-NEXT:    .cfi_offset v20, -192
+; CHECK-PWR9-NEXT:    .cfi_offset v21, -176
+; CHECK-PWR9-NEXT:    stxv v20, 32(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    stxv v21, 48(r1) # 16-byte Folded Spill
 ; CHECK-PWR9-NEXT:    #APP
 ; CHECK-PWR9-NEXT:    add r3, r3, r4
 ; CHECK-PWR9-NEXT:    #NO_APP
 ; CHECK-PWR9-NEXT:    extsw r3, r3
 ; CHECK-PWR9-NEXT:    bl callee
 ; CHECK-PWR9-NEXT:    nop
-; CHECK-PWR9-NEXT:    addi r1, r1, 32
+; CHECK-PWR9-NEXT:    lxv v21, 48(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    lxv v20, 32(r1) # 16-byte Folded Reload
+; CHECK-PWR9-NEXT:    addi r1, r1, 224
 ; CHECK-PWR9-NEXT:    ld r0, 16(r1)
 ; CHECK-PWR9-NEXT:    mtlr r0
 ; CHECK-PWR9-NEXT:    blr
 entry:
   %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{vs52},~{vs53}"(i32 %a, i32 %b)
   %call = tail call signext i32 @callee(i32 signext %0)
   ret i32 %call
 }
 
 define dso_local signext i32 @caller_mixed(i32 signext %a, i32 signext %b) local_unnamed_addr {
 ; CHECK-PWR8-LABEL: caller_mixed:
 ; CHECK-PWR8:       # %bb.0: # %entry
 ; CHECK-PWR8-NEXT:    mflr r0
 ; CHECK-PWR8-NEXT:    std r0, 16(r1)
 ; CHECK-PWR8-NEXT:    stdu r1, -528(r1)
 ; CHECK-PWR8-NEXT:    .cfi_def_cfa_offset 528
 ; CHECK-PWR8-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR8-NEXT:    .cfi_offset r14, -288
 ; CHECK-PWR8-NEXT:    .cfi_offset f14, -144
 ; CHECK-PWR8-NEXT:    .cfi_offset v20, -480
+; CHECK-PWR8-NEXT:    .cfi_offset v21, -464
 ; CHECK-PWR8-NEXT:    li r5, 48
 ; CHECK-PWR8-NEXT:    std r14, 240(r1) # 8-byte Folded Spill
 ; CHECK-PWR8-NEXT:    stfd f14, 384(r1) # 8-byte Folded Spill
 ; CHECK-PWR8-NEXT:    stxvd2x v20, r1, r5 # 16-byte Folded Spill
+; CHECK-PWR8-NEXT:    li r5, 64
+; CHECK-PWR8-NEXT:    stxvd2x v21, r1, r5 # 16-byte Folded Spill
 ; CHECK-PWR8-NEXT:    #APP
 ; CHECK-PWR8-NEXT:    add r3, r3, r4
 ; CHECK-PWR8-NEXT:    #NO_APP
 ; CHECK-PWR8-NEXT:    extsw r3, r3
 ; CHECK-PWR8-NEXT:    bl callee
 ; CHECK-PWR8-NEXT:    nop
-; CHECK-PWR8-NEXT:    li r4, 48
+; CHECK-PWR8-NEXT:    li r4, 64
 ; CHECK-PWR8-NEXT:    lfd f14, 384(r1) # 8-byte Folded Reload
 ; CHECK-PWR8-NEXT:    ld r14, 240(r1) # 8-byte Folded Reload
+; CHECK-PWR8-NEXT:    lxvd2x v21, r1, r4 # 16-byte Folded Reload
+; CHECK-PWR8-NEXT:    li r4, 48
 ; CHECK-PWR8-NEXT:    lxvd2x v20, r1, r4 # 16-byte Folded Reload
 ; CHECK-PWR8-NEXT:    addi r1, r1, 528
 ; CHECK-PWR8-NEXT:    ld r0, 16(r1)
 ; CHECK-PWR8-NEXT:    mtlr r0
 ; CHECK-PWR8-NEXT:    blr
 ;
 ; CHECK-PWR9-LABEL: caller_mixed:
 ; CHECK-PWR9:       # %bb.0: # %entry
 ; CHECK-PWR9-NEXT:    mflr r0
 ; CHECK-PWR9-NEXT:    std r0, 16(r1)
 ; CHECK-PWR9-NEXT:    stdu r1, -512(r1)
 ; CHECK-PWR9-NEXT:    .cfi_def_cfa_offset 512
 ; CHECK-PWR9-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR9-NEXT:    .cfi_offset r14, -288
 ; CHECK-PWR9-NEXT:    .cfi_offset f14, -144
 ; CHECK-PWR9-NEXT:    .cfi_offset v20, -480
+; CHECK-PWR9-NEXT:    .cfi_offset v21, -464
 ; CHECK-PWR9-NEXT:    std r14, 224(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    stfd f14, 368(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    stxv v20, 32(r1) # 16-byte Folded Spill
+; CHECK-PWR9-NEXT:    stxv v21, 48(r1) # 16-byte Folded Spill
 ; CHECK-PWR9-NEXT:    #APP
 ; CHECK-PWR9-NEXT:    add r3, r3, r4
 ; CHECK-PWR9-NEXT:    #NO_APP
 ; CHECK-PWR9-NEXT:    extsw r3, r3
 ; CHECK-PWR9-NEXT:    bl callee
 ; CHECK-PWR9-NEXT:    nop
+; CHECK-PWR9-NEXT:    lxv v21, 48(r1) # 16-byte Folded Reload
 ; CHECK-PWR9-NEXT:    lxv v20, 32(r1) # 16-byte Folded Reload
 ; CHECK-PWR9-NEXT:    lfd f14, 368(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    ld r14, 224(r1) # 8-byte Folded Reload
 ; CHECK-PWR9-NEXT:    addi r1, r1, 512
 ; CHECK-PWR9-NEXT:    ld r0, 16(r1)
 ; CHECK-PWR9-NEXT:    mtlr r0
 ; CHECK-PWR9-NEXT:    blr
 entry:
   %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{f14},~{v20},~{vs53}"(i32 %a, i32 %b)
   %call = tail call signext i32 @callee(i32 signext %0)
   ret i32 %call
 }
 
 

llvm/test/CodeGen/PowerPC/inline-asm-vsx-clobbers.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -verify-machineinstrs -ppc-vsr-nums-as-vr \
+; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s
+
+define dso_local void @clobberVR(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
+; CHECK-LABEL: clobberVR:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stxv v22, -160(r1) # 16-byte Folded Spill
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    lxv v22, -160(r1) # 16-byte Folded Reload
+; CHECK-NEXT:    blr
+entry:
+  tail call void asm sideeffect "nop", "~{vs54}"()
+  ret void
+}
+
+define dso_local void @clobberFPR(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
+; CHECK-LABEL: clobberFPR:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stfd f14, -144(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    lfd f14, -144(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    blr
+entry:
+  tail call void asm sideeffect "nop", "~{vs14}"()
+  ret void
+}