[ARM] VQSUB instruction

[dmgreen]

Summary

Same as VQADD, VQSUB can be selected from llvm.ssub.sat intrinsics.

[dmgreen]

Ping. This is the same as D68566, just for subs. Look OK?

[SjoerdMeijer]

Yep, looks good to me.

[dmgreen]

Cheers

llvm/lib/Target/ARM/ARMISelLowering.cpp

for (auto VT : IntTypes) {
     setOperationAction(ISD::CTLZ, VT, Legal);
     setOperationAction(ISD::CTTZ, VT, Custom);
     setOperationAction(ISD::BITREVERSE, VT, Legal);
     setOperationAction(ISD::BSWAP, VT, Legal);
     setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
     setOperationAction(ISD::AND, VT, Custom);
     setOperationAction(ISD::SADDSAT, VT, Legal);
     setOperationAction(ISD::UADDSAT, VT, Legal);
+    setOperationAction(ISD::SSUBSAT, VT, Legal);
+    setOperationAction(ISD::USUBSAT, VT, Legal);
 
     // No native support for these.
     setOperationAction(ISD::UDIV, VT, Expand);
     setOperationAction(ISD::SDIV, VT, Expand);
     setOperationAction(ISD::UREM, VT, Expand);
     setOperationAction(ISD::SREM, VT, Expand);
     setOperationAction(ISD::CTPOP, VT, Expand);
 

llvm/lib/Target/ARM/ARMInstrMVE.td

let Predicates = [HasMVEInt] in {
   foreach instr = [MVE_VQADDu8, MVE_VQADDu16, MVE_VQADDu32] in
     foreach VT = [instr.VT] in
       def : Pat<(VT (uaddsat (VT MQPR:$Qm), (VT MQPR:$Qn))),
                 (VT (instr (VT MQPR:$Qm), (VT MQPR:$Qn)))>;
   foreach instr = [MVE_VQADDs8, MVE_VQADDs16, MVE_VQADDs32] in
     foreach VT = [instr.VT] in
       def : Pat<(VT (saddsat (VT MQPR:$Qm), (VT MQPR:$Qn))),
                 (VT (instr (VT MQPR:$Qm), (VT MQPR:$Qn)))>;
+  foreach instr = [MVE_VQSUBu8, MVE_VQSUBu16, MVE_VQSUBu32] in
+    foreach VT = [instr.VT] in
+      def : Pat<(VT (usubsat (VT MQPR:$Qm), (VT MQPR:$Qn))),
+                (VT (instr (VT MQPR:$Qm), (VT MQPR:$Qn)))>;
+  foreach instr = [MVE_VQSUBs8, MVE_VQSUBs16, MVE_VQSUBs32] in
+    foreach VT = [instr.VT] in
+      def : Pat<(VT (ssubsat (VT MQPR:$Qm), (VT MQPR:$Qn))),
+                (VT (instr (VT MQPR:$Qm), (VT MQPR:$Qn)))>;
 }
 
 
 class MVE_VABD_int<string suffix, bit U, bits<2> size, list<dag> pattern=[]>
   : MVE_int<"vabd", suffix, size, pattern> {
 
   let Inst{28} = U;
   let Inst{25-23} = 0b110;

llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll

entry:
   %0 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
   ret <2 x i64> %0
 }
 
 
 define arm_aapcs_vfpcc <16 x i8> @ssub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
 ; CHECK-LABEL: ssub_int8_t:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    .vsave {d8, d9}
-; CHECK-NEXT:    vpush {d8, d9}
-; CHECK-NEXT:    vsub.i8 q2, q0, q1
-; CHECK-NEXT:    vmov.i8 q3, #0x80
-; CHECK-NEXT:    vcmp.s8 lt, q2, zr
-; CHECK-NEXT:    vmov.i8 q4, #0x7f
-; CHECK-NEXT:    vpsel q3, q4, q3
-; CHECK-NEXT:    vcmp.s8 gt, q0, q2
-; CHECK-NEXT:    vmrs r0, p0
-; CHECK-NEXT:    vcmp.s8 gt, q1, zr
-; CHECK-NEXT:    vmrs r1, p0
-; CHECK-NEXT:    eors r0, r1
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpsel q0, q3, q2
-; CHECK-NEXT:    vpop {d8, d9}
+; CHECK-NEXT:    vqsub.s8 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
   ret <16 x i8> %0
 }
 
 define arm_aapcs_vfpcc <8 x i16> @ssub_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
 ; CHECK-LABEL: ssub_int16_t:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    .vsave {d8, d9}
-; CHECK-NEXT:    vpush {d8, d9}
-; CHECK-NEXT:    vsub.i16 q2, q0, q1
-; CHECK-NEXT:    vmov.i16 q3, #0x8000
-; CHECK-NEXT:    vcmp.s16 lt, q2, zr
-; CHECK-NEXT:    vmvn.i16 q4, #0x8000
-; CHECK-NEXT:    vpsel q3, q4, q3
-; CHECK-NEXT:    vcmp.s16 gt, q0, q2
-; CHECK-NEXT:    vmrs r0, p0
-; CHECK-NEXT:    vcmp.s16 gt, q1, zr
-; CHECK-NEXT:    vmrs r1, p0
-; CHECK-NEXT:    eors r0, r1
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpsel q0, q3, q2
-; CHECK-NEXT:    vpop {d8, d9}
+; CHECK-NEXT:    vqsub.s16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
   ret <8 x i16> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @ssub_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
 ; CHECK-LABEL: ssub_int32_t:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    .vsave {d8, d9}
-; CHECK-NEXT:    vpush {d8, d9}
-; CHECK-NEXT:    vsub.i32 q2, q0, q1
-; CHECK-NEXT:    vmov.i32 q3, #0x80000000
-; CHECK-NEXT:    vcmp.s32 lt, q2, zr
-; CHECK-NEXT:    vmvn.i32 q4, #0x80000000
-; CHECK-NEXT:    vpsel q3, q4, q3
-; CHECK-NEXT:    vcmp.s32 gt, q0, q2
-; CHECK-NEXT:    vmrs r0, p0
-; CHECK-NEXT:    vcmp.s32 gt, q1, zr
-; CHECK-NEXT:    vmrs r1, p0
-; CHECK-NEXT:    eors r0, r1
-; CHECK-NEXT:    vmsr p0, r0
-; CHECK-NEXT:    vpsel q0, q3, q2
-; CHECK-NEXT:    vpop {d8, d9}
+; CHECK-NEXT:    vqsub.s32 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
   ret <4 x i32> %0
 }
 
 define arm_aapcs_vfpcc <2 x i64> @ssub_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
 ; CHECK-LABEL: ssub_int64_t:

 entry:
   %0 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
   ret <2 x i64> %0
 }
 
 define arm_aapcs_vfpcc <16 x i8> @usub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
 ; CHECK-LABEL: usub_int8_t:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmax.u8 q0, q0, q1
-; CHECK-NEXT:    vsub.i8 q0, q0, q1
+; CHECK-NEXT:    vqsub.u8 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
   ret <16 x i8> %0
 }
 
 define arm_aapcs_vfpcc <8 x i16> @usub_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
 ; CHECK-LABEL: usub_int16_t:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmax.u16 q0, q0, q1
-; CHECK-NEXT:    vsub.i16 q0, q0, q1
+; CHECK-NEXT:    vqsub.u16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
   ret <8 x i16> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @usub_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
 ; CHECK-LABEL: usub_int32_t:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmax.u32 q0, q0, q1
-; CHECK-NEXT:    vsub.i32 q0, q0, q1
+; CHECK-NEXT:    vqsub.u32 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
   ret <4 x i32> %0
 }
 
 define arm_aapcs_vfpcc <2 x i64> @usub_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
 ; CHECK-LABEL: usub_int64_t: