[RISCV] Materialization of 64-bit mask immediate

[luismarques]

Summary

This approach of materializing 64-bit masks using ADDI+SRLI was suggested a while ago by @lewis-revill [1] but never implemented.

• The ShiftAmount is tweaked;
• In the code generated for the expansion of fcopysign(a, -b) an addi was replaced by a srli. This could be slightly slower (e.g. picorv32) but it's probably not very concerning. Even the E31 has single-cycle shifts, and these softfloat computations are probably not important workloads for microcontrollers.

[1] https://reviews.llvm.org/D52961?id=169524#inline-470319

[asb]

Plus our dev meeting coding lab last year stepped through a similar optimisation, so we really should land it.

Can you please add some more targeted imm.ll tests and to rv32i-aliases-valid.s and rv64i-aliases-valid.s.

Although it could be done in a follow-up commit, I'd be supportive of handling the left-shift case in this commit as well.

[luismarques]

This is superseded by D79492, which subsumes this special case with more general optimizations.

llvm/lib/Target/RISCV/Utils/RISCVMatInt.cpp

if (Lo12 || Hi20 == 0) {
       unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
       Res.push_back(Inst(AddiOpc, Lo12));
     }
     return;
   }
 
   assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target");
 
+  // If the immediate is -1 shifted right emit the sequence ADDI+SRLI.
+  if (isMask_64((uint64_t)Val)) {
+    Res.push_back(Inst(RISCV::ADDI, -1));
+
+    int ShiftAmount = 64 - findLastSet((uint64_t)Val) - 1;
+    Res.push_back(Inst(RISCV::SRLI, ShiftAmount));
+
+    return;
+  }
+
   // In the worst case, for a full 64-bit constant, a sequence of 8 instructions
   // (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emmitted. Note
   // that the first two instructions (LUI+ADDIW) can contribute up to 32 bits
   // while the following ADDI instructions contribute up to 12 bits each.
   //
   // On the first glance, implementing this seems to be possible by simply
   // emitting the most significant 32 bits (LUI+ADDIW) followed by as many left
   // shift (SLLI) and immediate additions (ADDI) as needed. However, due to the

llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll

 ; RV32IFD-NEXT:    lui a2, 524288
 ; RV32IFD-NEXT:    addi a2, a2, -1
 ; RV32IFD-NEXT:    and a1, a1, a2
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64I-LABEL: fabs:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, -1
-; RV64I-NEXT:    slli a1, a1, 63
-; RV64I-NEXT:    addi a1, a1, -1
+; RV64I-NEXT:    srli a1, a1, 1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fabs:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addi a1, zero, -1
-; RV64IFD-NEXT:    slli a1, a1, 63
-; RV64IFD-NEXT:    addi a1, a1, -1
+; RV64IFD-NEXT:    srli a1, a1, 1
 ; RV64IFD-NEXT:    and a0, a0, a1
 ; RV64IFD-NEXT:    ret
   %1 = call double @llvm.fabs.f64(double %a)
   ret double %1
 }
 
 declare double @llvm.copysign.f64(double, double)
 

 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64I-LABEL: fcopysign_fneg:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a1, a1
 ; RV64I-NEXT:    addi a2, zero, -1
-; RV64I-NEXT:    slli a2, a2, 63
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    addi a2, a2, -1
+; RV64I-NEXT:    slli a3, a2, 63
+; RV64I-NEXT:    and a1, a1, a3
+; RV64I-NEXT:    srli a2, a2, 1
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcopysign_fneg:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addi a2, zero, -1
 ; RV64IFD-NEXT:    slli a2, a2, 63

llvm/test/CodeGen/RISCV/double-intrinsics.ll

 ; RV32IFD-NEXT:    lui a2, 524288
 ; RV32IFD-NEXT:    addi a2, a2, -1
 ; RV32IFD-NEXT:    and a1, a1, a2
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fabs_f64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addi a1, zero, -1
-; RV64IFD-NEXT:    slli a1, a1, 63
-; RV64IFD-NEXT:    addi a1, a1, -1
+; RV64IFD-NEXT:    srli a1, a1, 1
 ; RV64IFD-NEXT:    and a0, a0, a1
 ; RV64IFD-NEXT:    ret
   %1 = call double @llvm.fabs.f64(double %a)
   ret double %1
 }
 
 declare double @llvm.minnum.f64(double, double)
 

llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll

 ; RV64F-LABEL: bitcast_double_and:
 ; RV64F:       # %bb.0:
 ; RV64F-NEXT:    addi sp, sp, -16
 ; RV64F-NEXT:    sd ra, 8(sp)
 ; RV64F-NEXT:    sd s0, 0(sp)
 ; RV64F-NEXT:    mv s0, a0
 ; RV64F-NEXT:    call __adddf3
 ; RV64F-NEXT:    addi a1, zero, -1
-; RV64F-NEXT:    slli a1, a1, 63
-; RV64F-NEXT:    addi a1, a1, -1
+; RV64F-NEXT:    srli a1, a1, 1
 ; RV64F-NEXT:    and a1, a0, a1
 ; RV64F-NEXT:    mv a0, s0
 ; RV64F-NEXT:    call __adddf3
 ; RV64F-NEXT:    ld s0, 0(sp)
 ; RV64F-NEXT:    ld ra, 8(sp)
 ; RV64F-NEXT:    addi sp, sp, 16
 ; RV64F-NEXT:    ret
 ;

llvm/test/CodeGen/RISCV/imm.ll

 ; RV32I-LABEL: imm64_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a0, zero, -1
 ; RV32I-NEXT:    mv a1, zero
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm64_2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi a0, zero, 1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    addi a0, zero, -1
+; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
   ret i64 4294967295
 }
 
 define i64 @imm64_3() nounwind {
 ; RV32I-LABEL: imm64_3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 1