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[RISCV] Materialization of 64-bit mask immediate
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Authored by luismarques on Sep 25 2019, 3:52 PM.

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asb
lenary
Summary

This approach of materializing 64-bit masks using ADDI+SRLI was suggested a while ago by @lewis-revill [1] but never implemented.

  • The ShiftAmount is tweaked;
  • In the code generated for the expansion of fcopysign(a, -b) an addi was replaced by a srli. This could be slightly slower (e.g. picorv32) but it's probably not very concerning. Even the E31 has single-cycle shifts, and these softfloat computations are probably not important workloads for microcontrollers.

[1] https://reviews.llvm.org/D52961?id=169524#inline-470319

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luismarques created this revision.Sep 25 2019, 3:52 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 25 2019, 3:52 PM
asb added a comment.EditedSep 26 2019, 4:45 AM

Plus our dev meeting coding lab last year stepped through a similar optimisation, so we really should land it.

Can you please add some more targeted imm.ll tests and to rv32i-aliases-valid.s and rv64i-aliases-valid.s.

Although it could be done in a follow-up commit, I'd be supportive of handling the left-shift case in this commit as well.

luismarques abandoned this revision.May 6 2020, 12:21 PM

This is superseded by D79492, which subsumes this special case with more general optimizations.