This is an archive of the discontinued LLVM Phabricator instance.

Differential D67708

AMDGPU/GlobalISel: Fix RegBankSelect G_SMULH/G_UMULH pre-gfx9
ClosedPublic

Authored by arsenm on Sep 18 2019, 7:06 AM.

Details

Reviewers
hliao
tstellar
nhaehnle
kerbowa
Summary

The scalar versions were only introduced in gfx9.

Diff Detail

Event Timeline

arsenm created this revision.Sep 18 2019, 7:06 AM
Herald added subscribers: Petar.Avramovic, t-tye, tpr and 6 others. · View Herald TranscriptSep 18 2019, 7:06 AM
hliao accepted this revision.Sep 18 2019, 7:47 AM

LGTM

This revision is now accepted and ready to land.Sep 18 2019, 7:47 AM
arsenm closed this revision.Sep 18 2019, 6:40 PM

r372286

Revision Contents

PathSize
lib/
Target/
AMDGPU/
10 lines
4 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
62 lines
62 lines

Diff 220660

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 1,742 Lines • ▼ Show 20 Lines if (Size == 64) {
OpdsMapping[2] = AMDGPU::getValueMapping(Bank2, Size); OpdsMapping[2] = AMDGPU::getValueMapping(Bank2, Size);
} }
break; break;
} }
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
} }
case AMDGPU::G_UMULH:
case AMDGPU::G_SMULH: {
if (MF.getSubtarget<GCNSubtarget>().hasScalarMulHiInsts() &&
isSALUMapping(MI))
return getDefaultMappingSOP(MI);
return getDefaultMappingVOP(MI);
}
case AMDGPU::G_GEP: case AMDGPU::G_GEP:
case AMDGPU::G_ADD: case AMDGPU::G_ADD:
case AMDGPU::G_SUB: case AMDGPU::G_SUB:
case AMDGPU::G_MUL: case AMDGPU::G_MUL:
case AMDGPU::G_SHL: case AMDGPU::G_SHL:
case AMDGPU::G_LSHR: case AMDGPU::G_LSHR:
case AMDGPU::G_ASHR: case AMDGPU::G_ASHR:
case AMDGPU::G_UADDO: case AMDGPU::G_UADDO:
case AMDGPU::G_SADDO: case AMDGPU::G_SADDO:
case AMDGPU::G_USUBO: case AMDGPU::G_USUBO:
case AMDGPU::G_SSUBO: case AMDGPU::G_SSUBO:
case AMDGPU::G_UADDE: case AMDGPU::G_UADDE:
case AMDGPU::G_SADDE: case AMDGPU::G_SADDE:
case AMDGPU::G_USUBE: case AMDGPU::G_USUBE:
case AMDGPU::G_SSUBE: case AMDGPU::G_SSUBE:
case AMDGPU::G_UMULH:
case AMDGPU::G_SMULH:
case AMDGPU::G_SMIN: case AMDGPU::G_SMIN:
case AMDGPU::G_SMAX: case AMDGPU::G_SMAX:
case AMDGPU::G_UMIN: case AMDGPU::G_UMIN:
case AMDGPU::G_UMAX: case AMDGPU::G_UMAX:
if (isSALUMapping(MI)) if (isSALUMapping(MI))
return getDefaultMappingSOP(MI); return getDefaultMappingSOP(MI);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
▲ Show 20 Lines • Show All 601 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPUSubtarget.h

Show First 20 Lines • Show All 549 Lines • ▼ Show 20 Linespublic:
bool hasSwap() const { bool hasSwap() const {
return GFX9Insts; return GFX9Insts;
} }
bool hasScalarPackInsts() const { bool hasScalarPackInsts() const {
return GFX9Insts; return GFX9Insts;
} }
bool hasScalarMulHiInsts() const {
return GFX9Insts;
}
TrapHandlerAbi getTrapHandlerAbi() const { TrapHandlerAbi getTrapHandlerAbi() const {
return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone; return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
} }
/// True if the offset field of DS instructions works as expected. On SI, the /// True if the offset field of DS instructions works as expected. On SI, the
/// offset uses a 16-bit adder and does not always wrap properly. /// offset uses a 16-bit adder and does not always wrap properly.
bool hasUsableDSOffset() const { bool hasUsableDSOffset() const {
return getGeneration() >= SEA_ISLANDS; return getGeneration() >= SEA_ISLANDS;
▲ Show 20 Lines • Show All 782 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
--- ---
name: smulh_s32_ss name: smulh_s32_ss
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: smulh_s32_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GFX6-LABEL: name: smulh_s32_ss
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GFX6: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[SMULH:%[0-9]+]]:sgpr(s32) = G_SMULH [[COPY]], [[COPY1]] ; GFX6: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GFX6: [[SMULH:%[0-9]+]]:vgpr(s32) = G_SMULH [[COPY]], [[COPY2]]
; GFX9-LABEL: name: smulh_s32_ss
; GFX9: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GFX9: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GFX9: [[SMULH:%[0-9]+]]:sgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s32) = G_SMULH %0, %1 %2:_(s32) = G_SMULH %0, %1
... ...
--- ---
name: smulh_s32_sv name: smulh_s32_sv
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; CHECK-LABEL: name: smulh_s32_sv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GFX6-LABEL: name: smulh_s32_sv
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[SMULH:%[0-9]+]]:vgpr(s32) = G_SMULH [[COPY]], [[COPY1]] ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX6: [[SMULH:%[0-9]+]]:vgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
; GFX9-LABEL: name: smulh_s32_sv
; GFX9: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX9: [[SMULH:%[0-9]+]]:vgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr0
%2:_(s32) = G_SMULH %0, %1 %2:_(s32) = G_SMULH %0, %1
... ...
--- ---
name: smulh_s32_vs name: smulh_s32_vs
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; CHECK-LABEL: name: smulh_s32_vs
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; GFX6-LABEL: name: smulh_s32_vs
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) ; GFX6: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[SMULH:%[0-9]+]]:vgpr(s32) = G_SMULH [[COPY]], [[COPY2]] ; GFX6: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GFX6: [[SMULH:%[0-9]+]]:vgpr(s32) = G_SMULH [[COPY]], [[COPY2]]
; GFX9-LABEL: name: smulh_s32_vs
; GFX9: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GFX9: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GFX9: [[SMULH:%[0-9]+]]:vgpr(s32) = G_SMULH [[COPY]], [[COPY2]]
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr0
%2:_(s32) = G_SMULH %0, %1 %2:_(s32) = G_SMULH %0, %1
... ...
--- ---
name: smulh_s32_vv name: smulh_s32_vv
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: smulh_s32_vv
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; GFX6-LABEL: name: smulh_s32_vv
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; GFX6: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[SMULH:%[0-9]+]]:vgpr(s32) = G_SMULH [[COPY]], [[COPY1]] ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GFX6: [[SMULH:%[0-9]+]]:vgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
; GFX9-LABEL: name: smulh_s32_vv
; GFX9: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GFX9: [[SMULH:%[0-9]+]]:vgpr(s32) = G_SMULH [[COPY]], [[COPY1]]
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s32) = G_SMULH %0, %1 %2:_(s32) = G_SMULH %0, %1
... ...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# XUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
# XUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
--- ---
name: umulh_s32_ss name: umulh_s32_ss
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: umulh_s32_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GFX6-LABEL: name: umulh_s32_ss
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GFX6: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[UMULH:%[0-9]+]]:sgpr(s32) = G_UMULH [[COPY]], [[COPY1]] ; GFX6: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GFX6: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[COPY]], [[COPY2]]
; GFX9-LABEL: name: umulh_s32_ss
; GFX9: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GFX9: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GFX9: [[UMULH:%[0-9]+]]:sgpr(s32) = G_UMULH [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s32) = G_UMULH %0, %1 %2:_(s32) = G_UMULH %0, %1
... ...
--- ---
name: umulh_s32_sv name: umulh_s32_sv
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; CHECK-LABEL: name: umulh_s32_sv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GFX6-LABEL: name: umulh_s32_sv
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[COPY]], [[COPY1]] ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX6: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[COPY]], [[COPY1]]
; GFX9-LABEL: name: umulh_s32_sv
; GFX9: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX9: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr0
%2:_(s32) = G_UMULH %0, %1 %2:_(s32) = G_UMULH %0, %1
... ...
--- ---
name: umulh_s32_vs name: umulh_s32_vs
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; CHECK-LABEL: name: umulh_s32_vs
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; GFX6-LABEL: name: umulh_s32_vs
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) ; GFX6: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[COPY]], [[COPY2]] ; GFX6: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GFX6: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[COPY]], [[COPY2]]
; GFX9-LABEL: name: umulh_s32_vs
; GFX9: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GFX9: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GFX9: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[COPY]], [[COPY2]]
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr0
%2:_(s32) = G_UMULH %0, %1 %2:_(s32) = G_UMULH %0, %1
... ...
--- ---
name: umulh_s32_vv name: umulh_s32_vv
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: umulh_s32_vv
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; GFX6-LABEL: name: umulh_s32_vv
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; GFX6: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[COPY]], [[COPY1]] ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GFX6: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[COPY]], [[COPY1]]
; GFX9-LABEL: name: umulh_s32_vv
; GFX9: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GFX9: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[COPY]], [[COPY1]]
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s32) = G_UMULH %0, %1 %2:_(s32) = G_UMULH %0, %1
... ...