[PowerPC][NFC] Update test assertions using update_llc_test_checks.py

[lkail]

Summary

This patch is made due to https://reviews.llvm.org/rL371289 where typo fixes failed.

[Higuoxing]

llvm/test/CodeGen/PowerPC/store-combine.ll

238 ↗

(On Diff #219238)

Thanks, I'm not familiar with PowerPC instructions. What's your purpose by removing these two check points? It's useless or you will fix the typo later?

[lkail]

llvm/test/CodeGen/PowerPC/store-combine.ll

238 ↗

(On Diff #219238)

This test has been declared NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py. Re-running update_llc_test_checks.py, seems these two instructions should not appear. I've also added original author as a reviewer to see if some CHECK-NOT directives shall keep or not.

[Higuoxing]

llvm/test/CodeGen/PowerPC/store-combine.ll

238 ↗

(On Diff #219238)

Ok, I got it. Thanks a lot.

[nemanjai]

LGTM.
If we are producing the checks with the script, we should refrain from manually changing them as any future updates to the test will make it very difficult to determine whether the change is intended or not.

[nemanjai]

Forgot to select Accept.

llvm/trunk/test/CodeGen/PowerPC/store-combine.ll

 define void @store_i32_by_i8(i32 signext %m, i8* %p) {
 ; CHECK-PPC64LE-LABEL: store_i32_by_i8:
 ; CHECK-PPC64LE:       # %bb.0: # %entry
 ; CHECK-PPC64LE-NEXT:    stw 3, 0(4)
 ; CHECK-PPC64LE-NEXT:    blr
 ;
 ; CHECK-PPC64-LABEL: store_i32_by_i8:
 ; CHECK-PPC64:       # %bb.0: # %entry
-; CHECK-PPC64-NEXT:    stwbrx 3, 0, 4 
+; CHECK-PPC64-NEXT:    stwbrx 3, 0, 4
 ; CHECK-PPC64-NEXT:    blr
 entry:
   %conv = trunc i32 %m to i8
   store i8 %conv, i8* %p, align 1
   %0 = lshr i32 %m, 8
   %conv3 = trunc i32 %0 to i8
   %arrayidx4 = getelementptr inbounds i8, i8* %p, i64 1
   store i8 %conv3, i8* %arrayidx4, align 1

 ; p[4] = (m >> 24) & 0xFF;
 ; p[3] = (m >> 32) & 0xFF;
 ; p[2] = (m >> 40) & 0xFF;
 ; p[1] = (m >> 48) & 0xFF;
 ; p[0] = (m >> 56) & 0xFF;
 define void @store_i64_by_i8_bswap_uses(i32 signext %t, i8* %p) {
 ; CHECK-PPC64LE-LABEL: store_i64_by_i8_bswap_uses:
 ; CHECK-PPC64LE:       # %bb.0: # %entry
-; CHECK-PPC64LE-NEXT:    slwi [[REG:[0-9]+]], 3, 3
-; CHECK-PPC64LE-NEXT:    subf [[REG1:[0-9]+]], 3, [[REG]] 
-; CHECK-PPC64LE-NEXT:    extsw [[REG2:[0-9]+]], [[REG1]]
-; CHECK-PPC64LE-NEXT:    stdbrx [[REG2]], 0, 4
+; CHECK-PPC64LE-NEXT:    slwi 5, 3, 3
+; CHECK-PPC64LE-NEXT:    subf 3, 3, 5
+; CHECK-PPC64LE-NEXT:    extsw 3, 3
+; CHECK-PPC64LE-NEXT:    stdbrx 3, 0, 4
 ; CHECK-PPC64LE-NEXT:    blr
 ;
 ; CHECK-PPC64-LABEL: store_i64_by_i8_bswap_uses:
 ; CHECK-PPC64:       # %bb.0: # %entry
-; CHECK-PPC64-NEXT:    slwi [[REG:[0-9]+]], 3, 3
-; CHECK-PPC64-NEXT:    subf [[REG1:[0-9]+]], 3, [[REG]]
-; CHECK-PPC64-NEXT:    extsw [[REG2:[0-9]+]], [[REG1]]
-; CHECK-PPC64-NEXT:    stdx [[REG2]], 0, 4
+; CHECK-PPC64-NEXT:    slwi 5, 3, 3
+; CHECK-PPC64-NEXT:    subf 3, 3, 5
+; CHECK-PPC64-NEXT:    extsw 3, 3
+; CHECK-PPC64-NEXT:    stdx 3, 0, 4
 ; CHECK-PPC64-NEXT:    blr
 entry:
   %mul = mul nsw i32 %t, 7
   %conv = sext i32 %mul to i64
   %conv1 = trunc i32 %mul to i8
   %arrayidx = getelementptr inbounds i8, i8* %p, i64 7
   store i8 %conv1, i8* %arrayidx, align 1
   %0 = lshr i64 %conv, 8
entry:
   %shr22 = ashr i64 %conv, 48
   %conv24 = trunc i64 %shr22 to i8
   %arrayidx25 = getelementptr inbounds i8, i8* %p, i64 1
   store i8 %conv24, i8* %arrayidx25, align 1
   %shr26 = ashr i64 %conv, 56
   %conv28 = trunc i64 %shr26 to i8
   store i8 %conv28, i8* %p, align 1
   ret void
-; CEHCK-PPC64LE: stdbrx [[REG2]], 0, 4
-; CEHCK-PPC64: stdx [[REG2]], 0, 4
 }
 
 ; One of the stores is volatile
 ; i8 *p;
 ; p0 = volatile *p;
 ; p[3] = (m >> 0) & 0xFF;
 ; p[2] = (m >> 8) & 0xFF;
 ; p[1] = (m >> 16) & 0xFF;
 ; *p0 = (m >> 24) & 0xFF;
 define void @store_i32_by_i8_bswap_volatile(i32 signext %m, i8* %p) {
 ; CHECK-PPC64LE-LABEL: store_i32_by_i8_bswap_volatile:
 ; CHECK-PPC64LE:       # %bb.0: # %entry
-; CHECK-PPC64LE-NOT:   stwbrx 
+; CHECK-PPC64LE-NEXT:    li 5, 2
+; CHECK-PPC64LE-NEXT:    sthbrx 3, 4, 5
+; CHECK-PPC64LE-NEXT:    srwi 5, 3, 16
+; CHECK-PPC64LE-NEXT:    srwi 3, 3, 24
+; CHECK-PPC64LE-NEXT:    stb 5, 1(4)
+; CHECK-PPC64LE-NEXT:    stb 3, 0(4)
+; CHECK-PPC64LE-NEXT:    blr
 ;
 ; CHECK-PPC64-LABEL: store_i32_by_i8_bswap_volatile:
 ; CHECK-PPC64:       # %bb.0: # %entry
-; CHECK-PPC64-NOT:   stw 
+; CHECK-PPC64-NEXT:    sth 3, 2(4)
+; CHECK-PPC64-NEXT:    srwi 5, 3, 16
+; CHECK-PPC64-NEXT:    srwi 3, 3, 24
+; CHECK-PPC64-NEXT:    stb 5, 1(4)
+; CHECK-PPC64-NEXT:    stb 3, 0(4)
+; CHECK-PPC64-NEXT:    blr
 entry:
   %conv = trunc i32 %m to i8
   %arrayidx = getelementptr inbounds i8, i8* %p, i64 3
   store i8 %conv, i8* %arrayidx, align 1
   %0 = lshr i32 %m, 8
   %conv3 = trunc i32 %0 to i8
   %arrayidx4 = getelementptr inbounds i8, i8* %p, i64 2
   store i8 %conv3, i8* %arrayidx4, align 1

 ; p[3] = (m >> 0) & 0xFF;
 ; p[2] = (m >> 8) & 0xFF;
 ; *q = 3;
 ; p[1] = (m >> 16) & 0xFF;
 ; p[0] = (m >> 24) & 0xFF;
 define void @store_i32_by_i8_bswap_store_in_between(i32 signext %m, i8* %p, i8* %q) {
 ; CHECK-PPC64LE-LABEL: store_i32_by_i8_bswap_store_in_between:
 ; CHECK-PPC64LE:       # %bb.0: # %entry
-; CHECK-PPC64LE-NOT:   stwbrx 
+; CHECK-PPC64LE-NEXT:    li 6, 2
+; CHECK-PPC64LE-NEXT:    sthbrx 3, 4, 6
+; CHECK-PPC64LE-NEXT:    li 6, 3
+; CHECK-PPC64LE-NEXT:    stb 6, 0(5)
+; CHECK-PPC64LE-NEXT:    srwi 5, 3, 16
+; CHECK-PPC64LE-NEXT:    srwi 3, 3, 24
+; CHECK-PPC64LE-NEXT:    stb 5, 1(4)
+; CHECK-PPC64LE-NEXT:    stb 3, 0(4)
+; CHECK-PPC64LE-NEXT:    blr
 ;
 ; CHECK-PPC64-LABEL: store_i32_by_i8_bswap_store_in_between:
 ; CHECK-PPC64:       # %bb.0: # %entry
-; CHECK-PPC64-NOT:   stw 
+; CHECK-PPC64-NEXT:    li 6, 3
+; CHECK-PPC64-NEXT:    sth 3, 2(4)
+; CHECK-PPC64-NEXT:    stb 6, 0(5)
+; CHECK-PPC64-NEXT:    srwi 5, 3, 16
+; CHECK-PPC64-NEXT:    srwi 3, 3, 24
+; CHECK-PPC64-NEXT:    stb 5, 1(4)
+; CHECK-PPC64-NEXT:    stb 3, 0(4)
+; CHECK-PPC64-NEXT:    blr
 entry:
   %conv = trunc i32 %m to i8
   %arrayidx = getelementptr inbounds i8, i8* %p, i64 3
   store i8 %conv, i8* %arrayidx, align 1
   %0 = lshr i32 %m, 8
   %conv3 = trunc i32 %0 to i8
   %arrayidx4 = getelementptr inbounds i8, i8* %p, i64 2
   store i8 %conv3, i8* %arrayidx4, align 1
   store i8 3, i8* %q, align 1
   %1 = lshr i32 %m, 16
   %conv7 = trunc i32 %1 to i8
   %arrayidx8 = getelementptr inbounds i8, i8* %p, i64 1
   store i8 %conv7, i8* %arrayidx8, align 1
   %2 = lshr i32 %m, 24
   %conv11 = trunc i32 %2 to i8
   store i8 %conv11, i8* %p, align 1
   ret void
 }
 
 define void @store_i32_by_i8_bswap_unrelated_store(i32 signext %m, i8* %p, i8* %q) {
 ; CHECK-PPC64LE-LABEL: store_i32_by_i8_bswap_unrelated_store:
 ; CHECK-PPC64LE:       # %bb.0: # %entry
-; CHECK-PPC64LE-NOT:   stwbrx 
+; CHECK-PPC64LE-NEXT:    srwi 6, 3, 8
+; CHECK-PPC64LE-NEXT:    stb 3, 3(4)
+; CHECK-PPC64LE-NEXT:    stb 6, 2(5)
+; CHECK-PPC64LE-NEXT:    srwi 5, 3, 16
+; CHECK-PPC64LE-NEXT:    srwi 3, 3, 24
+; CHECK-PPC64LE-NEXT:    stb 5, 1(4)
+; CHECK-PPC64LE-NEXT:    stb 3, 0(4)
+; CHECK-PPC64LE-NEXT:    blr
 ;
 ; CHECK-PPC64-LABEL: store_i32_by_i8_bswap_unrelated_store:
 ; CHECK-PPC64:       # %bb.0: # %entry
-; CHECK-PPC64-NOT:   stw 
+; CHECK-PPC64-NEXT:    srwi 6, 3, 8
+; CHECK-PPC64-NEXT:    stb 3, 3(4)
+; CHECK-PPC64-NEXT:    stb 6, 2(5)
+; CHECK-PPC64-NEXT:    srwi 5, 3, 16
+; CHECK-PPC64-NEXT:    srwi 3, 3, 24
+; CHECK-PPC64-NEXT:    stb 5, 1(4)
+; CHECK-PPC64-NEXT:    stb 3, 0(4)
+; CHECK-PPC64-NEXT:    blr
 entry:
   %conv = trunc i32 %m to i8
   %arrayidx = getelementptr inbounds i8, i8* %p, i64 3
   store i8 %conv, i8* %arrayidx, align 1
   %0 = lshr i32 %m, 8
   %conv3 = trunc i32 %0 to i8
   %arrayidx4 = getelementptr inbounds i8, i8* %q, i64 2
   store i8 %conv3, i8* %arrayidx4, align 1

 ; i8* p;
 ; p[3] = (m >> 8) & 0xFF;
 ; p[4] = (m >> 0) & 0xFF;
 ; p[2] = (m >> 16) & 0xFF;
 ; p[1] = (m >> 24) & 0xFF;
 define void @store_i32_by_i8_bswap_nonzero_offset(i32 signext %m, i8* %p) {
 ; CHECK-PPC64LE-LABEL: store_i32_by_i8_bswap_nonzero_offset:
 ; CHECK-PPC64LE:       # %bb.0: # %entry
-; CHECK-PPC64LE-NEXT:    addi [[REG1:[0-9]+]], 4, 1
-; CHECK-PPC64LE-NEXT:    stwbrx 3, 0, [[REG1]] 
+; CHECK-PPC64LE-NEXT:    addi 4, 4, 1
+; CHECK-PPC64LE-NEXT:    stwbrx 3, 0, 4
 ; CHECK-PPC64LE-NEXT:    blr
 ;
 ; CHECK-PPC64-LABEL: store_i32_by_i8_bswap_nonzero_offset:
 ; CHECK-PPC64:       # %bb.0: # %entry
 ; CHECK-PPC64-NEXT:    stw 3, 1(4)
 ; CHECK-PPC64-NEXT:    blr
 entry:
   %0 = lshr i32 %m, 8

 define void @store_i32_by_i8_neg_offset(i32 signext %m, i8* %p) {
 ; CHECK-PPC64LE-LABEL: store_i32_by_i8_neg_offset:
 ; CHECK-PPC64LE:       # %bb.0: # %entry
 ; CHECK-PPC64LE-NEXT:    stw 3, -4(4)
 ; CHECK-PPC64LE-NEXT:    blr
 ;
 ; CHECK-PPC64-LABEL: store_i32_by_i8_neg_offset:
 ; CHECK-PPC64:       # %bb.0: # %entry
-; CHECK-PPC64-NEXT:    addi [[REG1:[0-9]+]], 4, -4
-; CHECK-PPC64-NEXT:    stwbrx 3, 0, [[REG1]] 
+; CHECK-PPC64-NEXT:    addi 4, 4, -4
+; CHECK-PPC64-NEXT:    stwbrx 3, 0, 4
 ; CHECK-PPC64-NEXT:    blr
 entry:
   %0 = lshr i32 %m, 8
   %conv = trunc i32 %0 to i8
   %arrayidx = getelementptr inbounds i8, i8* %p, i64 -3
   store i8 %conv, i8* %arrayidx, align 1
   %conv3 = trunc i32 %m to i8
   %arrayidx4 = getelementptr inbounds i8, i8* %p, i64 -4

 ; i8* p;
 ; p[-3] = (m >> 16) & 0xFF;
 ; p[-4] = (m >> 24) & 0xFF;
 ; p[-2] = (m >> 8) & 0xFF;
 ; p[-1] = (m >> 0) & 0xFF;
 define void @store_i32_by_i8_bswap_neg_offset(i32 signext %m, i8* %p) {
 ; CHECK-PPC64LE-LABEL: store_i32_by_i8_bswap_neg_offset:
 ; CHECK-PPC64LE:       # %bb.0: # %entry
-; CHECK-PPC64LE-NEXT:    addi [[REG1:[0-9]+]], 4, -4
-; CHECK-PPC64LE-NEXT:    stwbrx 3, 0, [[REG1]] 
+; CHECK-PPC64LE-NEXT:    addi 4, 4, -4
+; CHECK-PPC64LE-NEXT:    stwbrx 3, 0, 4
 ; CHECK-PPC64LE-NEXT:    blr
 ;
 ; CHECK-PPC64-LABEL: store_i32_by_i8_bswap_neg_offset:
 ; CHECK-PPC64:       # %bb.0: # %entry
 ; CHECK-PPC64-NEXT:    stw 3, -4(4)
 ; CHECK-PPC64-NEXT:    blr
 entry:
   %0 = lshr i32 %m, 16

 ; i8* p;
 ; p[i-3] = (m >> 16) & 0xFF;
 ; p[i-4] = (m >> 24) & 0xFF;
 ; p[i-2] = (m >> 8) & 0xFF;
 ; p[i-1] = (m >> 0) & 0xFF;
 define void @store_i32_by_i8_bswap_base_index_offset(i32 %m, i32 %i, i8* %p) {
 ; CHECK-PPC64LE-LABEL: store_i32_by_i8_bswap_base_index_offset:
 ; CHECK-PPC64LE:       # %bb.0: # %entry
-; CHECK-PPC64LE-NEXT:    extsw [[REG1:[0-9]+]], 4
-; CHECK-PPC64LE-NEXT:    add [[REG2:[0-9]+]], 5, [[REG1]] 
-; CHECK-PPC64LE-NEXT:    addi [[REG3:[0-9]+]], [[REG2]], -4
-; CHECK-PPC64LE-NEXT:    stwbrx 3, 0, [[REG3]] 
+; CHECK-PPC64LE-NEXT:    extsw 4, 4
+; CHECK-PPC64LE-NEXT:    add 4, 5, 4
+; CHECK-PPC64LE-NEXT:    addi 4, 4, -4
+; CHECK-PPC64LE-NEXT:    stwbrx 3, 0, 4
 ; CHECK-PPC64LE-NEXT:    blr
 ;
 ; CHECK-PPC64-LABEL: store_i32_by_i8_bswap_base_index_offset:
 ; CHECK-PPC64:       # %bb.0: # %entry
-; CHECK-PPC64-NEXT:    extsw [[REG1:[0-9]+]], 4
-; CHECK-PPC64-NEXT:    add [[REG2:[0-9]+]], 5, [[REG1]] 
-; CHECK-PPC64-NEXT:    stw 3, -4([[REG2]])
+; CHECK-PPC64-NEXT:    extsw 4, 4
+; CHECK-PPC64-NEXT:    add 4, 5, 4
+; CHECK-PPC64-NEXT:    stw 3, -4(4)
 ; CHECK-PPC64-NEXT:    blr
 entry:
   %0 = lshr i32 %m, 16
   %conv = trunc i32 %0 to i8
   %sub = add nsw i32 %i, -3
   %idxprom = sext i32 %sub to i64
   %arrayidx = getelementptr inbounds i8, i8* %p, i64 %idxprom
   store i8 %conv, i8* %arrayidx, align 1

 ; i8 *p3 = p + i + 3;
 ; p0[3] = (m >> 24) & 0xFF;
 ; p1[3] = (m >> 16) & 0xFF;
 ; p2[3] = (m >> 8) & 0xFF;
 ; p3[3] = (m >> 0) & 0xFF;
 define void @store_i32_by_i8_bswap_complicated(i32 %m, i32 %i, i8* %p) {
 ; CHECK-PPC64LE-LABEL: store_i32_by_i8_bswap_complicated:
 ; CHECK-PPC64LE:       # %bb.0: # %entry
-; CHECK-PPC64LE-NEXT:    extsw [[REG1:[0-9]+]], 4
-; CHECK-PPC64LE-NEXT:    add [[REG2:[0-9]+]], 5, [[REG1]] 
-; CHECK-PPC64LE-NEXT:    addi [[REG3:[0-9]+]], [[REG2]], 3 
-; CHECK-PPC64LE-NEXT:    stwbrx 3, 0, [[REG3]] 
+; CHECK-PPC64LE-NEXT:    extsw 4, 4
+; CHECK-PPC64LE-NEXT:    add 4, 5, 4
+; CHECK-PPC64LE-NEXT:    addi 4, 4, 3
+; CHECK-PPC64LE-NEXT:    stwbrx 3, 0, 4
 ; CHECK-PPC64LE-NEXT:    blr
 ;
 ; CHECK-PPC64-LABEL: store_i32_by_i8_bswap_complicated:
 ; CHECK-PPC64:       # %bb.0: # %entry
-; CHECK-PPC64-NEXT:    extsw [[REG1:[0-9]+]], 4
-; CHECK-PPC64-NEXT:    add [[REG2:[0-9]+]], 5, [[REG1]] 
-; CHECK-PPC64-NEXT:    stw 3, 3([[REG2]])
+; CHECK-PPC64-NEXT:    extsw 4, 4
+; CHECK-PPC64-NEXT:    add 4, 5, 4
+; CHECK-PPC64-NEXT:    stw 3, 3(4)
 ; CHECK-PPC64-NEXT:    blr
 entry:
   %idx.ext = sext i32 %i to i64
   %add.ptr = getelementptr inbounds i8, i8* %p, i64 %idx.ext
   %add.ptr3 = getelementptr inbounds i8, i8* %add.ptr, i64 1
   %add.ptr6 = getelementptr inbounds i8, i8* %add.ptr, i64 2
   %add.ptr9 = getelementptr inbounds i8, i8* %add.ptr, i64 3
   %0 = lshr i32 %m, 24
entry:
   store i8 %conv5, i8* %arrayidx6, align 1
   ret void
 }
 ; This was found when testing the hexxagon in testsuite
 ; i8* p; i8 v;
 ; p[0] = v;
 ; p[1] = v;
 define void @store_same_value_to_consecutive_mem(i8* %p, i8 zeroext %v) {
-; CHECK-PPC64LE-LABEL: store_same_value_to_consecutive_mem 
-; CHECK-PPC64LE:       # %bb.0: # %entry 
-; CHECK-PPC64LE-NEXT:    stb 4, 0(3) 
-; CHECK-PPC64LE-NEXT:    stb 4, 1(3) 
+; CHECK-PPC64LE-LABEL: store_same_value_to_consecutive_mem:
+; CHECK-PPC64LE:       # %bb.0: # %entry
+; CHECK-PPC64LE-NEXT:    stb 4, 0(3)
+; CHECK-PPC64LE-NEXT:    stb 4, 1(3)
+; CHECK-PPC64LE-NEXT:    blr
 ;
-; CHECK-PPC64-LABEL: store_same_value_to_consecutive_mem 
+; CHECK-PPC64-LABEL: store_same_value_to_consecutive_mem:
 ; CHECK-PPC64:       # %bb.0: # %entry
 ; CHECK-PPC64-NEXT:    stb 4, 0(3)
 ; CHECK-PPC64-NEXT:    stb 4, 1(3)
+; CHECK-PPC64-NEXT:    blr
 entry:
   store i8 %v, i8* %p, align 1
   %arrayidx1 = getelementptr inbounds i8, i8* %p, i64 1
   store i8 %v, i8* %arrayidx1, align 1
   ret void
 }