[ARM] Add patterns for BSWAP intrinsic on MVE

[oliverlars]

Summary

BSWAP can use the VREV instruction on MVE to produce better results than expanding.

[oliverlars]

Added verify-machineinstrs

[dmgreen]

I guess an i8 bswap isn't a thing that makes sense! That's good.

Can you add a 64bit test. We have a vrev64.8 too if you want to try and add the codegen for it.

[oliverlars]

Added test for 2i64

[dmgreen]

LGTM

llvm/test/CodeGen/Thumb2/mve-bswap.ll

27

We get this one for free through a shuffle vector? That's good!

[oliverlars]

rGee6fbebbaff5

llvm/lib/Target/ARM/ARMISelLowering.cpp

for (auto VT : IntTypes) {
     setOperationAction(ISD::SMAX, VT, Legal);
     setOperationAction(ISD::UMIN, VT, Legal);
     setOperationAction(ISD::UMAX, VT, Legal);
     setOperationAction(ISD::ABS, VT, Legal);
     setOperationAction(ISD::SETCC, VT, Custom);
     setOperationAction(ISD::CTLZ, VT, Legal);
     setOperationAction(ISD::CTTZ, VT, Custom);
     setOperationAction(ISD::BITREVERSE, VT, Legal);
+    setOperationAction(ISD::BSWAP, VT, Legal);
 
     // No native support for these.
     setOperationAction(ISD::UDIV, VT, Expand);
     setOperationAction(ISD::SDIV, VT, Expand);
     setOperationAction(ISD::UREM, VT, Expand);
     setOperationAction(ISD::SREM, VT, Expand);
     setOperationAction(ISD::CTPOP, VT, Expand);
 

llvm/lib/Target/ARM/ARMInstrMVE.td

 def MVE_VREV64_32 : MVE_VREV<"vrev64", "32", 0b10, 0b00, "@earlyclobber $Qd">;
 
 def MVE_VREV32_8  : MVE_VREV<"vrev32", "8", 0b00, 0b01>;
 def MVE_VREV32_16 : MVE_VREV<"vrev32", "16", 0b01, 0b01>;
 
 def MVE_VREV16_8  : MVE_VREV<"vrev16", "8", 0b00, 0b10>;
 
 let Predicates = [HasMVEInt] in {
+  def : Pat<(v8i16 (bswap (v8i16 MQPR:$src))),
+            (v8i16 (MVE_VREV16_8 (v8i16 MQPR:$src)))>;
+  def : Pat<(v4i32 (bswap (v4i32 MQPR:$src))),
+            (v4i32 (MVE_VREV32_8 (v4i32 MQPR:$src)))>;
+}
+
+let Predicates = [HasMVEInt] in {
   def : Pat<(v4i32 (ARMvrev64 (v4i32 MQPR:$src))),
             (v4i32 (MVE_VREV64_32 (v4i32 MQPR:$src)))>;
   def : Pat<(v8i16 (ARMvrev64 (v8i16 MQPR:$src))),
             (v8i16 (MVE_VREV64_16 (v8i16 MQPR:$src)))>;
   def : Pat<(v16i8 (ARMvrev64 (v16i8 MQPR:$src))),
             (v16i8 (MVE_VREV64_8  (v16i8 MQPR:$src)))>;
 
   def : Pat<(v8i16 (ARMvrev32 (v8i16 MQPR:$src))),

llvm/test/CodeGen/Thumb2/mve-bswap.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s
+
+define arm_aapcs_vfpcc <4 x i32> @bswap_4i32_t(<4 x i32> %src){
+; CHECK-LABEL: bswap_4i32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrev32.8 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+    %0 = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %src)
+    ret <4 x i32> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @bswap_8i16_t(<8 x i16> %src){
+; CHECK-LABEL: bswap_8i16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrev16.8 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+    %0 = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %src)
+    ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <2 x i64> @bswap_2i64_t(<2 x i64> %src){
+; CHECK-LABEL: bswap_2i64_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrev64.8 q1, q0
+; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+    %0 = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %src)
+    ret <2 x i64> %0
+}
+
+declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
+declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
+declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)