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[SVE][Inline-Asm] Fix -Wimplicit-fallthrough in AArch64ISelLowering.cpp
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Authored by kmclaughlin on Sep 3 2019, 6:32 AM.

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Summary

Adds break to 'x' case in getRegForInlineAsmConstraint added by D66302, fixing the unintentional fallthrough.

LGTM

This revision is now accepted and ready to land.Sep 3 2019, 6:50 AM

This revision was automatically updated to reflect the committed changes.

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llvm/

trunk/

lib/

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AArch64/

1 line

Show First 20 Lines • Show All 5,828 Lines • ▼ Show 20 Lines	if (Constraint.size() == 1) {
// only take 128-bit registers so just use that regclass.		// only take 128-bit registers so just use that regclass.
case 'x':		case 'x':
if (!Subtarget->hasFPARMv8())		if (!Subtarget->hasFPARMv8())
break;		break;
if (VT.isScalableVector())		if (VT.isScalableVector())
return std::make_pair(0U, &AArch64::ZPR_4bRegClass);		return std::make_pair(0U, &AArch64::ZPR_4bRegClass);
if (VT.getSizeInBits() == 128)		if (VT.getSizeInBits() == 128)
return std::make_pair(0U, &AArch64::FPR128_loRegClass);		return std::make_pair(0U, &AArch64::FPR128_loRegClass);
		break;
case 'y':		case 'y':
if (!Subtarget->hasFPARMv8())		if (!Subtarget->hasFPARMv8())
break;		break;
if (VT.isScalableVector())		if (VT.isScalableVector())
return std::make_pair(0U, &AArch64::ZPR_3bRegClass);		return std::make_pair(0U, &AArch64::ZPR_3bRegClass);
break;		break;
}		}
}		}
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