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Differential D67048

[AMDGPU] Set default flat work group size to (1,256) for HIP
ClosedPublic

Authored by yaxunl on Sep 1 2019, 6:16 AM.

Details

Reviewers
arsenm
rampitec
b-sumner
Commits
rG1bea97c971d6: [AMDGPU] Set default flat work group size to (1,256) for HIP
rL370808: [AMDGPU] Set default flat work group size to (1,256) for HIP
rC370808: [AMDGPU] Set default flat work group size to (1,256) for HIP

Diff Detail

Event Timeline

yaxunl created this revision.Sep 1 2019, 6:16 AM
Herald added subscribers: t-tye, tpr, dstuttard and 2 others. · View Herald TranscriptSep 1 2019, 6:16 AM
yaxunl updated this revision to Diff 218261.Sep 1 2019, 6:48 AM

add test

Herald added a subscriber: jvesely. · View Herald TranscriptSep 1 2019, 6:48 AM
arsenm accepted this revision.Sep 1 2019, 8:06 AM

LGTM

This revision is now accepted and ready to land.Sep 1 2019, 8:06 AM
Closed by commit rL370808: [AMDGPU] Set default flat work group size to (1,256) for HIP (authored by yaxunl). · Explain WhySep 3 2019, 11:49 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptSep 3 2019, 11:49 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript

Revision Contents

PathSize
lib/
CodeGen/
7 lines

Diff 218259

lib/CodeGen/TargetInfo.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,916 Lines • ▼ Show 20 Linesvoid AMDGPUTargetCodeGenInfo::setTargetAttributes(
llvm::Function *F = cast<llvm::Function>(GV); llvm::Function *F = cast<llvm::Function>(GV);
const auto *ReqdWGS = M.getLangOpts().OpenCL ? const auto *ReqdWGS = M.getLangOpts().OpenCL ?
FD->getAttr<ReqdWorkGroupSizeAttr>() : nullptr; FD->getAttr<ReqdWorkGroupSizeAttr>() : nullptr;
const bool IsOpenCLKernel = M.getLangOpts().OpenCL && const bool IsOpenCLKernel = M.getLangOpts().OpenCL &&
FD->hasAttr<OpenCLKernelAttr>(); FD->hasAttr<OpenCLKernelAttr>();
if ((IsOpenCLKernel || const bool IsHIPKernel = M.getLangOpts().HIP &&
(M.getLangOpts().HIP && FD->hasAttr<CUDAGlobalAttr>())) && FD->hasAttr<CUDAGlobalAttr>();
if ((IsOpenCLKernel || IsHIPKernel) &&
(M.getTriple().getOS() == llvm::Triple::AMDHSA)) (M.getTriple().getOS() == llvm::Triple::AMDHSA))
F->addFnAttr("amdgpu-implicitarg-num-bytes", "56"); F->addFnAttr("amdgpu-implicitarg-num-bytes", "56");
const auto *FlatWGS = FD->getAttr<AMDGPUFlatWorkGroupSizeAttr>(); const auto *FlatWGS = FD->getAttr<AMDGPUFlatWorkGroupSizeAttr>();
if (ReqdWGS || FlatWGS) { if (ReqdWGS || FlatWGS) {
unsigned Min = 0; unsigned Min = 0;
unsigned Max = 0; unsigned Max = 0;
if (FlatWGS) { if (FlatWGS) {
Show All 9 Lines if (ReqdWGS || FlatWGS) {
if (Min != 0) { if (Min != 0) {
assert(Min <= Max && "Min must be less than or equal Max"); assert(Min <= Max && "Min must be less than or equal Max");
std::string AttrVal = llvm::utostr(Min) + "," + llvm::utostr(Max); std::string AttrVal = llvm::utostr(Min) + "," + llvm::utostr(Max);
F->addFnAttr("amdgpu-flat-work-group-size", AttrVal); F->addFnAttr("amdgpu-flat-work-group-size", AttrVal);
} else } else
assert(Max == 0 && "Max must be zero"); assert(Max == 0 && "Max must be zero");
} else if (IsOpenCLKernel) { } else if (IsOpenCLKernel || IsHIPKernel) {
// By default, restrict the maximum size to 256. // By default, restrict the maximum size to 256.
F->addFnAttr("amdgpu-flat-work-group-size", "1,256"); F->addFnAttr("amdgpu-flat-work-group-size", "1,256");
} }
if (const auto *Attr = FD->getAttr<AMDGPUWavesPerEUAttr>()) { if (const auto *Attr = FD->getAttr<AMDGPUWavesPerEUAttr>()) {
unsigned Min = unsigned Min =
Attr->getMin()->EvaluateKnownConstInt(M.getContext()).getExtValue(); Attr->getMin()->EvaluateKnownConstInt(M.getContext()).getExtValue();
unsigned Max = Attr->getMax() ? Attr->getMax() unsigned Max = Attr->getMax() ? Attr->getMax()
▲ Show 20 Lines • Show All 1,985 Lines • Show Last 20 Lines