[ARM] Fix MVE ldst offset ranges

[dmgreen]

Summary

We were using isShiftedInt<7, Shift>(RHSC) to detect the ranges of offsets to fold into MVE loads/stores. The instructions actually take a 7 bit unsigned integer which is either added or subtracted. So something more like isShiftedUInt<7, Shift>(abs(RHSC)).

Instead I've changes this to use the isScaledConstantInRange method, same as in SelectT2AddrModeImm7Offset used by pre/post inc, which seemed to already be getting this correct.

I've also added some extra testing around the negative extreme ranges, for which the differences are shown here.

[ostannard]

LGTM

llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp

OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
       ? CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32)
       : CurDAG->getTargetConstant(-RHSC, SDLoc(N), MVT::i32);
     return true;
   }
 
   return false;
 }
 
-template<unsigned Shift>
-bool ARMDAGToDAGISel::SelectT2AddrModeImm7(SDValue N,
-                                           SDValue &Base, SDValue &OffImm) {
-  if (N.getOpcode() == ISD::SUB ||
-      CurDAG->isBaseWithConstantOffset(N)) {
-    if (auto RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
-      int RHSC = (int)RHS->getZExtValue();
-      if (N.getOpcode() == ISD::SUB)
-        RHSC = -RHSC;
-
-      if (isShiftedInt<7, Shift>(RHSC)) {
-        Base = N.getOperand(0);
-        if (Base.getOpcode() == ISD::FrameIndex) {
-          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
-          Base = CurDAG->getTargetFrameIndex(
+template <unsigned Shift>
+bool ARMDAGToDAGISel::SelectT2AddrModeImm7(SDValue N, SDValue &Base,
+                                           SDValue &OffImm) {
+  if (N.getOpcode() == ISD::SUB || CurDAG->isBaseWithConstantOffset(N)) {
+    int RHSC;
+    if (isScaledConstantInRange(N.getOperand(1), 1 << Shift, -0x7f, 0x80,
+                                RHSC)) {
             FI, TLI->getPointerTy(CurDAG->getDataLayout()));
-        }
-        OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
-        return true;
-      }
-    }
-  }
+
+      if (N.getOpcode() == ISD::SUB)
+        RHSC = -RHSC;
+      OffImm =
+          CurDAG->getTargetConstant(RHSC * (1 << Shift), SDLoc(N), MVT::i32);
 
   // Base only.
   Base = N;
-  OffImm  = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
+  OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
   return true;
 }
 
 template <unsigned Shift>
 bool ARMDAGToDAGISel::SelectT2AddrModeImm7Offset(SDNode *Op, SDValue N,
                                                  SDValue &OffImm) {
   return SelectT2AddrModeImm7Offset(Op, N, OffImm, Shift);
 }

llvm/trunk/test/CodeGen/Thumb2/mve-ldst-offset.ll

entry:
   %2 = bitcast i8* %y to <4 x i32>*
   store <4 x i32> %1, <4 x i32>* %2, align 4
   ret i8* %x
 }
 
 define i8* @ldrwu32_508(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrwu32_508:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    add.w r2, r0, #508
-; CHECK-NEXT:    vldrw.u32 q0, [r2]
+; CHECK-NEXT:    vldrw.u32 q0, [r0, #508]
 ; CHECK-NEXT:    vstrw.32 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 508
   %0 = bitcast i8* %z to <4 x i32>*
   %1 = load <4 x i32>, <4 x i32>* %0, align 4
   %2 = bitcast i8* %y to <4 x i32>*
   store <4 x i32> %1, <4 x i32>* %2, align 4
entry:
   %2 = bitcast i8* %y to <4 x i32>*
   store <4 x i32> %1, <4 x i32>* %2, align 4
   ret i8* %x
 }
 
 define i8* @ldrwu32_m508(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrwu32_m508:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    sub.w r2, r0, #508
-; CHECK-NEXT:    vldrw.u32 q0, [r2]
+; CHECK-NEXT:    vldrw.u32 q0, [r0, #-508]
 ; CHECK-NEXT:    vstrw.32 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 -508
   %0 = bitcast i8* %z to <4 x i32>*
   %1 = load <4 x i32>, <4 x i32>* %0, align 4
   %2 = bitcast i8* %y to <4 x i32>*
   store <4 x i32> %1, <4 x i32>* %2, align 4
entry:
   %3 = bitcast i8* %y to <4 x i32>*
   store <4 x i32> %2, <4 x i32>* %3, align 4
   ret i8* %x
 }
 
 define i8* @ldrhu32_254(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrhu32_254:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    add.w r2, r0, #254
-; CHECK-NEXT:    vldrh.u32 q0, [r2]
+; CHECK-NEXT:    vldrh.u32 q0, [r0, #254]
 ; CHECK-NEXT:    vstrw.32 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 254
   %0 = bitcast i8* %z to <4 x i16>*
   %1 = load <4 x i16>, <4 x i16>* %0, align 2
   %2 = zext <4 x i16> %1 to <4 x i32>
   %3 = bitcast i8* %y to <4 x i32>*
entry:
   %3 = bitcast i8* %y to <4 x i32>*
   store <4 x i32> %2, <4 x i32>* %3, align 4
   ret i8* %x
 }
 
 define i8* @ldrhu32_m254(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrhu32_m254:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    sub.w r2, r0, #254
-; CHECK-NEXT:    vldrh.u32 q0, [r2]
+; CHECK-NEXT:    vldrh.u32 q0, [r0, #-254]
 ; CHECK-NEXT:    vstrw.32 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 -254
   %0 = bitcast i8* %z to <4 x i16>*
   %1 = load <4 x i16>, <4 x i16>* %0, align 2
   %2 = zext <4 x i16> %1 to <4 x i32>
   %3 = bitcast i8* %y to <4 x i32>*
entry:
   %3 = bitcast i8* %y to <4 x i32>*
   store <4 x i32> %2, <4 x i32>* %3, align 4
   ret i8* %x
 }
 
 define i8* @ldrhs32_254(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrhs32_254:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    add.w r2, r0, #254
-; CHECK-NEXT:    vldrh.s32 q0, [r2]
+; CHECK-NEXT:    vldrh.s32 q0, [r0, #254]
 ; CHECK-NEXT:    vstrw.32 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 254
   %0 = bitcast i8* %z to <4 x i16>*
   %1 = load <4 x i16>, <4 x i16>* %0, align 2
   %2 = sext <4 x i16> %1 to <4 x i32>
   %3 = bitcast i8* %y to <4 x i32>*
entry:
   %3 = bitcast i8* %y to <4 x i32>*
   store <4 x i32> %2, <4 x i32>* %3, align 4
   ret i8* %x
 }
 
 define i8* @ldrhs32_m254(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrhs32_m254:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    sub.w r2, r0, #254
-; CHECK-NEXT:    vldrh.s32 q0, [r2]
+; CHECK-NEXT:    vldrh.s32 q0, [r0, #-254]
 ; CHECK-NEXT:    vstrw.32 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 -254
   %0 = bitcast i8* %z to <4 x i16>*
   %1 = load <4 x i16>, <4 x i16>* %0, align 2
   %2 = sext <4 x i16> %1 to <4 x i32>
   %3 = bitcast i8* %y to <4 x i32>*
entry:
   %2 = bitcast i8* %y to <8 x i16>*
   store <8 x i16> %1, <8 x i16>* %2, align 2
   ret i8* %x
 }
 
 define i8* @ldrhu16_254(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrhu16_254:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    add.w r2, r0, #254
-; CHECK-NEXT:    vldrh.u16 q0, [r2]
+; CHECK-NEXT:    vldrh.u16 q0, [r0, #254]
 ; CHECK-NEXT:    vstrh.16 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 254
   %0 = bitcast i8* %z to <8 x i16>*
   %1 = load <8 x i16>, <8 x i16>* %0, align 2
   %2 = bitcast i8* %y to <8 x i16>*
   store <8 x i16> %1, <8 x i16>* %2, align 2
entry:
   %2 = bitcast i8* %y to <8 x i16>*
   store <8 x i16> %1, <8 x i16>* %2, align 2
   ret i8* %x
 }
 
 define i8* @ldrhu16_m254(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrhu16_m254:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    sub.w r2, r0, #254
-; CHECK-NEXT:    vldrh.u16 q0, [r2]
+; CHECK-NEXT:    vldrh.u16 q0, [r0, #-254]
 ; CHECK-NEXT:    vstrh.16 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 -254
   %0 = bitcast i8* %z to <8 x i16>*
   %1 = load <8 x i16>, <8 x i16>* %0, align 2
   %2 = bitcast i8* %y to <8 x i16>*
   store <8 x i16> %1, <8 x i16>* %2, align 2
entry:
   %3 = bitcast i8* %y to <4 x i32>*
   store <4 x i32> %2, <4 x i32>* %3, align 4
   ret i8* %x
 }
 
 define i8* @ldrbu32_127(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrbu32_127:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    add.w r2, r0, #127
-; CHECK-NEXT:    vldrb.u32 q0, [r2]
+; CHECK-NEXT:    vldrb.u32 q0, [r0, #127]
 ; CHECK-NEXT:    vstrw.32 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 127
   %0 = bitcast i8* %z to <4 x i8>*
   %1 = load <4 x i8>, <4 x i8>* %0, align 1
   %2 = zext <4 x i8> %1 to <4 x i32>
   %3 = bitcast i8* %y to <4 x i32>*
entry:
   %3 = bitcast i8* %y to <4 x i32>*
   store <4 x i32> %2, <4 x i32>* %3, align 4
   ret i8* %x
 }
 
 define i8* @ldrbu32_m127(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrbu32_m127:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    sub.w r2, r0, #127
-; CHECK-NEXT:    vldrb.u32 q0, [r2]
+; CHECK-NEXT:    vldrb.u32 q0, [r0, #-127]
 ; CHECK-NEXT:    vstrw.32 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 -127
   %0 = bitcast i8* %z to <4 x i8>*
   %1 = load <4 x i8>, <4 x i8>* %0, align 1
   %2 = zext <4 x i8> %1 to <4 x i32>
   %3 = bitcast i8* %y to <4 x i32>*
entry:
   %3 = bitcast i8* %y to <4 x i32>*
   store <4 x i32> %2, <4 x i32>* %3, align 4
   ret i8* %x
 }
 
 define i8* @ldrbs32_127(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrbs32_127:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    add.w r2, r0, #127
-; CHECK-NEXT:    vldrb.s32 q0, [r2]
+; CHECK-NEXT:    vldrb.s32 q0, [r0, #127]
 ; CHECK-NEXT:    vstrw.32 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 127
   %0 = bitcast i8* %z to <4 x i8>*
   %1 = load <4 x i8>, <4 x i8>* %0, align 1
   %2 = sext <4 x i8> %1 to <4 x i32>
   %3 = bitcast i8* %y to <4 x i32>*
entry:
   %3 = bitcast i8* %y to <4 x i32>*
   store <4 x i32> %2, <4 x i32>* %3, align 4
   ret i8* %x
 }
 
 define i8* @ldrbs32_m127(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrbs32_m127:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    sub.w r2, r0, #127
-; CHECK-NEXT:    vldrb.s32 q0, [r2]
+; CHECK-NEXT:    vldrb.s32 q0, [r0, #-127]
 ; CHECK-NEXT:    vstrw.32 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 -127
   %0 = bitcast i8* %z to <4 x i8>*
   %1 = load <4 x i8>, <4 x i8>* %0, align 1
   %2 = sext <4 x i8> %1 to <4 x i32>
   %3 = bitcast i8* %y to <4 x i32>*
entry:
   %3 = bitcast i8* %y to <8 x i16>*
   store <8 x i16> %2, <8 x i16>* %3, align 2
   ret i8* %x
 }
 
 define i8* @ldrbu16_127(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrbu16_127:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    add.w r2, r0, #127
-; CHECK-NEXT:    vldrb.u16 q0, [r2]
+; CHECK-NEXT:    vldrb.u16 q0, [r0, #127]
 ; CHECK-NEXT:    vstrh.16 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 127
   %0 = bitcast i8* %z to <8 x i8>*
   %1 = load <8 x i8>, <8 x i8>* %0, align 1
   %2 = zext <8 x i8> %1 to <8 x i16>
   %3 = bitcast i8* %y to <8 x i16>*
entry:
   %3 = bitcast i8* %y to <8 x i16>*
   store <8 x i16> %2, <8 x i16>* %3, align 2
   ret i8* %x
 }
 
 define i8* @ldrbu16_m127(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrbu16_m127:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    sub.w r2, r0, #127
-; CHECK-NEXT:    vldrb.u16 q0, [r2]
+; CHECK-NEXT:    vldrb.u16 q0, [r0, #-127]
 ; CHECK-NEXT:    vstrh.16 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 -127
   %0 = bitcast i8* %z to <8 x i8>*
   %1 = load <8 x i8>, <8 x i8>* %0, align 1
   %2 = zext <8 x i8> %1 to <8 x i16>
   %3 = bitcast i8* %y to <8 x i16>*
entry:
   %3 = bitcast i8* %y to <8 x i16>*
   store <8 x i16> %2, <8 x i16>* %3, align 2
   ret i8* %x
 }
 
 define i8* @ldrbs16_127(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrbs16_127:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    add.w r2, r0, #127
-; CHECK-NEXT:    vldrb.s16 q0, [r2]
+; CHECK-NEXT:    vldrb.s16 q0, [r0, #127]
 ; CHECK-NEXT:    vstrh.16 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 127
   %0 = bitcast i8* %z to <8 x i8>*
   %1 = load <8 x i8>, <8 x i8>* %0, align 1
   %2 = sext <8 x i8> %1 to <8 x i16>
   %3 = bitcast i8* %y to <8 x i16>*
entry:
   %3 = bitcast i8* %y to <8 x i16>*
   store <8 x i16> %2, <8 x i16>* %3, align 2
   ret i8* %x
 }
 
 define i8* @ldrbs16_m127(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrbs16_m127:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    sub.w r2, r0, #127
-; CHECK-NEXT:    vldrb.s16 q0, [r2]
+; CHECK-NEXT:    vldrb.s16 q0, [r0, #-127]
 ; CHECK-NEXT:    vstrh.16 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 -127
   %0 = bitcast i8* %z to <8 x i8>*
   %1 = load <8 x i8>, <8 x i8>* %0, align 1
   %2 = sext <8 x i8> %1 to <8 x i16>
   %3 = bitcast i8* %y to <8 x i16>*
entry:
   %2 = bitcast i8* %y to <16 x i8>*
   store <16 x i8> %1, <16 x i8>* %2, align 1
   ret i8* %x
 }
 
 define i8* @ldrbu8_127(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrbu8_127:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    add.w r2, r0, #127
-; CHECK-NEXT:    vldrb.u8 q0, [r2]
+; CHECK-NEXT:    vldrb.u8 q0, [r0, #127]
 ; CHECK-NEXT:    vstrb.8 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 127
   %0 = bitcast i8* %z to <16 x i8>*
   %1 = load <16 x i8>, <16 x i8>* %0, align 1
   %2 = bitcast i8* %y to <16 x i8>*
   store <16 x i8> %1, <16 x i8>* %2, align 1
entry:
   %2 = bitcast i8* %y to <16 x i8>*
   store <16 x i8> %1, <16 x i8>* %2, align 1
   ret i8* %x
 }
 
 define i8* @ldrbu8_m127(i8* %x, i8* %y) {
 ; CHECK-LABEL: ldrbu8_m127:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    sub.w r2, r0, #127
-; CHECK-NEXT:    vldrb.u8 q0, [r2]
+; CHECK-NEXT:    vldrb.u8 q0, [r0, #-127]
 ; CHECK-NEXT:    vstrb.8 q0, [r1]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %x, i32 -127
   %0 = bitcast i8* %z to <16 x i8>*
   %1 = load <16 x i8>, <16 x i8>* %0, align 1
   %2 = bitcast i8* %y to <16 x i8>*
   store <16 x i8> %1, <16 x i8>* %2, align 1
entry:
   store <4 x i32> %1, <4 x i32>* %2, align 4
   ret i8* %y
 }
 
 define i8* @strw32_508(i8* %y, i8* %x) {
 ; CHECK-LABEL: strw32_508:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
-; CHECK-NEXT:    add.w r1, r0, #508
-; CHECK-NEXT:    vstrw.32 q0, [r1]
+; CHECK-NEXT:    vstrw.32 q0, [r0, #508]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %y, i32 508
   %0 = bitcast i8* %x to <4 x i32>*
   %1 = load <4 x i32>, <4 x i32>* %0, align 4
   %2 = bitcast i8* %z to <4 x i32>*
   store <4 x i32> %1, <4 x i32>* %2, align 4
   ret i8* %y
entry:
   store <4 x i32> %1, <4 x i32>* %2, align 4
   ret i8* %y
 }
 
 define i8* @strw32_m508(i8* %y, i8* %x) {
 ; CHECK-LABEL: strw32_m508:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
-; CHECK-NEXT:    sub.w r1, r0, #508
-; CHECK-NEXT:    vstrw.32 q0, [r1]
+; CHECK-NEXT:    vstrw.32 q0, [r0, #-508]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %y, i32 -508
   %0 = bitcast i8* %x to <4 x i32>*
   %1 = load <4 x i32>, <4 x i32>* %0, align 4
   %2 = bitcast i8* %z to <4 x i32>*
   store <4 x i32> %1, <4 x i32>* %2, align 4
   ret i8* %y
entry:
   store <4 x i16> %1, <4 x i16>* %2, align 2
   ret i8* %y
 }
 
 define i8* @strh32_254(i8* %y, i8* %x) {
 ; CHECK-LABEL: strh32_254:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldrh.u32 q0, [r1]
-; CHECK-NEXT:    add.w r1, r0, #254
-; CHECK-NEXT:    vstrh.32 q0, [r1]
+; CHECK-NEXT:    vstrh.32 q0, [r0, #254]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %y, i32 254
   %0 = bitcast i8* %x to <4 x i16>*
   %1 = load <4 x i16>, <4 x i16>* %0, align 2
   %2 = bitcast i8* %z to <4 x i16>*
   store <4 x i16> %1, <4 x i16>* %2, align 2
   ret i8* %y
entry:
   store <4 x i16> %1, <4 x i16>* %2, align 2
   ret i8* %y
 }
 
 define i8* @strh32_m254(i8* %y, i8* %x) {
 ; CHECK-LABEL: strh32_m254:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldrh.u32 q0, [r1]
-; CHECK-NEXT:    sub.w r1, r0, #254
-; CHECK-NEXT:    vstrh.32 q0, [r1]
+; CHECK-NEXT:    vstrh.32 q0, [r0, #-254]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %y, i32 -254
   %0 = bitcast i8* %x to <4 x i16>*
   %1 = load <4 x i16>, <4 x i16>* %0, align 2
   %2 = bitcast i8* %z to <4 x i16>*
   store <4 x i16> %1, <4 x i16>* %2, align 2
   ret i8* %y
entry:
   store <8 x i16> %1, <8 x i16>* %2, align 2
   ret i8* %y
 }
 
 define i8* @strh16_254(i8* %y, i8* %x) {
 ; CHECK-LABEL: strh16_254:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldrh.u16 q0, [r1]
-; CHECK-NEXT:    add.w r1, r0, #254
-; CHECK-NEXT:    vstrh.16 q0, [r1]
+; CHECK-NEXT:    vstrh.16 q0, [r0, #254]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %y, i32 254
   %0 = bitcast i8* %x to <8 x i16>*
   %1 = load <8 x i16>, <8 x i16>* %0, align 2
   %2 = bitcast i8* %z to <8 x i16>*
   store <8 x i16> %1, <8 x i16>* %2, align 2
   ret i8* %y
entry:
   store <8 x i16> %1, <8 x i16>* %2, align 2
   ret i8* %y
 }
 
 define i8* @strh16_m254(i8* %y, i8* %x) {
 ; CHECK-LABEL: strh16_m254:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldrh.u16 q0, [r1]
-; CHECK-NEXT:    sub.w r1, r0, #254
-; CHECK-NEXT:    vstrh.16 q0, [r1]
+; CHECK-NEXT:    vstrh.16 q0, [r0, #-254]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %y, i32 -254
   %0 = bitcast i8* %x to <8 x i16>*
   %1 = load <8 x i16>, <8 x i16>* %0, align 2
   %2 = bitcast i8* %z to <8 x i16>*
   store <8 x i16> %1, <8 x i16>* %2, align 2
   ret i8* %y
entry:
   store <4 x i8> %1, <4 x i8>* %2, align 1
   ret i8* %y
 }
 
 define i8* @strb32_127(i8* %y, i8* %x) {
 ; CHECK-LABEL: strb32_127:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldrb.u32 q0, [r1]
-; CHECK-NEXT:    add.w r1, r0, #127
-; CHECK-NEXT:    vstrb.32 q0, [r1]
+; CHECK-NEXT:    vstrb.32 q0, [r0, #127]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %y, i32 127
   %0 = bitcast i8* %x to <4 x i8>*
   %1 = load <4 x i8>, <4 x i8>* %0, align 1
   %2 = bitcast i8* %z to <4 x i8>*
   store <4 x i8> %1, <4 x i8>* %2, align 1
   ret i8* %y
entry:
   store <4 x i8> %1, <4 x i8>* %2, align 1
   ret i8* %y
 }
 
 define i8* @strb32_m127(i8* %y, i8* %x) {
 ; CHECK-LABEL: strb32_m127:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldrb.u32 q0, [r1]
-; CHECK-NEXT:    sub.w r1, r0, #127
-; CHECK-NEXT:    vstrb.32 q0, [r1]
+; CHECK-NEXT:    vstrb.32 q0, [r0, #-127]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %y, i32 -127
   %0 = bitcast i8* %x to <4 x i8>*
   %1 = load <4 x i8>, <4 x i8>* %0, align 1
   %2 = bitcast i8* %z to <4 x i8>*
   store <4 x i8> %1, <4 x i8>* %2, align 1
   ret i8* %y
entry:
   store <8 x i8> %1, <8 x i8>* %2, align 1
   ret i8* %y
 }
 
 define i8* @strb16_127(i8* %y, i8* %x) {
 ; CHECK-LABEL: strb16_127:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldrb.u16 q0, [r1]
-; CHECK-NEXT:    add.w r1, r0, #127
-; CHECK-NEXT:    vstrb.16 q0, [r1]
+; CHECK-NEXT:    vstrb.16 q0, [r0, #127]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %y, i32 127
   %0 = bitcast i8* %x to <8 x i8>*
   %1 = load <8 x i8>, <8 x i8>* %0, align 1
   %2 = bitcast i8* %z to <8 x i8>*
   store <8 x i8> %1, <8 x i8>* %2, align 1
   ret i8* %y
entry:
   store <8 x i8> %1, <8 x i8>* %2, align 1
   ret i8* %y
 }
 
 define i8* @strb16_m127(i8* %y, i8* %x) {
 ; CHECK-LABEL: strb16_m127:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldrb.u16 q0, [r1]
-; CHECK-NEXT:    sub.w r1, r0, #127
-; CHECK-NEXT:    vstrb.16 q0, [r1]
+; CHECK-NEXT:    vstrb.16 q0, [r0, #-127]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %y, i32 -127
   %0 = bitcast i8* %x to <8 x i8>*
   %1 = load <8 x i8>, <8 x i8>* %0, align 1
   %2 = bitcast i8* %z to <8 x i8>*
   store <8 x i8> %1, <8 x i8>* %2, align 1
   ret i8* %y
entry:
   store <16 x i8> %1, <16 x i8>* %2, align 1
   ret i8* %y
 }
 
 define i8* @strb8_127(i8* %y, i8* %x) {
 ; CHECK-LABEL: strb8_127:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldrb.u8 q0, [r1]
-; CHECK-NEXT:    add.w r1, r0, #127
-; CHECK-NEXT:    vstrb.8 q0, [r1]
+; CHECK-NEXT:    vstrb.8 q0, [r0, #127]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %y, i32 127
   %0 = bitcast i8* %x to <16 x i8>*
   %1 = load <16 x i8>, <16 x i8>* %0, align 1
   %2 = bitcast i8* %z to <16 x i8>*
   store <16 x i8> %1, <16 x i8>* %2, align 1
   ret i8* %y
entry:
   store <16 x i8> %1, <16 x i8>* %2, align 1
   ret i8* %y
 }
 
 define i8* @strb8_m127(i8* %y, i8* %x) {
 ; CHECK-LABEL: strb8_m127:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldrb.u8 q0, [r1]
-; CHECK-NEXT:    sub.w r1, r0, #127
-; CHECK-NEXT:    vstrb.8 q0, [r1]
+; CHECK-NEXT:    vstrb.8 q0, [r0, #-127]
 ; CHECK-NEXT:    bx lr
 entry:
   %z = getelementptr inbounds i8, i8* %y, i32 -127
   %0 = bitcast i8* %x to <16 x i8>*
   %1 = load <16 x i8>, <16 x i8>* %0, align 1
   %2 = bitcast i8* %z to <16 x i8>*
   store <16 x i8> %1, <16 x i8>* %2, align 1
   ret i8* %y

llvm/trunk/test/CodeGen/Thumb2/mve-loadstore.ll

entry:
   %0 = lshr <4 x i32> %val, <i32 1, i32 1, i32 1, i32 1>
   store <4 x i32> %0, <4 x i32>* %vp, align 1
   ret void
 }
 
 define arm_aapcs_vfpcc <4 x i32> @load_4xi32_a4_offset_pos(i32* %ip) {
 ; CHECK-LE-LABEL: load_4xi32_a4_offset_pos:
 ; CHECK-LE:       @ %bb.0: @ %entry
-; CHECK-LE-NEXT:    add.w r0, r0, #508
-; CHECK-LE-NEXT:    vldrw.u32 q0, [r0]
+; CHECK-LE-NEXT:    vldrw.u32 q0, [r0, #508]
 ; CHECK-LE-NEXT:    bx lr
 ;
 ; CHECK-BE-LABEL: load_4xi32_a4_offset_pos:
 ; CHECK-BE:       @ %bb.0: @ %entry
 ; CHECK-BE-NEXT:    add.w r0, r0, #508
 ; CHECK-BE-NEXT:    vldrb.u8 q1, [r0]
 ; CHECK-BE-NEXT:    vrev64.8 q0, q1
 ; CHECK-BE-NEXT:    bx lr
 entry:
   %ipoffset = getelementptr inbounds i32, i32* %ip, i32 127
   %vp = bitcast i32* %ipoffset to <4 x i32>*
   %0 = load <4 x i32>, <4 x i32>* %vp, align 4
   ret <4 x i32> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @load_4xi32_a4_offset_neg(i32* %ip) {
 ; CHECK-LE-LABEL: load_4xi32_a4_offset_neg:
 ; CHECK-LE:       @ %bb.0: @ %entry
-; CHECK-LE-NEXT:    sub.w r0, r0, #508
-; CHECK-LE-NEXT:    vldrw.u32 q0, [r0]
+; CHECK-LE-NEXT:    vldrw.u32 q0, [r0, #-508]
 ; CHECK-LE-NEXT:    bx lr
 ;
 ; CHECK-BE-LABEL: load_4xi32_a4_offset_neg:
 ; CHECK-BE:       @ %bb.0: @ %entry
 ; CHECK-BE-NEXT:    sub.w r0, r0, #508
 ; CHECK-BE-NEXT:    vldrb.u8 q1, [r0]
 ; CHECK-BE-NEXT:    vrev64.8 q0, q1
 ; CHECK-BE-NEXT:    bx lr