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Differential D66769

[GlobalISel] Import patterns containing SUBREG_TO_REG
ClosedPublic

Authored by paquette on Aug 26 2019, 2:51 PM.

Details

Reviewers
aemerson
dsanders
arsenm
igorb
Commits
rG7080ffa21a41: [GlobalISel] Import patterns containing SUBREG_TO_REG
rL370254: [GlobalISel] Import patterns containing SUBREG_TO_REG
Summary

Reuse the logic for INSERT_SUBREG to also import SUBREG_TO_REG patterns. There are some intrinsic + load/store patterns in AArch64 that use this.

  • Split inferSuperRegisterClass into two functions, one which tries to use an existing TreePatternNode (inferSuperRegisterClassForNode), and one that doesn't. SUBREG_TO_REG doesn't have a node to leverage, which is the cause for the split.
  • Rename GlobalISelEmitterInsertSubreg.td to GlobalISelEmitterSubreg.td and update it.
  • Update impacted tests in the AArch64 and X86 backends.

This is kind of a hit/miss for code size improvements/regressions. E.g. in add-ext.ll, we now get some identity copies. This isn't really anything the importer can handle, since it's caused by a later pass introducing the copy for the sake of correctness.

Diff Detail

Repository
rL LLVM

Event Timeline

paquette created this revision.Aug 26 2019, 2:51 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 26 2019, 2:51 PM
Herald added subscribers: Petar.Avramovic, jfb, kristof.beyls and 3 others. · View Herald Transcript
paquette updated this revision to Diff 217250.Aug 26 2019, 2:53 PM

Add missing change to a fast isel test

aemerson added a subscriber: t.p.northover.Aug 26 2019, 3:50 PM

This is kind of a hit/miss for code size improvements/regressions. E.g. in add-ext.ll, we now get some identity copies. This isn't really anything the importer can handle, since it's caused by a later pass introducing the copy for the sake of correctness.

To clarify this for upstream after we had some private discussion: what's happening here is that the x86 GISel backend previously implemented i16->i32 anyexts with custom C++ selection as INSERT_SUBREG. With this change, we start importing the new SelectionDAG pattern which changed the anyext representation to SUBREG_TO_REG. As a result, the imul instruction which is destructive in it's first source operand, and thus relies on the TwoAddress pass to add copies, now results in an additional copy because TwoAddress commutes the source ops, causing the SUBREG_TO_REG to be the destroyed operand, and therefore we see an extra copy inserted. There isn't really anything GISel can do here it seems to avoid this. There might be the case for identity copies to be eliminated after regalloc though, it's surprising it doesn't already happen.

llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
139 ↗(On Diff #217250)

I've verified that this code is exactly what the x86 SDAG backend wants for the pattern. The original pattern seems to have been introduced by @t.p.northover in r182921. Why an anyext of GR8->i64 would want to use a mov + subreg_to_reg instead of just a subreg_to_reg I don't know.

paquette added a child revision: D66897: [AArch64][GlobalISel] Select @llvm.aarch64.ldaxr.* intrinsics.Aug 28 2019, 10:52 AM
paquette mentioned this in D65422: [GlobalISel][AArch64] Add naive selection for @llvm.aarch64.ldaxr.
paquette added a child revision: D66898: [AArch64][GlobalISel] Select @llvm.aarch64.ldxr.* intrinsics.Aug 28 2019, 11:05 AM
dsanders accepted this revision.Aug 28 2019, 11:25 AM

LGTM aside from the redundant movl's. I see you've already commented on those though and given that another pass is introducing them it should probably be on that pass to avoid them if they're truly redundant

llvm/test/CodeGen/X86/GlobalISel/add-ext.ll
205 ↗(On Diff #217250)

Redundant movl instruction?

210 ↗(On Diff #217250)

Redundant movl instruction?

This revision is now accepted and ready to land.Aug 28 2019, 11:25 AM
Closed by commit rL370254: [GlobalISel] Import patterns containing SUBREG_TO_REG (authored by paquette). · Explain WhyAug 28 2019, 1:11 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
test/
CodeGen/
AArch64/
GlobalISel/
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93 lines
70 lines
5 lines
17 lines
5 lines
10 lines
3 lines
58 lines
2 lines
X86/
GlobalISel/
7 lines
6 lines
3 lines
TableGen/
18 lines
utils/
TableGen/
104 lines

Diff 217707

llvm/trunk/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir

Show First 20 Lines • Show All 280 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
; Show that we don't get a shifted load from a mul when we don't have a ; Show that we don't get a shifted load from a mul when we don't have a
; power of 2. (The bit isn't set on the load.) ; power of 2. (The bit isn't set on the load.)
liveins: $x0, $x1, $d2 liveins: $x0, $x1, $d2
; CHECK-LABEL: name: mul_not_pow_2 ; CHECK-LABEL: name: mul_not_pow_2
; CHECK: liveins: $x0, $x1, $d2 ; CHECK: liveins: $x0, $x1, $d2
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 7 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[MOVi64imm]], [[COPY]], $xzr ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[SUBREG_TO_REG]], [[COPY]], $xzr
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1
; CHECK: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[MADDXrrr]], 0, 0 :: (load 8 from %ir.addr) ; CHECK: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[MADDXrrr]], 0, 0 :: (load 8 from %ir.addr)
; CHECK: $d2 = COPY [[LDRDroX]] ; CHECK: $d2 = COPY [[LDRDroX]]
; CHECK: RET_ReallyLR implicit $d2 ; CHECK: RET_ReallyLR implicit $d2
%0:gpr(s64) = COPY $x0 %0:gpr(s64) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 7 %1:gpr(s64) = G_CONSTANT i64 7
%2:gpr(s64) = G_MUL %1, %0(s64) %2:gpr(s64) = G_MUL %1, %0(s64)
%3:gpr(p0) = COPY $x1 %3:gpr(p0) = COPY $x1
Show All 13 Lines
body: | body: |
bb.0: bb.0:
; Show that we don't get a shifted load from a mul when we don't have ; Show that we don't get a shifted load from a mul when we don't have
; the right power of 2. (The bit isn't set on the load.) ; the right power of 2. (The bit isn't set on the load.)
liveins: $x0, $x1, $d2 liveins: $x0, $x1, $d2
; CHECK-LABEL: name: mul_wrong_pow_2 ; CHECK-LABEL: name: mul_wrong_pow_2
; CHECK: liveins: $x0, $x1, $d2 ; CHECK: liveins: $x0, $x1, $d2
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 16 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 16
; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[MOVi64imm]], [[COPY]], $xzr ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[SUBREG_TO_REG]], [[COPY]], $xzr
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1
; CHECK: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[MADDXrrr]], 0, 0 :: (load 8 from %ir.addr) ; CHECK: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[MADDXrrr]], 0, 0 :: (load 8 from %ir.addr)
; CHECK: $d2 = COPY [[LDRDroX]] ; CHECK: $d2 = COPY [[LDRDroX]]
; CHECK: RET_ReallyLR implicit $d2 ; CHECK: RET_ReallyLR implicit $d2
%0:gpr(s64) = COPY $x0 %0:gpr(s64) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 16 %1:gpr(s64) = G_CONSTANT i64 16
%2:gpr(s64) = G_MUL %1, %0(s64) %2:gpr(s64) = G_MUL %1, %0(s64)
%3:gpr(p0) = COPY $x1 %3:gpr(p0) = COPY $x1
▲ Show 20 Lines • Show All 303 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir

Show All 38 Lines
body: | body: |
bb.0: bb.0:
liveins: $w0, $w1 liveins: $w0, $w1
; CHECK-LABEL: name: cmn_s32_rhs ; CHECK-LABEL: name: cmn_s32_rhs
; CHECK: liveins: $w0, $w1 ; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVwzr:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv ; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVwzr]], 1, implicit $nzcv ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 1, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0 %0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1 %1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0 %2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1 %6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_SUB %2, %1 %3:gpr(s32) = G_SUB %2, %1
%7:gpr(s32) = G_ICMP intpred(ne), %0(s32), %3 %7:gpr(s32) = G_ICMP intpred(ne), %0(s32), %3
Show All 12 Lines
body: | body: |
bb.0: bb.0:
liveins: $w0, $w1 liveins: $w0, $w1
; CHECK-LABEL: name: cmn_s32_lhs ; CHECK-LABEL: name: cmn_s32_lhs
; CHECK: liveins: $w0, $w1 ; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv ; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 1, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0 %0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1 %1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0 %2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1 %6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_SUB %2, %0 %3:gpr(s32) = G_SUB %2, %0
%7:gpr(s32) = G_ICMP intpred(ne), %3(s32), %1 %7:gpr(s32) = G_ICMP intpred(ne), %3(s32), %1
Show All 12 Lines
body: | body: |
bb.0: bb.0:
liveins: $w0, $w1 liveins: $w0, $w1
; CHECK-LABEL: name: no_cmn_s32_rhs ; CHECK-LABEL: name: no_cmn_s32_rhs
; CHECK: liveins: $w0, $w1 ; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[MOVi32imm]], [[COPY1]], implicit-def $nzcv ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY1]], implicit-def $nzcv
; CHECK: $wzr = SUBSWrr [[COPY]], [[SUBSWrr]], implicit-def $nzcv ; CHECK: $wzr = SUBSWrr [[COPY]], [[SUBSWrr]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 11, implicit $nzcv ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 11, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0 %0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1 %1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0 %2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1 %6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_SUB %2, %1 %3:gpr(s32) = G_SUB %2, %1
%7:gpr(s32) = G_ICMP intpred(slt), %0(s32), %3 %7:gpr(s32) = G_ICMP intpred(slt), %0(s32), %3
Show All 12 Lines
body: | body: |
bb.0: bb.0:
liveins: $w0, $w1 liveins: $w0, $w1
; CHECK-LABEL: name: no_cmn_s32_lhs ; CHECK-LABEL: name: no_cmn_s32_lhs
; CHECK: liveins: $w0, $w1 ; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[MOVi32imm]], [[COPY]], implicit-def $nzcv ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY]], implicit-def $nzcv
; CHECK: $wzr = SUBSWrr [[SUBSWrr]], [[COPY1]], implicit-def $nzcv ; CHECK: $wzr = SUBSWrr [[SUBSWrr]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 11, implicit $nzcv ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 11, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0 %0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1 %1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0 %2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1 %6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_SUB %2, %0 %3:gpr(s32) = G_SUB %2, %0
%7:gpr(s32) = G_ICMP intpred(slt), %3(s32), %1 %7:gpr(s32) = G_ICMP intpred(slt), %3(s32), %1
Show All 12 Lines
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; CHECK-LABEL: name: cmn_s64_rhs ; CHECK-LABEL: name: cmn_s64_rhs
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = COPY $xzr ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv ; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv ; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 1, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]] ; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0 %0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1 %1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0 %2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1 %6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_SUB %2, %1 %3:gpr(s64) = G_SUB %2, %1
%7:gpr(s32) = G_ICMP intpred(ne), %0(s64), %3 %7:gpr(s32) = G_ICMP intpred(ne), %0(s64), %3
Show All 12 Lines
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; CHECK-LABEL: name: cmn_s64_lhs ; CHECK-LABEL: name: cmn_s64_lhs
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = COPY $xzr ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv ; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv ; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 1, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]] ; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0 %0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1 %1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0 %2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1 %6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_SUB %2, %0 %3:gpr(s64) = G_SUB %2, %0
%7:gpr(s32) = G_ICMP intpred(ne), %3(s64), %1 %7:gpr(s32) = G_ICMP intpred(ne), %3(s64), %1
Show All 12 Lines
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; CHECK-LABEL: name: no_cmn_s64_rhs ; CHECK-LABEL: name: no_cmn_s64_rhs
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = COPY $xzr ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[MOVi64imm]], [[COPY1]], implicit-def $nzcv ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY1]], implicit-def $nzcv
; CHECK: $xzr = SUBSXrr [[COPY]], [[SUBSXrr]], implicit-def $nzcv ; CHECK: $xzr = SUBSXrr [[COPY]], [[SUBSXrr]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 11, implicit $nzcv ; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 11, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]] ; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0 %0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1 %1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0 %2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1 %6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_SUB %2, %1 %3:gpr(s64) = G_SUB %2, %1
%7:gpr(s32) = G_ICMP intpred(slt), %0(s64), %3 %7:gpr(s32) = G_ICMP intpred(slt), %0(s64), %3
Show All 12 Lines
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; CHECK-LABEL: name: no_cmn_s64_lhs ; CHECK-LABEL: name: no_cmn_s64_lhs
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = COPY $xzr ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[MOVi64imm]], [[COPY]], implicit-def $nzcv ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY]], implicit-def $nzcv
; CHECK: $xzr = SUBSXrr [[SUBSXrr]], [[COPY1]], implicit-def $nzcv ; CHECK: $xzr = SUBSXrr [[SUBSXrr]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 11, implicit $nzcv ; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 11, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]] ; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0 %0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1 %1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0 %2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1 %6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_SUB %2, %0 %3:gpr(s64) = G_SUB %2, %0
%7:gpr(s32) = G_ICMP intpred(slt), %3(s64), %1 %7:gpr(s32) = G_ICMP intpred(slt), %3(s64), %1
Show All 10 Lines
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $w0, $w1 liveins: $w0, $w1
; CHECK-LABEL: name: tst_s32 ; CHECK-LABEL: name: tst_s32
; CHECK: liveins: $w0, $w1 ; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: $wzr = ANDSWrr [[MOVi32imm]], [[COPY]], implicit-def $nzcv ; CHECK: $wzr = ANDSWrr [[COPY1]], [[COPY]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 0, implicit $nzcv ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 0, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0 %0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1 %1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0 %2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1 %6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_AND %2, %1 %3:gpr(s32) = G_AND %2, %1
%8:gpr(s32) = G_CONSTANT i32 0 %8:gpr(s32) = G_CONSTANT i32 0
Show All 11 Lines
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; CHECK-LABEL: name: tst_s64 ; CHECK-LABEL: name: tst_s64
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x1 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = COPY $xzr ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: $xzr = ANDSXrr [[MOVi64imm]], [[COPY]], implicit-def $nzcv ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 0, implicit $nzcv ; CHECK: $xzr = ANDSXrr [[COPY1]], [[COPY]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY1]], 0, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]] ; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0 %0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1 %1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0 %2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1 %6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_AND %2, %1 %3:gpr(s64) = G_AND %2, %1
%8:gpr(s64) = G_CONSTANT i64 0 %8:gpr(s64) = G_CONSTANT i64 0
Show All 11 Lines
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $w0, $w1 liveins: $w0, $w1
; CHECK-LABEL: name: no_tst_unsigned_compare ; CHECK-LABEL: name: no_tst_unsigned_compare
; CHECK: liveins: $w0, $w1 ; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[MOVi32imm]], [[COPY]] ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]]
; CHECK: $wzr = SUBSWri [[ANDWrr]], 0, 0, implicit-def $nzcv ; CHECK: $wzr = SUBSWri [[ANDWrr]], 0, 0, implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 8, implicit $nzcv ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 8, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0 %0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1 %1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0 %2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1 %6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_AND %2, %1 %3:gpr(s32) = G_AND %2, %1
%8:gpr(s32) = G_CONSTANT i32 0 %8:gpr(s32) = G_CONSTANT i32 0
Show All 11 Lines
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $w0, $w1 liveins: $w0, $w1
; CHECK-LABEL: name: no_tst_nonzero ; CHECK-LABEL: name: no_tst_nonzero
; CHECK: liveins: $w0, $w1 ; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[MOVi32imm]], [[COPY]] ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]]
; CHECK: $wzr = SUBSWri [[ANDWrr]], 42, 0, implicit-def $nzcv ; CHECK: $wzr = SUBSWri [[ANDWrr]], 42, 0, implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 8, implicit $nzcv ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 8, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0 %0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1 %1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0 %2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1 %6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_AND %2, %1 %3:gpr(s32) = G_AND %2, %1
%8:gpr(s32) = G_CONSTANT i32 42 %8:gpr(s32) = G_CONSTANT i32 42
▲ Show 20 Lines • Show All 96 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir

Show All 23 Lines
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: atomicrmw_xchg_i64 ; CHECK-LABEL: name: atomicrmw_xchg_i64
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr64 = SWPX [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr) ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: $x0 = COPY [[RES]] ; CHECK: [[SWPX:%[0-9]+]]:gpr64 = SWPX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
; CHECK: $x0 = COPY [[SWPX]]
%0:gpr(p0) = COPY $x0 %0:gpr(p0) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 1 %1:gpr(s64) = G_CONSTANT i64 1
%2:gpr(s64) = G_ATOMICRMW_XCHG %0, %1 :: (load store monotonic 8 on %ir.addr) %2:gpr(s64) = G_ATOMICRMW_XCHG %0, %1 :: (load store monotonic 8 on %ir.addr)
$x0 = COPY %2(s64) $x0 = COPY %2(s64)
... ...
--- ---
name: atomicrmw_add_i64 name: atomicrmw_add_i64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: atomicrmw_add_i64 ; CHECK-LABEL: name: atomicrmw_add_i64
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr64 = LDADDX [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr) ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: $x0 = COPY [[RES]] ; CHECK: [[LDADDX:%[0-9]+]]:gpr64 = LDADDX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
; CHECK: $x0 = COPY [[LDADDX]]
%0:gpr(p0) = COPY $x0 %0:gpr(p0) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 1 %1:gpr(s64) = G_CONSTANT i64 1
%2:gpr(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 8 on %ir.addr) %2:gpr(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 8 on %ir.addr)
$x0 = COPY %2(s64) $x0 = COPY %2(s64)
... ...
--- ---
name: atomicrmw_add_i32 name: atomicrmw_add_i32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: atomicrmw_add_i32 ; CHECK-LABEL: name: atomicrmw_add_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDADDALW [[CST]], [[COPY]] :: (load store seq_cst 4 on %ir.addr) ; CHECK: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst 4 on %ir.addr)
; CHECK: $w0 = COPY [[RES]] ; CHECK: $w0 = COPY [[LDADDALW]]
%0:gpr(p0) = COPY $x0 %0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1 %1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4 on %ir.addr) %2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4 on %ir.addr)
$w0 = COPY %2(s32) $w0 = COPY %2(s32)
... ...
--- ---
name: atomicrmw_sub_i32 name: atomicrmw_sub_i32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: atomicrmw_sub_i32 ; CHECK-LABEL: name: atomicrmw_sub_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDADDALW [[CST]], [[COPY]] :: (load store seq_cst 4 on %ir.addr) ; CHECK: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst 4 on %ir.addr)
; CHECK: $w0 = COPY [[RES]] ; CHECK: $w0 = COPY [[LDADDALW]]
%0:gpr(p0) = COPY $x0 %0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1 %1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4 on %ir.addr) %2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4 on %ir.addr)
$w0 = COPY %2(s32) $w0 = COPY %2(s32)
... ...
--- ---
name: atomicrmw_and_i32 name: atomicrmw_and_i32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: atomicrmw_and_i32 ; CHECK-LABEL: name: atomicrmw_and_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[CST2:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[CST]] ; CHECK: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[MOVi32imm]]
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDCLRAW [[CST2]], [[COPY]] :: (load store acquire 4 on %ir.addr) ; CHECK: [[LDCLRAW:%[0-9]+]]:gpr32 = LDCLRAW [[ORNWrr]], [[COPY]] :: (load store acquire 4 on %ir.addr)
; CHECK: $w0 = COPY [[RES]] ; CHECK: $w0 = COPY [[LDCLRAW]]
%0:gpr(p0) = COPY $x0 %0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1 %1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_AND %0, %1 :: (load store acquire 4 on %ir.addr) %2:gpr(s32) = G_ATOMICRMW_AND %0, %1 :: (load store acquire 4 on %ir.addr)
$w0 = COPY %2(s32) $w0 = COPY %2(s32)
... ...
--- ---
name: atomicrmw_or_i32 name: atomicrmw_or_i32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: atomicrmw_or_i32 ; CHECK-LABEL: name: atomicrmw_or_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSETLW [[CST]], [[COPY]] :: (load store release 4 on %ir.addr) ; CHECK: [[LDSETLW:%[0-9]+]]:gpr32 = LDSETLW [[MOVi32imm]], [[COPY]] :: (load store release 4 on %ir.addr)
; CHECK: $w0 = COPY [[RES]] ; CHECK: $w0 = COPY [[LDSETLW]]
%0:gpr(p0) = COPY $x0 %0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1 %1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_OR %0, %1 :: (load store release 4 on %ir.addr) %2:gpr(s32) = G_ATOMICRMW_OR %0, %1 :: (load store release 4 on %ir.addr)
$w0 = COPY %2(s32) $w0 = COPY %2(s32)
... ...
--- ---
name: atomicrmw_xor_i32 name: atomicrmw_xor_i32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: atomicrmw_xor_i32 ; CHECK-LABEL: name: atomicrmw_xor_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDEORALW [[CST]], [[COPY]] :: (load store acq_rel 4 on %ir.addr) ; CHECK: [[LDEORALW:%[0-9]+]]:gpr32 = LDEORALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
; CHECK: $w0 = COPY [[RES]] ; CHECK: $w0 = COPY [[LDEORALW]]
%0:gpr(p0) = COPY $x0 %0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1 %1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store acq_rel 4 on %ir.addr) %2:gpr(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store acq_rel 4 on %ir.addr)
$w0 = COPY %2(s32) $w0 = COPY %2(s32)
... ...
--- ---
name: atomicrmw_min_i32 name: atomicrmw_min_i32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: atomicrmw_min_i32 ; CHECK-LABEL: name: atomicrmw_min_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSMINALW [[CST]], [[COPY]] :: (load store acq_rel 4 on %ir.addr) ; CHECK: [[LDSMINALW:%[0-9]+]]:gpr32 = LDSMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
; CHECK: $w0 = COPY [[RES]] ; CHECK: $w0 = COPY [[LDSMINALW]]
%0:gpr(p0) = COPY $x0 %0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1 %1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store acq_rel 4 on %ir.addr) %2:gpr(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store acq_rel 4 on %ir.addr)
$w0 = COPY %2(s32) $w0 = COPY %2(s32)
... ...
--- ---
name: atomicrmw_max_i32 name: atomicrmw_max_i32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: atomicrmw_max_i32 ; CHECK-LABEL: name: atomicrmw_max_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSMAXALW [[CST]], [[COPY]] :: (load store acq_rel 4 on %ir.addr) ; CHECK: [[LDSMAXALW:%[0-9]+]]:gpr32 = LDSMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
; CHECK: $w0 = COPY [[RES]] ; CHECK: $w0 = COPY [[LDSMAXALW]]
%0:gpr(p0) = COPY $x0 %0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1 %1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store acq_rel 4 on %ir.addr) %2:gpr(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store acq_rel 4 on %ir.addr)
$w0 = COPY %2(s32) $w0 = COPY %2(s32)
... ...
--- ---
name: atomicrmw_umin_i32 name: atomicrmw_umin_i32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: atomicrmw_umin_i32 ; CHECK-LABEL: name: atomicrmw_umin_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDUMINALW [[CST]], [[COPY]] :: (load store acq_rel 4 on %ir.addr) ; CHECK: [[LDUMINALW:%[0-9]+]]:gpr32 = LDUMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
; CHECK: $w0 = COPY [[RES]] ; CHECK: $w0 = COPY [[LDUMINALW]]
%0:gpr(p0) = COPY $x0 %0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1 %1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store acq_rel 4 on %ir.addr) %2:gpr(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store acq_rel 4 on %ir.addr)
$w0 = COPY %2(s32) $w0 = COPY %2(s32)
... ...
--- ---
name: atomicrmw_umax_i32 name: atomicrmw_umax_i32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: atomicrmw_umax_i32 ; CHECK-LABEL: name: atomicrmw_umax_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = LDUMAXALW [[CST]], [[COPY]] :: (load store acq_rel 4 on %ir.addr) ; CHECK: [[LDUMAXALW:%[0-9]+]]:gpr32 = LDUMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
; CHECK: $w0 = COPY [[RES]] ; CHECK: $w0 = COPY [[LDUMAXALW]]
%0:gpr(p0) = COPY $x0 %0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 1 %1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store acq_rel 4 on %ir.addr) %2:gpr(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store acq_rel 4 on %ir.addr)
$w0 = COPY %2(s32) $w0 = COPY %2(s32)
... ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-cmp.mir

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1: bb.1:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: cmp_imm_out_of_range ; CHECK-LABEL: name: cmp_imm_out_of_range
; CHECK: liveins: $x0 ; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 13132 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 13132
; CHECK: $xzr = SUBSXrr [[COPY]], [[MOVi64imm]], implicit-def $nzcv ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: $xzr = SUBSXrr [[COPY]], [[SUBREG_TO_REG]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK: $w0 = COPY [[CSINCWr]] ; CHECK: $w0 = COPY [[CSINCWr]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s64) = COPY $x0 %0:gpr(s64) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 13132 %1:gpr(s64) = G_CONSTANT i64 13132
%5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %1 %5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %1
$w0 = COPY %5(s32) $w0 = COPY %5(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir

Show All 13 Lines
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: cmpxchg_i32 ; CHECK-LABEL: name: cmpxchg_i32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CMP:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr32 = CASW [[CMP]], [[CST]], [[COPY]] :: (load store monotonic 4 on %ir.addr) ; CHECK: [[CASW:%[0-9]+]]:gpr32 = CASW [[COPY1]], [[MOVi32imm]], [[COPY]] :: (load store monotonic 4 on %ir.addr)
; CHECK: $w0 = COPY [[RES]] ; CHECK: $w0 = COPY [[CASW]]
%0:gpr(p0) = COPY $x0 %0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 0 %1:gpr(s32) = G_CONSTANT i32 0
%2:gpr(s32) = G_CONSTANT i32 1 %2:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 4 on %ir.addr) %3:gpr(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 4 on %ir.addr)
$w0 = COPY %3(s32) $w0 = COPY %3(s32)
... ...
--- ---
name: cmpxchg_i64 name: cmpxchg_i64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: cmpxchg_i64 ; CHECK-LABEL: name: cmpxchg_i64
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[CMP:%[0-9]+]]:gpr64 = COPY $xzr ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[RES:%[0-9]+]]:gpr64 = CASX [[CMP]], [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr) ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: $x0 = COPY [[RES]] ; CHECK: [[CASX:%[0-9]+]]:gpr64 = CASX [[COPY1]], [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
; CHECK: $x0 = COPY [[CASX]]
%0:gpr(p0) = COPY $x0 %0:gpr(p0) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 0 %1:gpr(s64) = G_CONSTANT i64 0
%2:gpr(s64) = G_CONSTANT i64 1 %2:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 8 on %ir.addr) %3:gpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 8 on %ir.addr)
$x0 = COPY %3(s64) $x0 = COPY %3(s64)
... ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-imm.mir

Show All 37 Lines
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
body: | body: |
bb.0: bb.0:
liveins: $w0, $w1 liveins: $w0, $w1
; CHECK-LABEL: name: imm_s64_gpr ; CHECK-LABEL: name: imm_s64_gpr
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 1234 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234
; CHECK: $x0 = COPY [[MOVi64imm]] ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
%0(s64) = G_CONSTANT i64 1234 %0(s64) = G_CONSTANT i64 1234
$x0 = COPY %0(s64) $x0 = COPY %0(s64)
... ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.1: bb.1:
liveins: $w0 liveins: $w0
; CHECK-LABEL: name: lshr_32_notimm64 ; CHECK-LABEL: name: lshr_32_notimm64
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 8 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8
; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[MOVi64imm]], 8000 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[SUBREG_TO_REG]], 8000
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32
; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]] ; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
; CHECK: $w0 = COPY [[LSRVWr]] ; CHECK: $w0 = COPY [[LSRVWr]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0 %0:gpr(s32) = COPY $w0
%3:gpr(s64) = G_CONSTANT i64 8 %3:gpr(s64) = G_CONSTANT i64 8
%4:gpr(s64) = G_AND %3, %3 %4:gpr(s64) = G_AND %3, %3
%2:gpr(s32) = G_LSHR %0, %4(s64) %2:gpr(s32) = G_LSHR %0, %4(s64)
$w0 = COPY %2(s32) $w0 = COPY %2(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
--- ---
name: ashr_32_notimm64 name: ashr_32_notimm64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.1: bb.1:
liveins: $w0 liveins: $w0
; CHECK-LABEL: name: ashr_32_notimm64 ; CHECK-LABEL: name: ashr_32_notimm64
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 8 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8
; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[MOVi64imm]], 8000 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[SUBREG_TO_REG]], 8000
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32
; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]] ; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
; CHECK: $w0 = COPY [[ASRVWr]] ; CHECK: $w0 = COPY [[ASRVWr]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0 %0:gpr(s32) = COPY $w0
%3:gpr(s64) = G_CONSTANT i64 8 %3:gpr(s64) = G_CONSTANT i64 8
%4:gpr(s64) = G_AND %3, %3 %4:gpr(s64) = G_AND %3, %3
%2:gpr(s32) = G_ASHR %0, %4(s64) %2:gpr(s32) = G_ASHR %0, %4(s64)
$w0 = COPY %2(s32) $w0 = COPY %2(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/select.mir

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
# CHECK: body: # CHECK: body:
# CHECK: %0:gpr64 = COPY $x0 # CHECK: %0:gpr64 = COPY $x0
# CHECK: %1:gpr64 = MOVi64imm 10000 # CHECK: %3:gpr32 = MOVi32imm 10000
# CHECK: %1:gpr64 = SUBREG_TO_REG 0, %3, %subreg.sub_32
# CHECK: %2:gpr64 = ADDXrr %0, %1 # CHECK: %2:gpr64 = ADDXrr %0, %1
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
%0(p0) = COPY $x0 %0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 10000 %1(s64) = G_CONSTANT i64 10000
%2(p0) = G_GEP %0, %1(s64) %2(p0) = G_GEP %0, %1(s64)
$x0 = COPY %2(p0) $x0 = COPY %2(p0)
▲ Show 20 Lines • Show All 261 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/swifterror.ll

; RUN: llc -verify-machineinstrs -frame-pointer=all -global-isel < %s -mtriple=aarch64-apple-ios -disable-post-ra | FileCheck %s ; RUN: llc -verify-machineinstrs -frame-pointer=all -global-isel < %s -mtriple=aarch64-apple-ios -disable-post-ra | FileCheck %s
declare i8* @malloc(i64) declare i8* @malloc(i64)
declare void @free(i8*) declare void @free(i8*)
%swift_error = type {i64, i8} %swift_error = type {i64, i8}
; This tests the basic usage of a swifterror parameter. "foo" is the function ; This tests the basic usage of a swifterror parameter. "foo" is the function
; that takes a swifterror parameter and "caller" is the caller of "foo". ; that takes a swifterror parameter and "caller" is the caller of "foo".
define float @foo(%swift_error** swifterror %error_ptr_ref) { define float @foo(%swift_error** swifterror %error_ptr_ref) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: mov [[ID:w[0-9]+]], #1 ; CHECK: mov [[ID:w[0-9]+]], #1
; CHECK: mov x0, #16 ; CHECK: mov w0, #16
; CHECK: malloc ; CHECK: malloc
; CHECK: strb [[ID]], [x0, #8] ; CHECK: strb [[ID]], [x0, #8]
; CHECK: mov x21, x0 ; CHECK: mov x21, x0
; CHECK-NOT: x21 ; CHECK-NOT: x21
entry: entry:
%call = call i8* @malloc(i64 16) %call = call i8* @malloc(i64 16)
%call.0 = bitcast i8* %call to %swift_error* %call.0 = bitcast i8* %call to %swift_error*
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
} }
; "foo_if" is a function that takes a swifterror parameter, it sets swifterror ; "foo_if" is a function that takes a swifterror parameter, it sets swifterror
; under a certain condition. ; under a certain condition.
define float @foo_if(%swift_error** swifterror %error_ptr_ref, i32 %cc) { define float @foo_if(%swift_error** swifterror %error_ptr_ref, i32 %cc) {
; CHECK-LABEL: foo_if: ; CHECK-LABEL: foo_if:
; CHECK: cbz w0 ; CHECK: cbz w0
; CHECK: mov [[ID:w[0-9]+]], #1 ; CHECK: mov [[ID:w[0-9]+]], #1
; CHECK: mov x0, #16 ; CHECK: mov w0, #16
; CHECK: malloc ; CHECK: malloc
; CHECK: strb [[ID]], [x0, #8] ; CHECK: strb [[ID]], [x0, #8]
; CHECK: mov x21, x0 ; CHECK: mov x21, x0
; CHECK-NOT: x21 ; CHECK-NOT: x21
; CHECK: ret ; CHECK: ret
entry: entry:
%cond = icmp ne i32 %cc, 0 %cond = icmp ne i32 %cc, 0
Show All 11 Linesnormal:
ret float 0.0 ret float 0.0
} }
; "foo_loop" is a function that takes a swifterror parameter, it sets swifterror ; "foo_loop" is a function that takes a swifterror parameter, it sets swifterror
; under a certain condition inside a loop. ; under a certain condition inside a loop.
define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float %cc2) { define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float %cc2) {
; CHECK-LABEL: foo_loop: ; CHECK-LABEL: foo_loop:
; CHECK: cbz ; CHECK: cbz
; CHECK: mov x0, #16 ; CHECK: mov w0, #16
; CHECK: malloc ; CHECK: malloc
; CHECK: mov x21, x0 ; CHECK: mov x21, x0
; CHECK: strb w{{.*}}, [x0, #8] ; CHECK: strb w{{.*}}, [x0, #8]
; CHECK: fcmp ; CHECK: fcmp
; CHECK: b.le ; CHECK: b.le
; CHECK: ret ; CHECK: ret
entry: entry:
Show All 21 Lines
%struct.S = type { i32, i32, i32, i32, i32, i32 } %struct.S = type { i32, i32, i32, i32, i32, i32 }
; "foo_sret" is a function that takes a swifterror parameter, it also has a sret ; "foo_sret" is a function that takes a swifterror parameter, it also has a sret
; parameter. ; parameter.
define void @foo_sret(%struct.S* sret %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) { define void @foo_sret(%struct.S* sret %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) {
; CHECK-LABEL: foo_sret: ; CHECK-LABEL: foo_sret:
; CHECK: mov [[SRET:x[0-9]+]], x8 ; CHECK: mov [[SRET:x[0-9]+]], x8
; CHECK: mov [[ID:w[0-9]+]], #1 ; CHECK: mov [[ID:w[0-9]+]], #1
; CHECK: mov x0, #16 ; CHECK: mov w0, #16
; CHECK: malloc ; CHECK: malloc
; CHECK: strb [[ID]], [x0, #8] ; CHECK: strb [[ID]], [x0, #8]
; CHECK: str w{{.*}}, [{{.*}}[[SRET]], #4] ; CHECK: str w{{.*}}, [{{.*}}[[SRET]], #4]
; CHECK: mov x21, x0 ; CHECK: mov x21, x0
; CHECK-NOT: x21 ; CHECK-NOT: x21
entry: entry:
%call = call i8* @malloc(i64 16) %call = call i8* @malloc(i64 16)
Show All 39 Lines
} }
; "foo_vararg" is a function that takes a swifterror parameter, it also has ; "foo_vararg" is a function that takes a swifterror parameter, it also has
; variable number of arguments. ; variable number of arguments.
declare void @llvm.va_start(i8*) nounwind declare void @llvm.va_start(i8*) nounwind
define float @foo_vararg(%swift_error** swifterror %error_ptr_ref, ...) { define float @foo_vararg(%swift_error** swifterror %error_ptr_ref, ...) {
; CHECK-LABEL: foo_vararg: ; CHECK-LABEL: foo_vararg:
; CHECK-DAG: mov [[ID:w[0-9]+]], #1 ; CHECK-DAG: mov [[ID:w[0-9]+]], #1
; CHECK: mov x0, #16 ; CHECK: mov w0, #16
; CHECK: malloc ; CHECK: malloc
; CHECK-DAG: strb [[ID]], [x0, #8] ; CHECK-DAG: strb [[ID]], [x0, #8]
; First vararg ; First vararg
; CHECK: ldr {{w[0-9]+}}, [x[[ARG1:[0-9]+]]], #8 ; CHECK: ldr {{w[0-9]+}}, [x[[ARG1:[0-9]+]]], #8
; Second vararg ; Second vararg
; CHECK: ldr {{w[0-9]+}}, [x[[ARG1]]], #8 ; CHECK: ldr {{w[0-9]+}}, [x[[ARG1]]], #8
; Third vararg ; Third vararg
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; CHECK: mov x22, x2 ; CHECK: mov x22, x2
; CHECK: mov x23, x3 ; CHECK: mov x23, x3
; CHECK: mov x24, x4 ; CHECK: mov x24, x4
; CHECK: mov x25, x5 ; CHECK: mov x25, x5
; CHECK: mov x26, x6 ; CHECK: mov x26, x6
; CHECK: mov x27, x7 ; CHECK: mov x27, x7
; CHECK: mov x28, x21 ; CHECK: mov x28, x21
; Setup call. ; Setup call.
; CHECK: mov x0, #1 ; CHECK: mov w0, #1
; CHECK: mov x1, #2 ; CHECK: mov w1, #2
; CHECK: mov x2, #3 ; CHECK: mov w2, #3
; CHECK: mov x3, #4 ; CHECK: mov w3, #4
; CHECK: mov x4, #5 ; CHECK: mov w4, #5
; CHECK: mov x5, #6 ; CHECK: mov w5, #6
; CHECK: mov x6, #7 ; CHECK: mov w6, #7
; CHECK: mov x7, #8 ; CHECK: mov w7, #8
; CHECK: str xzr, [sp] ; CHECK: str xzr, [sp]
; CHECK: mov x21, xzr ; CHECK: mov x21, xzr
; CHECK: bl _params_in_reg2 ; CHECK: bl _params_in_reg2
; Restore original arguments for next call. ; Restore original arguments for next call.
; CHECK: ldr x0, [sp ; CHECK: ldr x0, [sp
; CHECK: mov x1, x20 ; CHECK: mov x1, x20
; CHECK: mov x2, x22 ; CHECK: mov x2, x22
; CHECK: mov x3, x23 ; CHECK: mov x3, x23
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; CHECK: mov x22, x2 ; CHECK: mov x22, x2
; CHECK: mov x23, x3 ; CHECK: mov x23, x3
; CHECK: mov x24, x4 ; CHECK: mov x24, x4
; CHECK: mov x25, x5 ; CHECK: mov x25, x5
; CHECK: mov x26, x6 ; CHECK: mov x26, x6
; CHECK: mov x27, x7 ; CHECK: mov x27, x7
; CHECK: mov x28, x21 ; CHECK: mov x28, x21
; Setup call arguments. ; Setup call arguments.
; CHECK: mov x0, #1 ; CHECK: mov w0, #1
; CHECK: mov x1, #2 ; CHECK: mov w1, #2
; CHECK: mov x2, #3 ; CHECK: mov w2, #3
; CHECK: mov x3, #4 ; CHECK: mov w3, #4
; CHECK: mov x4, #5 ; CHECK: mov w4, #5
; CHECK: mov x5, #6 ; CHECK: mov w5, #6
; CHECK: mov x6, #7 ; CHECK: mov w6, #7
; CHECK: mov x7, #8 ; CHECK: mov w7, #8
; CHECK: mov x21, xzr ; CHECK: mov x21, xzr
; CHECK: bl _params_in_reg2 ; CHECK: bl _params_in_reg2
; Store swifterror %error_ptr_ref. ; Store swifterror %error_ptr_ref.
; CHECK: stp {{x[0-9]+}}, x21, [sp] ; CHECK: stp {{x[0-9]+}}, x21, [sp]
; Setup call arguments from original arguments. ; Setup call arguments from original arguments.
; CHECK: ldr x0, [sp, #24 ; CHECK: ldr x0, [sp, #24
; CHECK: mov x1, x20 ; CHECK: mov x1, x20
; CHECK: mov x2, x22 ; CHECK: mov x2, x22
Show All 11 Lines
; CHECK: mov x24, x3 ; CHECK: mov x24, x3
; CHECK: mov x25, x4 ; CHECK: mov x25, x4
; CHECK: mov x26, x5 ; CHECK: mov x26, x5
; CHECK: mov x27, x6 ; CHECK: mov x27, x6
; CHECK: mov x28, x7 ; CHECK: mov x28, x7
; Save swifterror %err. ; Save swifterror %err.
; CHECK: mov x19, x21 ; CHECK: mov x19, x21
; Setup call. ; Setup call.
; CHECK: mov x0, #1 ; CHECK: mov w0, #1
; CHECK: mov x1, #2 ; CHECK: mov w1, #2
; CHECK: mov x2, #3 ; CHECK: mov w2, #3
; CHECK: mov x3, #4 ; CHECK: mov w3, #4
; CHECK: mov x4, #5 ; CHECK: mov w4, #5
; CHECK: mov x5, #6 ; CHECK: mov w5, #6
; CHECK: mov x6, #7 ; CHECK: mov w6, #7
; CHECK: mov x7, #8 ; CHECK: mov w7, #8
; ... setup call with swiferror %error_ptr_ref. ; ... setup call with swiferror %error_ptr_ref.
; CHECK: ldr x21, [sp, #8] ; CHECK: ldr x21, [sp, #8]
; CHECK: bl _params_in_reg2 ; CHECK: bl _params_in_reg2
; Restore return values for return from this function. ; Restore return values for return from this function.
; CHECK: mov x0, x20 ; CHECK: mov x0, x20
; CHECK: mov x1, x22 ; CHECK: mov x1, x22
; CHECK: mov x2, x23 ; CHECK: mov x2, x23
; CHECK: mov x3, x24 ; CHECK: mov x3, x24
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll

; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
@sortlist = common global [5001 x i32] zeroinitializer, align 16 @sortlist = common global [5001 x i32] zeroinitializer, align 16
@sortlist2 = common global [5001 x i64] zeroinitializer, align 16 @sortlist2 = common global [5001 x i64] zeroinitializer, align 16
; Load an address with an offset larget then LDR imm can handle ; Load an address with an offset larget then LDR imm can handle
define i32 @foo() nounwind { define i32 @foo() nounwind {
entry: entry:
; CHECK-LABEL: @foo ; CHECK-LABEL: @foo
Show All 38 Lines

llvm/trunk/test/CodeGen/X86/GlobalISel/add-ext.ll

Show First 20 Lines • Show All 196 Lines • ▼ Show 20 Lines
} }
; The same as @PR20134 but sign extension is replaced with zero extension ; The same as @PR20134 but sign extension is replaced with zero extension
define void @PR20134_zext(i32* %a, i32 %i) { define void @PR20134_zext(i32* %a, i32 %i) {
; CHECK-LABEL: PR20134_zext: ; CHECK-LABEL: PR20134_zext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $esi killed $esi def $rsi ; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-NEXT: leal 1(%rsi), %eax ; CHECK-NEXT: leal 1(%rsi), %eax
; CHECK-NEXT: movl %eax, %eax
; CHECK-NEXT: movq $4, %rcx ; CHECK-NEXT: movq $4, %rcx
; CHECK-NEXT: imulq %rcx, %rax ; CHECK-NEXT: imulq %rcx, %rax
; CHECK-NEXT: addq %rdi, %rax ; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: leal 2(%rsi), %edx ; CHECK-NEXT: leal 2(%rsi), %edx
; CHECK-NEXT: movl %edx, %edx
; CHECK-NEXT: imulq %rcx, %rdx ; CHECK-NEXT: imulq %rcx, %rdx
; CHECK-NEXT: addq %rdi, %rdx ; CHECK-NEXT: addq %rdi, %rdx
; CHECK-NEXT: movl (%rdx), %edx ; CHECK-NEXT: movl (%rdx), %edx
; CHECK-NEXT: addl (%rax), %edx ; CHECK-NEXT: addl (%rax), %edx
; CHECK-NEXT: imulq %rcx, %rsi ; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: leaq (%rdi,%rsi), %rax ; CHECK-NEXT: imulq %rcx, %rax
; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: movl %edx, (%rax) ; CHECK-NEXT: movl %edx, (%rax)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%add1 = add nuw i32 %i, 1 %add1 = add nuw i32 %i, 1
%idx1 = zext i32 %add1 to i64 %idx1 = zext i32 %add1 to i64
%gep1 = getelementptr i32, i32* %a, i64 %idx1 %gep1 = getelementptr i32, i32* %a, i64 %idx1
%load1 = load i32, i32* %gep1, align 4 %load1 = load i32, i32* %gep1, align 4
Show All 11 Lines

llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Linesregisters:
- { id: 2, class: gpr } - { id: 2, class: gpr }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $edi liveins: $edi
; ALL-LABEL: name: anyext_s64_from_s8 ; ALL-LABEL: name: anyext_s64_from_s8
; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit ; ALL: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOVZX32rr8_]], %subreg.sub_32bit
; ALL: $rax = COPY [[SUBREG_TO_REG]] ; ALL: $rax = COPY [[SUBREG_TO_REG]]
; ALL: RET 0, implicit $rax ; ALL: RET 0, implicit $rax
%0(s64) = COPY $rdi %0(s64) = COPY $rdi
%1(s8) = G_TRUNC %0(s64) %1(s8) = G_TRUNC %0(s64)
%2(s64) = G_ANYEXT %1(s8) %2(s64) = G_ANYEXT %1(s8)
$rax = COPY %2(s64) $rax = COPY %2(s64)
RET 0, implicit $rax RET 0, implicit $rax
... ...
--- ---
name: anyext_s64_from_s16 name: anyext_s64_from_s16
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $edi liveins: $edi
; ALL-LABEL: name: anyext_s64_from_s16 ; ALL-LABEL: name: anyext_s64_from_s16
; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_16bit ; ALL: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]]
; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOVZX32rr16_]], %subreg.sub_32bit
; ALL: $rax = COPY [[SUBREG_TO_REG]] ; ALL: $rax = COPY [[SUBREG_TO_REG]]
; ALL: RET 0, implicit $rax ; ALL: RET 0, implicit $rax
%0(s64) = COPY $rdi %0(s64) = COPY $rdi
%1(s16) = G_TRUNC %0(s64) %1(s16) = G_TRUNC %0(s64)
%2(s64) = G_ANYEXT %1(s16) %2(s64) = G_ANYEXT %1(s16)
$rax = COPY %2(s64) $rax = COPY %2(s64)
RET 0, implicit $rax RET 0, implicit $rax
... ...
Show All 26 Lines

llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir

Show First 20 Lines • Show All 345 Lines • ▼ Show 20 Linesregisters:
- { id: 1, class: gpr } - { id: 1, class: gpr }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $edi liveins: $edi
; CHECK-LABEL: name: zext_i32_to_i64 ; CHECK-LABEL: name: zext_i32_to_i64
; CHECK: liveins: $edi ; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32bit ; CHECK: [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY]]
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32rr]], %subreg.sub_32bit
; CHECK: $rax = COPY [[SUBREG_TO_REG]] ; CHECK: $rax = COPY [[SUBREG_TO_REG]]
; CHECK: RET 0, implicit $rax ; CHECK: RET 0, implicit $rax
%0:gpr(s32) = COPY $edi %0:gpr(s32) = COPY $edi
%1:gpr(s64) = G_ZEXT %0(s32) %1:gpr(s64) = G_ZEXT %0(s32)
$rax = COPY %1(s64) $rax = COPY %1(s64)
RET 0, implicit $rax RET 0, implicit $rax
... ...

llvm/trunk/test/TableGen/GlobalISelEmitterSubreg.td

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/1, // CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/1,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DRegs*/1, // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DRegs*/1,
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC DRegs*/1, // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC DRegs*/1,
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC SRegs*/0, // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC SRegs*/0,
// Test that we can import SUBREG_TO_REG
def : Pat<(i32 (zext SOP:$src)),
(SUBREG_TO_REG (i64 0), (SUBSOME_INSN SOP:$src), sub0)>;
// CHECK-LABEL: (zext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (SUBREG_TO_REG:{ *:[i32] } 0:{ *:[i64] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] })
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/MyTarget::SUBSOME_INSN,
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0,
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/1,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DRegs*/1,
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC SRegs*/0,

llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp

Show First 20 Lines • Show All 3,163 Lines • ▼ Show 20 Linesprivate:
MatchTable buildMatchTable(MutableArrayRef<RuleMatcher> Rules, bool Optimize, MatchTable buildMatchTable(MutableArrayRef<RuleMatcher> Rules, bool Optimize,
bool WithCoverage); bool WithCoverage);
/// Infer a CodeGenRegisterClass for the type of \p SuperRegNode. The returned /// Infer a CodeGenRegisterClass for the type of \p SuperRegNode. The returned
/// CodeGenRegisterClass will support the CodeGenRegisterClass of /// CodeGenRegisterClass will support the CodeGenRegisterClass of
/// \p SubRegNode, and the subregister index defined by \p SubRegIdxNode. /// \p SubRegNode, and the subregister index defined by \p SubRegIdxNode.
/// If no register class is found, return None. /// If no register class is found, return None.
Optional<const CodeGenRegisterClass *> Optional<const CodeGenRegisterClass *>
inferSuperRegisterClass(const TypeSetByHwMode &Ty, inferSuperRegisterClassForNode(const TypeSetByHwMode &Ty,
TreePatternNode *SuperRegNode, TreePatternNode *SuperRegNode,
TreePatternNode *SubRegIdxNode); TreePatternNode *SubRegIdxNode);
/// Infer a CodeGenRegisterClass which suppoorts \p Ty and \p SubRegIdxNode.
/// Return None if no such class exists.
Optional<const CodeGenRegisterClass *>
inferSuperRegisterClass(const TypeSetByHwMode &Ty,
TreePatternNode *SubRegIdxNode);
/// Return the CodeGenRegisterClass associated with \p Leaf if it has one. /// Return the CodeGenRegisterClass associated with \p Leaf if it has one.
Optional<const CodeGenRegisterClass *> Optional<const CodeGenRegisterClass *>
getRegClassFromLeaf(TreePatternNode *Leaf); getRegClassFromLeaf(TreePatternNode *Leaf);
/// Return a CodeGenRegisterClass for \p N if one can be found. Return None /// Return a CodeGenRegisterClass for \p N if one can be found. Return None
/// otherwise. /// otherwise.
Optional<const CodeGenRegisterClass *> Optional<const CodeGenRegisterClass *>
inferRegClassFromPattern(TreePatternNode *N); inferRegClassFromPattern(TreePatternNode *N);
▲ Show 20 Lines • Show All 675 Lines • ▼ Show 20 LinesGlobalISelEmitter::createAndImportSubInstructionRenderer(
// subinstruction that it ends up being constrained to the correct super // subinstruction that it ends up being constrained to the correct super
// register and subregister classes. // register and subregister classes.
if (Target.getInstruction(Dst->getOperator()).TheDef->getName() == if (Target.getInstruction(Dst->getOperator()).TheDef->getName() ==
"INSERT_SUBREG") { "INSERT_SUBREG") {
auto SubClass = inferRegClassFromPattern(Dst->getChild(1)); auto SubClass = inferRegClassFromPattern(Dst->getChild(1));
if (!SubClass) if (!SubClass)
return failedImport( return failedImport(
"Cannot infer register class from INSERT_SUBREG operand #1"); "Cannot infer register class from INSERT_SUBREG operand #1");
Optional<const CodeGenRegisterClass *> SuperClass = inferSuperRegisterClass( Optional<const CodeGenRegisterClass *> SuperClass =
Dst->getExtType(0), Dst->getChild(0), Dst->getChild(2)); inferSuperRegisterClassForNode(Dst->getExtType(0), Dst->getChild(0),
Dst->getChild(2));
if (!SuperClass) if (!SuperClass)
return failedImport( return failedImport(
"Cannot infer register class for INSERT_SUBREG operand #0"); "Cannot infer register class for INSERT_SUBREG operand #0");
// The destination and the super register source of an INSERT_SUBREG must // The destination and the super register source of an INSERT_SUBREG must
// be the same register class. // be the same register class.
M.insertAction<ConstrainOperandToRegClassAction>( M.insertAction<ConstrainOperandToRegClassAction>(
InsertPt, DstMIBuilder.getInsnID(), 0, **SuperClass); InsertPt, DstMIBuilder.getInsnID(), 0, **SuperClass);
M.insertAction<ConstrainOperandToRegClassAction>( M.insertAction<ConstrainOperandToRegClassAction>(
InsertPt, DstMIBuilder.getInsnID(), 1, **SuperClass); InsertPt, DstMIBuilder.getInsnID(), 1, **SuperClass);
M.insertAction<ConstrainOperandToRegClassAction>( M.insertAction<ConstrainOperandToRegClassAction>(
InsertPt, DstMIBuilder.getInsnID(), 2, **SubClass); InsertPt, DstMIBuilder.getInsnID(), 2, **SubClass);
return InsertPtOrError.get(); return InsertPtOrError.get();
} }
// Similar to INSERT_SUBREG, we also have to handle SUBREG_TO_REG as a
// subinstruction.
if (Target.getInstruction(Dst->getOperator()).TheDef->getName() ==
"SUBREG_TO_REG") {
auto SubClass = inferRegClassFromPattern(Dst->getChild(1));
if (!SubClass)
return failedImport(
"Cannot infer register class from SUBREG_TO_REG child #1");
auto SuperClass = inferSuperRegisterClass(Dst->getExtType(0),
Dst->getChild(2));
if (!SuperClass)
return failedImport(
"Cannot infer register class for SUBREG_TO_REG operand #0");
M.insertAction<ConstrainOperandToRegClassAction>(
InsertPt, DstMIBuilder.getInsnID(), 0, **SuperClass);
M.insertAction<ConstrainOperandToRegClassAction>(
InsertPt, DstMIBuilder.getInsnID(), 2, **SubClass);
return InsertPtOrError.get();
}
M.insertAction<ConstrainOperandsToDefinitionAction>(InsertPt, M.insertAction<ConstrainOperandsToDefinitionAction>(InsertPt,
DstMIBuilder.getInsnID()); DstMIBuilder.getInsnID());
return InsertPtOrError.get(); return InsertPtOrError.get();
} }
Expected<action_iterator> GlobalISelEmitter::createInstructionRenderer( Expected<action_iterator> GlobalISelEmitter::createInstructionRenderer(
action_iterator InsertPt, RuleMatcher &M, const TreePatternNode *Dst) { action_iterator InsertPt, RuleMatcher &M, const TreePatternNode *Dst) {
Record *DstOp = Dst->getOperator(); Record *DstOp = Dst->getOperator();
▲ Show 20 Lines • Show All 232 Lines • ▼ Show 20 Lines if (DstIOpRec->isSubClassOf("RegisterClass")) {
return &RC; return &RC;
} }
return None; return None;
} }
Optional<const CodeGenRegisterClass *> Optional<const CodeGenRegisterClass *>
GlobalISelEmitter::inferSuperRegisterClass(const TypeSetByHwMode &Ty, GlobalISelEmitter::inferSuperRegisterClass(const TypeSetByHwMode &Ty,
TreePatternNode *SuperRegNode,
TreePatternNode *SubRegIdxNode) { TreePatternNode *SubRegIdxNode) {
// Check if we already have a defined register class for the super register assert(SubRegIdxNode && "Expected subregister index node!");
// node. If we do, then we should preserve that rather than inferring anything
// from the subregister index node. We can assume that whoever wrote the
// pattern in the first place made sure that the super register and
// subregister are compatible.
if (Optional<const CodeGenRegisterClass *> SuperRegisterClass =
inferRegClassFromPattern(SuperRegNode))
return SuperRegisterClass;
// We need a ValueTypeByHwMode for getSuperRegForSubReg. // We need a ValueTypeByHwMode for getSuperRegForSubReg.
if (!Ty.isValueTypeByHwMode(false)) if (!Ty.isValueTypeByHwMode(false))
return None; return None;
// We don't know anything about the super register. Try to use the subregister
// index to infer an appropriate register class.
if (!SubRegIdxNode->isLeaf()) if (!SubRegIdxNode->isLeaf())
return None; return None;
DefInit *SubRegInit = dyn_cast<DefInit>(SubRegIdxNode->getLeafValue()); DefInit *SubRegInit = dyn_cast<DefInit>(SubRegIdxNode->getLeafValue());
if (!SubRegInit) if (!SubRegInit)
return None; return None;
CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef());
// Use the information we found above to find a minimal register class which // Use the information we found above to find a minimal register class which
// supports the subregister and type we want. // supports the subregister and type we want.
auto RC = auto RC =
Target.getSuperRegForSubReg(Ty.getValueTypeByHwMode(), CGRegs, SubIdx); Target.getSuperRegForSubReg(Ty.getValueTypeByHwMode(), CGRegs, SubIdx);
if (!RC) if (!RC)
return None; return None;
return *RC; return *RC;
} }
Optional<const CodeGenRegisterClass *>
GlobalISelEmitter::inferSuperRegisterClassForNode(
const TypeSetByHwMode &Ty, TreePatternNode *SuperRegNode,
TreePatternNode *SubRegIdxNode) {
assert(SuperRegNode && "Expected super register node!");
// Check if we already have a defined register class for the super register
// node. If we do, then we should preserve that rather than inferring anything
// from the subregister index node. We can assume that whoever wrote the
// pattern in the first place made sure that the super register and
// subregister are compatible.
if (Optional<const CodeGenRegisterClass *> SuperRegisterClass =
inferRegClassFromPattern(SuperRegNode))
return *SuperRegisterClass;
return inferSuperRegisterClass(Ty, SubRegIdxNode);
}
Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) { Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
// Keep track of the matchers and actions to emit. // Keep track of the matchers and actions to emit.
int Score = P.getPatternComplexity(CGP); int Score = P.getPatternComplexity(CGP);
RuleMatcher M(P.getSrcRecord()->getLoc()); RuleMatcher M(P.getSrcRecord()->getLoc());
RuleMatcherScores[M.getRuleID()] = Score; RuleMatcherScores[M.getRuleID()] = Score;
M.addAction<DebugCommentAction>(llvm::to_string(*P.getSrcPattern()) + M.addAction<DebugCommentAction>(llvm::to_string(*P.getSrcPattern()) +
" => " + " => " +
llvm::to_string(*P.getDstPattern())); llvm::to_string(*P.getDstPattern()));
▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 Lines if (DstI.TheDef->getName() == "COPY_TO_REGCLASS") {
// We can assume that a subregister is in the same bank as it's super // We can assume that a subregister is in the same bank as it's super
// register. // register.
DstIOpRec = getInitValueAsRegClass(Dst->getChild(0)->getLeafValue()); DstIOpRec = getInitValueAsRegClass(Dst->getChild(0)->getLeafValue());
if (DstIOpRec == nullptr) if (DstIOpRec == nullptr)
return failedImport("EXTRACT_SUBREG operand #0 isn't a register class"); return failedImport("EXTRACT_SUBREG operand #0 isn't a register class");
} else if (DstI.TheDef->getName() == "INSERT_SUBREG") { } else if (DstI.TheDef->getName() == "INSERT_SUBREG") {
auto MaybeSuperClass = auto MaybeSuperClass = inferSuperRegisterClassForNode(
inferSuperRegisterClass(VTy, Dst->getChild(0), Dst->getChild(2)); VTy, Dst->getChild(0), Dst->getChild(2));
if (!MaybeSuperClass) if (!MaybeSuperClass)
return failedImport( return failedImport(
"Cannot infer register class for INSERT_SUBREG operand #0"); "Cannot infer register class for INSERT_SUBREG operand #0");
// Move to the next pattern here, because the register class we found // Move to the next pattern here, because the register class we found
// doesn't necessarily have a record associated with it. So, we can't // doesn't necessarily have a record associated with it. So, we can't
// set DstIOpRec using this. // set DstIOpRec using this.
OperandMatcher &OM = InsnMatcher.getOperand(OpIdx); OperandMatcher &OM = InsnMatcher.getOperand(OpIdx);
OM.setSymbolicName(DstIOperand.Name); OM.setSymbolicName(DstIOperand.Name);
M.defineOperand(OM.getSymbolicName(), OM); M.defineOperand(OM.getSymbolicName(), OM);
OM.addPredicate<RegisterBankOperandMatcher>(**MaybeSuperClass); OM.addPredicate<RegisterBankOperandMatcher>(**MaybeSuperClass);
++OpIdx; ++OpIdx;
continue; continue;
} else if (DstI.TheDef->getName() == "SUBREG_TO_REG") {
auto MaybeRegClass = inferSuperRegisterClass(VTy, Dst->getChild(2));
if (!MaybeRegClass)
return failedImport(
"Cannot infer register class for SUBREG_TO_REG operand #0");
OperandMatcher &OM = InsnMatcher.getOperand(OpIdx);
OM.setSymbolicName(DstIOperand.Name);
M.defineOperand(OM.getSymbolicName(), OM);
OM.addPredicate<RegisterBankOperandMatcher>(**MaybeRegClass);
++OpIdx;
continue;
} else if (DstIOpRec->isSubClassOf("RegisterOperand")) } else if (DstIOpRec->isSubClassOf("RegisterOperand"))
DstIOpRec = DstIOpRec->getValueAsDef("RegClass"); DstIOpRec = DstIOpRec->getValueAsDef("RegClass");
else if (!DstIOpRec->isSubClassOf("RegisterClass")) else if (!DstIOpRec->isSubClassOf("RegisterClass"))
return failedImport("Dst MI def isn't a register class" + return failedImport("Dst MI def isn't a register class" +
to_string(*Dst)); to_string(*Dst));
OperandMatcher &OM = InsnMatcher.getOperand(OpIdx); OperandMatcher &OM = InsnMatcher.getOperand(OpIdx);
OM.setSymbolicName(DstIOperand.Name); OM.setSymbolicName(DstIOperand.Name);
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines if (DstI.TheDef->getName() == "INSERT_SUBREG") {
assert(Src->getExtTypes().size() == 1 && assert(Src->getExtTypes().size() == 1 &&
"Expected Src of INSERT_SUBREG to have one result type"); "Expected Src of INSERT_SUBREG to have one result type");
// We need to constrain the destination, a super regsister source, and a // We need to constrain the destination, a super regsister source, and a
// subregister source. // subregister source.
auto SubClass = inferRegClassFromPattern(Dst->getChild(1)); auto SubClass = inferRegClassFromPattern(Dst->getChild(1));
if (!SubClass) if (!SubClass)
return failedImport( return failedImport(
"Cannot infer register class from INSERT_SUBREG operand #1"); "Cannot infer register class from INSERT_SUBREG operand #1");
auto SuperClass = inferSuperRegisterClass( auto SuperClass = inferSuperRegisterClassForNode(
Src->getExtType(0), Dst->getChild(0), Dst->getChild(2)); Src->getExtType(0), Dst->getChild(0), Dst->getChild(2));
if (!SuperClass) if (!SuperClass)
return failedImport( return failedImport(
"Cannot infer register class for INSERT_SUBREG operand #0"); "Cannot infer register class for INSERT_SUBREG operand #0");
M.addAction<ConstrainOperandToRegClassAction>(0, 0, **SuperClass); M.addAction<ConstrainOperandToRegClassAction>(0, 0, **SuperClass);
M.addAction<ConstrainOperandToRegClassAction>(0, 1, **SuperClass); M.addAction<ConstrainOperandToRegClassAction>(0, 1, **SuperClass);
M.addAction<ConstrainOperandToRegClassAction>(0, 2, **SubClass); M.addAction<ConstrainOperandToRegClassAction>(0, 2, **SubClass);
++NumPatternImported; ++NumPatternImported;
return std::move(M); return std::move(M);
} }
if (DstI.TheDef->getName() == "SUBREG_TO_REG") {
// We need to constrain the destination and subregister source.
assert(Src->getExtTypes().size() == 1 &&
"Expected Src of SUBREG_TO_REG to have one result type");
// Attempt to infer the subregister source from the first child. If it has
// an explicitly given register class, we'll use that. Otherwise, we will
// fail.
auto SubClass = inferRegClassFromPattern(Dst->getChild(1));
if (!SubClass)
return failedImport(
"Cannot infer register class from SUBREG_TO_REG child #1");
// We don't have a child to look at that might have a super register node.
auto SuperClass =
inferSuperRegisterClass(Src->getExtType(0), Dst->getChild(2));
if (!SuperClass)
return failedImport(
"Cannot infer register class for SUBREG_TO_REG operand #0");
M.addAction<ConstrainOperandToRegClassAction>(0, 0, **SuperClass);
M.addAction<ConstrainOperandToRegClassAction>(0, 2, **SubClass);
++NumPatternImported;
return std::move(M);
}
M.addAction<ConstrainOperandsToDefinitionAction>(0); M.addAction<ConstrainOperandsToDefinitionAction>(0);
// We're done with this pattern! It's eligible for GISel emission; return it. // We're done with this pattern! It's eligible for GISel emission; return it.
++NumPatternImported; ++NumPatternImported;
return std::move(M); return std::move(M);
} }
// Emit imm predicate table and an enum to reference them with. // Emit imm predicate table and an enum to reference them with.
▲ Show 20 Lines • Show All 813 Lines • Show Last 20 Lines