DAG: computeNumSignBits for MUL

[arsenm]

Summary

Copied directly from the IR version.

Most of the testcases I've added for this are somewhat problematic
because they really end up testing the yet to be implemented version
for MUL_I24/MUL_U24.

[lebedev.ri]

LG as a copy-paste from lib/Analysis/ValueTracking.cpp ComputeNumSignBitsImpl().

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

3723

1 is a magic 'i-dont-know', right? I wonder why it's not -1,
that one you certainly can't ever get normally, unlike 1 (INT_MIN)
(Well, yeah, or Optional<unsigned>)

[arsenm]

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

3723

There is always the sign bit itself, so any uses should naturally do the right thing from that.

[bjope]

Not sure if we need it for this patch, but I remember that last time I did something with computeNumSignBits in SelectionDAG I was informed that it is possible to add unittests in llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp. In case you for example want to make more detailed tests.

[RKSimon]

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

3719

Can't we just use the VTBits variable? Also, getValueSizeInBits only works on scalar types.

[arsenm]

Use VTBits

[lebedev.ri]

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

3719

Whoops, i thought i reviewed that bit, but looks like i looked at this line in next case.

[RKSimon]

LGTM - cheers

[arsenm]

r370099

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

if (ConstantSDNode *CLHS = isConstOrConstSplat(Op.getOperand(0)))
         // Otherwise, we treat this like a SUB.
       }
 
     // Sub can have at most one carry bit.  Thus we know that the output
     // is, at worst, one more bit than the inputs.
     Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
     if (Tmp == 1) return 1;  // Early out.
     return std::min(Tmp, Tmp2)-1;
+  case ISD::MUL: {
+    // The output of the Mul can be at most twice the valid bits in the inputs.
+    unsigned SignBitsOp0 = ComputeNumSignBits(Op.getOperand(0), Depth + 1);
+    if (SignBitsOp0 == 1)
+      break;
+    unsigned SignBitsOp1 = ComputeNumSignBits(Op.getOperand(1), Depth + 1);
+    if (SignBitsOp1 == 1)
+      break;
+    unsigned OutValidBits =
+        (VTBits - SignBitsOp0 + 1) + (VTBits - SignBitsOp1 + 1);
+    return OutValidBits > VTBits ? 1 : VTBits - OutValidBits + 1;
+  }
   case ISD::TRUNCATE: {
     // Check if the sign bits of source go down as far as the truncated value.
     unsigned NumSrcBits = Op.getOperand(0).getScalarValueSizeInBits();
     unsigned NumSrcSignBits = ComputeNumSignBits(Op.getOperand(0), Depth + 1);
     if (NumSrcSignBits > (NumSrcBits - VTBits))
       return NumSrcSignBits - (NumSrcBits - VTBits);
     break;
   }

test/CodeGen/AMDGPU/computeNumSignBits-mul.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - -amdgpu-codegenprepare-mul24=0 < %s | FileCheck -check-prefix=GFX9 %s
 
 define i16 @num_sign_bits_mul_i48_0(i8 %X, i8 %Y, i8 %Z, i8 %W) {
 ; GFX9-LABEL: num_sign_bits_mul_i48_0:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_mul_i32_i24_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
 ; GFX9-NEXT:    v_mul_i32_i24_sdwa v1, sext(v2), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-NEXT:    v_mul_lo_u32 v0, v0, v1
+; GFX9-NEXT:    v_mul_i32_i24_e32 v0, v0, v1
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
   %A = sext i8 %X to i48
   %B = sext i8 %Y to i48
   %C = sext i8 %Z to i48
   %D = sext i8 %W to i48
   %mul0 = mul i48 %A, %B
   %mul1 = mul i48 %C, %D
   %mul2 = mul i48 %mul0, %mul1
   %trunc = trunc i48 %mul2 to i16
   ret i16 %trunc
 }
 
 define i16 @num_sign_bits_mul_i48_1(i8 %X, i8 %Y, i8 %Z, i8 %W) {
 ; GFX9-LABEL: num_sign_bits_mul_i48_1:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX9-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX9-NEXT:    v_mul_hi_i32_i24_e32 v4, v0, v1
-; GFX9-NEXT:    v_mul_i32_i24_e32 v0, v0, v1
-; GFX9-NEXT:    v_bfe_i32 v1, v3, 0, 8
-; GFX9-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX9-NEXT:    v_mul_hi_i32_i24_e32 v3, v2, v1
-; GFX9-NEXT:    v_mul_i32_i24_e32 v1, v2, v1
-; GFX9-NEXT:    v_mul_lo_u32 v2, v4, v1
-; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v1
-; GFX9-NEXT:    v_mul_lo_u32 v0, v0, v1
-; GFX9-NEXT:    v_add3_u32 v1, v4, v3, v2
+; GFX9-NEXT:    v_mul_i32_i24_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-NEXT:    v_mul_i32_i24_sdwa v2, sext(v2), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-NEXT:    v_mul_hi_i32_i24_e32 v1, v0, v2
+; GFX9-NEXT:    v_mul_i32_i24_e32 v0, v0, v2
 ; GFX9-NEXT:    v_lshrrev_b64 v[0:1], 24, v[0:1]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
   %A = sext i8 %X to i48
   %B = sext i8 %Y to i48
   %C = sext i8 %Z to i48
   %D = sext i8 %W to i48
   %mul0 = mul i48 %A, %B
   %mul1 = mul i48 %C, %D