[RISCV] Fix ICE in isDesirableToCommuteWithShift

[lenary]

Summary

Ana Pazos reported a bug where we were not checking that an APInt would
fit into 64-bits before calling getSExtValue(). This caused asserts when
compiling large constants, such as i128s, as happens when compiling compiler-rt.

This patch adds a testcase and makes the callback less error-prone.

[lenary]

Note: this should be backported to 9.0 when it lands.

[lenary]

• Update check to match assert in APInt::getSExtValue()

[luismarques]

LGTM.

[lenary]

@hans Please may you backport this to the 9.0 release branch?

[apazos]

Thanks Sam, LGTM.

[hans]

In D66081#1625195, @lenary wrote:

@hans Please may you backport this to the 9.0 release branch?

Merged in r368674.

llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp

if (Ty.isScalarInteger() &&
     auto *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1));
     if (C1 && C2) {
       APInt C1Int = C1->getAPIntValue();
       APInt ShiftedC1Int = C1Int << C2->getAPIntValue();
 
       // We can materialise `c1 << c2` into an add immediate, so it's "free",
       // and the combine should happen, to potentially allow further combines
       // later.
-      if (isLegalAddImmediate(ShiftedC1Int.getSExtValue()))
+      if (ShiftedC1Int.getMinSignedBits() <= 64 &&
+          isLegalAddImmediate(ShiftedC1Int.getSExtValue()))
         return true;
 
       // We can materialise `c1` in an add immediate, so it's "free", and the
       // combine should be prevented.
-      if (isLegalAddImmediate(C1Int.getSExtValue()))
+      if (C1Int.getMinSignedBits() <= 64 &&
+          isLegalAddImmediate(C1Int.getSExtValue()))
         return false;
 
       // Neither constant will fit into an immediate, so find materialisation
       // costs.
       int C1Cost = RISCVMatInt::getIntMatCost(C1Int, Ty.getSizeInBits(),
                                               Subtarget.is64Bit());
       int ShiftedC1Cost = RISCVMatInt::getIntMatCost(
           ShiftedC1Int, Ty.getSizeInBits(), Subtarget.is64Bit());

llvm/trunk/test/CodeGen/RISCV/add-before-shl.ll

 ; RV64I-NEXT:    addi a0, a0, 256
 ; RV64I-NEXT:    slli a0, a0, 52
 ; RV64I-NEXT:    srai a0, a0, 40
 ; RV64I-NEXT:    ret
   %1 = add i24 %a, 256
   %2 = shl i24 %1, 12
   ret i24 %2
 }
+
+define i128 @add_wide_operand(i128 %a) nounwind {
+; RV32I-LABEL: add_wide_operand:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lw a2, 0(a1)
+; RV32I-NEXT:    srli a3, a2, 29
+; RV32I-NEXT:    lw a4, 4(a1)
+; RV32I-NEXT:    slli a5, a4, 3
+; RV32I-NEXT:    or a6, a5, a3
+; RV32I-NEXT:    srli a4, a4, 29
+; RV32I-NEXT:    lw a5, 8(a1)
+; RV32I-NEXT:    slli a3, a5, 3
+; RV32I-NEXT:    or a3, a3, a4
+; RV32I-NEXT:    slli a2, a2, 3
+; RV32I-NEXT:    sw a2, 0(a0)
+; RV32I-NEXT:    sw a3, 8(a0)
+; RV32I-NEXT:    sw a6, 4(a0)
+; RV32I-NEXT:    srli a2, a5, 29
+; RV32I-NEXT:    lw a1, 12(a1)
+; RV32I-NEXT:    slli a1, a1, 3
+; RV32I-NEXT:    or a1, a1, a2
+; RV32I-NEXT:    lui a2, 128
+; RV32I-NEXT:    add a1, a1, a2
+; RV32I-NEXT:    sw a1, 12(a0)
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add_wide_operand:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a1, a1, 3
+; RV64I-NEXT:    srli a2, a0, 61
+; RV64I-NEXT:    or a1, a1, a2
+; RV64I-NEXT:    addi a2, zero, 1
+; RV64I-NEXT:    slli a2, a2, 51
+; RV64I-NEXT:    add a1, a1, a2
+; RV64I-NEXT:    slli a0, a0, 3
+; RV64I-NEXT:    ret
+  %1 = add i128 %a, 5192296858534827628530496329220096
+  %2 = shl i128 %1, 3
+  ret i128 %2
+}