Add logical ops to Mips fast-isel

[rkotler]

Summary

Code is mostly copied from AArch64 port and modified where needed for Mips.

This handles the "non" legal cases of logical ops. Legal cases are handled by tablegen patterns.

[dsanders]

LGTM with whitespace nits and an improved test case. Currently many tests are missing and i32_test lacks any CHECK directives. There's a few more comments on this subject below.

lib/Target/Mips/MipsFastISel.cpp

232

Formatting nit: needs a blank line after this

236

Formatting nit: needs a blank line after this

239

Formatting nit: needs a blank line after this

243

Formatting nit: needs a blank line after this

245

Formatting nit: needs a blank line after this

479

Formatting nit: needs a blank line after this

734

Formatting nit: needs a blank line after this

748

Formatting nit: needs a blank line after this

750

Formatting nit: needs a blank line after this

test/CodeGen/Mips/Fast-ISel/logopm.ll

7–10

We don't need these lines

32–112

The tests are incomplete. Also, i32_test doesn't have any CHECK's.

The missing tests are:

• i1 xor/or
• i1 and/xor/or using immediates
• i8 and/xor
• i8 and/xor/or using immediates
• i16 and/or
• i16 and/xor/or using immediates
• i32 and/xor/or (there's code for xor but no checks)
• i32 and/xor/or using immediates (there's code for xor but no checks)

Also, please do one test per function (i.e. one function for the register form, and one for the immediate form). It makes it easier to tell what is covered.

Finally, test_i1 doesn't need to be significantly different from the others. Taking test_i8 and switching all the types to i1 (and switching to the correct global) will give you a simple test for 1-bit integers.

113–211

We don't need these lines. test/CodeGen tests are not executable.

[rkotler]

This just brings the previous patch up to tip of tree. The test case will be replaced with a more complete test case and other comments from the previous review will be addressed.

[rkotler]

FIx nits from previous review and rerun clang-format on the result.
What remains is to rewrite the test case.

[echristo]

Couple of inline comments.

Probably want to clean up the testcase a bit (though I know you've said you're working on it).

-eric

lib/Target/Mips/MipsFastISel.cpp

466

You never pass true for IsVectorAllowed, it's just dead so remove it.

test/CodeGen/Mips/Fast-ISel/logopm.ll

1

If you're going to line wrap then you should do it at 80-columns, this is just silly. :)

[rkotler]

Finish up test case.
Merge to tip of tree and run clang format.
Will go through past comments to make sure all nits have been addressed and then will request final push approval.

[rkotler]

Make Eric Christophers suggest change to remove the test for isVectorAllowed since this is not currently
an issue for Mips32 fast-isel... we don't support any vector types.

[dsanders]

The code change looks right to me (assuming the answer to my main question below is 'no') but I have a couple questions and nits regarding the test case.

The main question is should we optimize 'X & 0', 'X | 0', and 'X ^ 0'?

test/CodeGen/Mips/Fast-ISel/logopm.ll

23–49

Nit: These three aren't testing anything. They should be deleted.

51–73

Just a comment, no change required: This test and the others like it would be a lot simpler if it used arguments and returns. The patches needed for this appear later in the series though so this is ok for now and we should clean it up after those patches land.

60

Nit: Please use CHECK-LABEL to partition the file

90

There's a really trivial optimization opportunity here (x & 0 == 0). It would simply require an 'if (Opc == Mips::AND && RHSReg == Mips::ZERO) return RHSReg' in emitLogicalOp().

I'm wondering if we should handle it or not given that the goal is compile time. I'm leaning towards yes since it's so cheap to catch. Do we still delete dead code when using Fast ISel? If so, I think it's probably best to handle it since it removes the need to encode instructions. What do you think?

113

Why not 'andi $[[RES1:[0-9]+]], $[[UB1]], 1'? Will andi support be added in a later patch?

154–160

Just a question: Any idea what optimized the 'X | 0'? I don't see anything in the patch that would do it and I'm surprised that it noticed this and didn't notice 'X & 0' or 'X ^ 0'.

229

Similar to the 'X & 0' case above, there's a trivial optimization opportunity here since 'X ^ 0 == X'. It would only require an 'if (Opc == Mips::XOR && RHSReg == Mips::ZERO) return LHSReg' in emitLogicalOp().

620–739

Nit: Commented out code is discouraged. It should be deleted.

[rkotler]

test/CodeGen/Mips/Fast-ISel/logopm.ll

32–112

I like to make the putback tests be executable and possibly removing the "main function" before putting them back so I'm sure that they work.

32–112

I32 is handled without this patch already by means of the tablegen patterns.

The need for this patch is to handle things that normally would be taken care of by the legalizer. For example: xor or any non 32 integer types.

90

This situation will not occur in real life. It's occurring here because you wanted me to test all these cases in the matrix and this code I've constructed by hand. If you start to test for all these things you will make the compiler slower and more complicated.
It's also not important at this time in the greater scheme of things which is not not let fast-isel fail and revert to non fast-isel.

113

People can use -O0 if they need better code here. The more things you add to complicated fast-isel the more unreadable it becomes and more prone to bugs.

154–160

I tried to make clang IR for the whole test matrix but sometimes there is something in llvm which is still optimizing something away.

229

Not relevant IMO to worry about this now or even in the future as I explained earlier.

620–739

This test case is executable and can be compared for results with non fast-isel for testing. It should really be added to test-suite. I do not want to lose this ability to later add this in the mips specific part of test-suite.

[dsanders]

test/CodeGen/Mips/Fast-ISel/logopm.ll

23–49

This hasn't been done.

32–112

I like to make the putback tests be executable and possibly removing the "main function" before putting them back so I'm sure that they work.

I agree that checking that we can execute real C/C++ code is a good thing to have in addition to the test/CodeGen tests. However, the test/CodeGen tests are unit tests for LLVM-IR to assembly. They are not intended to be executable or language-specific (although tests for specific bugs often will be) and redundant code in these tests just costs everyone additional test overhead without adding any value.

There are people working on adding executable test support though. I'm not sure what the current state of it is but the last I saw on the subject was '[LLVMdev] QEMU testing for LIT execution tests' in September. It's aimed at compiler-rt/libcxx/etc. testing but there's no reason trivial source->execution tests couldn't use the same mechanism. Maybe we could end up with a set of tests somewhere like test/CompileAndRun/C99/... or something along those lines.

I32 is handled without this patch already by means of the tablegen patterns.

We should still check the output assembly so that we know that the tablegen patterns do the right thing in Fast ISel. At the moment you have the test but don't check that it passes.

38–39

Something I missed on the previous read throughs: None the instructions with the immediate check that the immediate is there.

I understand that we don't emit 'andi $1, $2, 3' and similar yet but we should check that the immediate is materialized in a register that is used by the instruction that would have had it.

60

This hasn't been done

90

We wouldn't implement algebraic identity elimination at all if it didn't ever occur, but I do at least agree that likely to be infrequent.

We need some numbers to make the decision properly. Extra checks cost compile time but they may also reduce compile time further down the line (e.g. by removing instructions). Whether it's generally beneficial to have them or not, I don't know.

For now, let's focus on functionality as you say and investigate optimizations to reduce compile-time later.

113

Just to double check. Did you mean -O0 here?

Hmm. FastISel is certainly aimed at low compilation time but the execution time of the output is still a relevant factor. Avoiding the immediate form instructions seems like a sacrifice too far to me.

In any case, there's no need to add the immediate forms in this patch.

620–739

I have no problem with you adding it to a mips-specific part of the test-suite but it doesn't belong here.

[dsanders]

test/CodeGen/Mips/Fast-ISel/logopm.ll

32–112

I32 is handled without this patch already by means of the tablegen patterns.

We should still check the output assembly so that we know that the tablegen patterns do the right thing in Fast ISel. At the moment you have the test but don't check that it passes.

Please disregard this comment. It appears I've commented on the first revision and not the latest.

38–39

Something I missed on the previous read throughs: None the instructions with the immediate check that the immediate is there.

I understand that we don't emit 'andi $1, $2, 3' and similar yet but we should check that the immediate is materialized in a register that is used by the instruction that would have had it.

Please disregard this comment. I've commented on the first revision and not the latest.

[rkotler]

Make requested changes to the test case.

[echristo]

Haven't looked at the contents of the testcases past the general stuff, but this looks much better.

One inline comment.

-eric

test/CodeGen/Mips/Fast-ISel/logopm.ll

583

Any reason for the CHECK-DAG here? Are you seeing ordering issues between mips32 and mip32r2 here?

[rkotler]

test/CodeGen/Mips/Fast-ISel/logopm.ll

583

The problem is that the load of US1_ADDR could be moved ahead of the load to US_ADDR. It's not happening today but there is no reason why the reordering could not occur and then it will create an unnecessary make check failure. I try and make heavy use of CHECK-DAG in order to ensure that only changes to the Mips target code generator will affect these tests and not changes to target independent code passes.

[dsanders]

Thanks and sorry for the various delays from my side. LGTM.

lib/Target/Mips/MipsFastISel.cpp

class MipsFastISel final : public FastISel {
 
   bool TargetSupported;
   bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
   // floating point but not reject doing fast-isel in other
   // situations
 
 private:
   // Selection routines.
+  bool selectLogicalOp(const Instruction *I);
   bool selectLoad(const Instruction *I);
   bool selectStore(const Instruction *I);
   bool selectBranch(const Instruction *I);
   bool selectCmp(const Instruction *I);
   bool selectFPExt(const Instruction *I);
   bool selectFPTrunc(const Instruction *I);
   bool selectFPToInt(const Instruction *I, bool IsSigned);
   bool selectRet(const Instruction *I);
   bool selectTrunc(const Instruction *I);
   bool selectIntExt(const Instruction *I);
 
   // Utility helper routines.
   bool isTypeLegal(Type *Ty, MVT &VT);
+  bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
   bool isLoadTypeLegal(Type *Ty, MVT &VT);
   bool computeAddress(const Value *Obj, Address &Addr);
   bool computeCallAddress(const Value *V, Address &Addr);
   void simplifyAddress(Address &Addr);
 
   // Emit helper routines.
   bool emitCmp(unsigned DestReg, const CmpInst *CI);
   bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
private:
   bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
   bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
                        unsigned DestReg);
   bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
                        unsigned DestReg);
 
   unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
 
+  unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
+                         const Value *RHS);
+
   unsigned materializeFP(const ConstantFP *CFP, MVT VT);
   unsigned materializeGV(const GlobalValue *GV, MVT VT);
   unsigned materializeInt(const Constant *C, MVT VT);
   unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
 
   MachineInstrBuilder emitInst(unsigned Opc) {
     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
   }

 }
 
 #include "MipsGenCallingConv.inc"
 
 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
   return CC_MipsO32;
 }
 
+unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
+                                     const Value *LHS, const Value *RHS) {
+  // Canonicalize immediates to the RHS first.
+  if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
+    std::swap(LHS, RHS);
+
+  unsigned Opc;
+  if (ISDOpc == ISD::AND) {
+    Opc = Mips::AND;
+  } else if (ISDOpc == ISD::OR) {
+    Opc = Mips::OR;
+  } else if (ISDOpc == ISD::XOR) {
+    Opc = Mips::XOR;
+  } else
+    llvm_unreachable("unexpected opcode");
+
+  unsigned LHSReg = getRegForValue(LHS);
+  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
+  if (!ResultReg)
+    return 0;
+
+  unsigned RHSReg;
+  if (!LHSReg)
+    return 0;
+
+  if (const auto *C = dyn_cast<ConstantInt>(RHS))
+    RHSReg = materializeInt(C, MVT::i32);
+  else
+    RHSReg = getRegForValue(RHS);
+
+  if (!RHSReg)
+    return 0;
+
+  emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
+  return ResultReg;
+}
+
 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
   if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
     return 0;
   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
   const ConstantInt *CI = cast<ConstantInt>(C);
   int64_t Imm;
   if ((VT != MVT::i1) && CI->isNegative())
     Imm = CI->getSExtValue();
if (evt == MVT::Other || !evt.isSimple())
     return false;
   VT = evt.getSimpleVT();
 
   // Handle all legal types, i.e. a register that will directly hold this
   // value.
   return TLI.isTypeLegal(VT);
 }
 
+bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed) {
+  if (Ty->isVectorTy() && !IsVectorAllowed)
+    return false;
+
+  if (isTypeLegal(Ty, VT))
+    return true;
+
+  // If this is a type than can be sign or zero-extended to a basic operation
+  // go ahead and accept it now.
+  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
+    return true;
+
+  return false;
+}
+
 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
   if (isTypeLegal(Ty, VT))
     return true;
   // We will extend this in a later patch:
   //   If this is a type than can be sign or zero-extended to a basic operation
   //   go ahead and accept it now.
   if (VT == MVT::i8 || VT == MVT::i16)
     return true;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
         .addFrameIndex(FI)
         .addImm(Offset)
         .addMemOperand(MMO);
     return true;
   }
   return false;
 }
 
+bool MipsFastISel::selectLogicalOp(const Instruction *I) {
+  MVT VT;
+  if (!isTypeSupported(I->getType(), VT))
+    return false;
+
+  unsigned ResultReg;
+  switch (I->getOpcode()) {
+  default:
+    llvm_unreachable("Unexpected instruction.");
+  case Instruction::And:
+    ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
+    break;
+  case Instruction::Or:
+    ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
+    break;
+  case Instruction::Xor:
+    ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
+    break;
+  }
+
+  if (!ResultReg)
+    return false;
+
+  updateValueMap(I, ResultReg);
+  return true;
+}
+
 bool MipsFastISel::selectLoad(const Instruction *I) {
   // Atomic loads need special handling.
   if (cast<LoadInst>(I)->isAtomic())
     return false;
 
   // Verify we have a legal type before going any further.
   MVT VT;
   if (!isLoadTypeLegal(I->getType(), VT))
if (!TargetSupported)
     return false;
   switch (I->getOpcode()) {
   default:
     break;
   case Instruction::Load:
     return selectLoad(I);
   case Instruction::Store:
     return selectStore(I);
+  case Instruction::And:
+  case Instruction::Or:
+  case Instruction::Xor:
+    return selectLogicalOp(I);
   case Instruction::Br:
     return selectBranch(I);
   case Instruction::Ret:
     return selectRet(I);
   case Instruction::Trunc:
     return selectTrunc(I);
   case Instruction::ZExt:
   case Instruction::SExt:
if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
     VReg = TempReg;
   }
   return VReg;
 }
 
 void MipsFastISel::simplifyAddress(Address &Addr) {
   if (!isInt<16>(Addr.getOffset())) {
     unsigned TempReg =
         materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
     unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
     emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
     Addr.setReg(DestReg);
     Addr.setOffset(0);
   }
 }
 
 namespace llvm {
 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
                                const TargetLibraryInfo *libInfo) {
   return new MipsFastISel(funcInfo, libInfo);
 }
 }

test/CodeGen/Mips/Fast-ISel/logopm.ll

+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN:     < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN:     < %s | FileCheck %s
+
+; ModuleID = 'logop.c'
+target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
+target triple = "mipsel--linux-gnu"
+
+@i1_1 = global i8 1, align 1
+@i1_2 = global i8 0, align 1
+@i1_3 = global i8 1, align 1
+@i1_4 = global i8 1, align 1
+@i8_1 = global i8 5, align 1
+@i8_2 = global i8 -61, align 1
+@i16_1 = global i16 -7998, align 2
+@i16_2 = global i16 -3871, align 2
+@i32_1 = global i32 987717, align 4
+@i32_2 = global i32 15733009, align 4
+@j1_1 = common global i8 0, align 1
+@j1_2 = common global i8 0, align 1
+@j1_3 = common global i8 0, align 1
+@j1_4 = common global i8 0, align 1
+@j8_1 = common global i8 0, align 1
+@j8_2 = common global i8 0, align 1
+@j16_1 = common global i16 0, align 2
+@j16_2 = common global i16 0, align 2
+@j32_1 = common global i32 0, align 4
+@j32_2 = common global i32 0, align 4
+
+; Function Attrs: nounwind
+define void @i1_test() #0 {
+entry:
+; CHECK-LABEL: .ent i1_test
+  %0 = load i8* @i1_1, align 1
+  %conv = trunc i8 %0 to i1
+  %and = and i1 1, %conv
+; CHECK:  and ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+  %conv1 = zext i1 %and to i8
+  store i8 %conv1, i8* @j1_1, align 1
+  %1 = load i8* @i1_1, align 1
+  %conv2 = trunc i8 %1 to i1
+  %2 = load i8* @i1_2, align 1
+  %conv3 = trunc i8 %2 to i1
+  %and4 = and i1 %conv2, %conv3
+; CHECK:  and ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+  %conv5 = zext i1 %and4 to i8
+  store i8 %conv5, i8* @j1_2, align 1
+  %3 = load i8* @i1_2, align 1
+  %conv6 = trunc i8 %3 to i1
+  %4 = load i8* @i1_3, align 1
+  %conv7 = trunc i8 %4 to i1
+  %and8 = and i1 %conv6, %conv7
+; CHECK:  and ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+  %conv9 = zext i1 %and8 to i8
+  store i8 %conv9, i8* @j1_3, align 1
+  %5 = load i8* @i1_3, align 1
+  %conv10 = trunc i8 %5 to i1
+  %6 = load i8* @i1_4, align 1
+  %conv11 = trunc i8 %6 to i1
+  %and12 = and i1 %conv10, %conv11
+; CHECK:  and ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+  %conv13 = zext i1 %and12 to i8
+  store i8 %conv13, i8* @j1_4, align 1
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @i8_test() #0 {
+entry:
+; CHECK-LABEL: .ent i8_test
+  %0 = load i8* @i8_1, align 1
+  %or = or i8 %0, 225
+  store i8 %or, i8* @j8_1, align 1
+; CHECK:  or  ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+  %1 = load i8* @i8_1, align 1
+  %2 = load i8* @i8_2, align 1
+  %or4 = or i8 %1, %2
+; CHECK:  or  ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+  store i8 %or4, i8* @j8_2, align 1
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @i16_test() #0 {
+entry:
+; CHECK-LABEL: .ent i16_test
+  %0 = load i16* @i16_1, align 2
+  %xor = xor i16 241, %0
+  store i16 %xor, i16* @j16_1, align 2
+; CHECK:  xor ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+  %1 = load i16* @i16_1, align 2
+  %2 = load i16* @i16_2, align 2
+  %xor4 = xor i16 %1, %2
+; CHECK:  xor ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+  store i16 %xor4, i16* @j16_2, align 2
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @i32_test() #0 {
+entry:
+  %0 = load i32* @i32_1, align 4
+  %xor = xor i32 %0, -16908096
+  store i32 %xor, i32* @j32_1, align 4
+  %1 = load i32* @i32_1, align 4
+  %2 = load i32* @i32_2, align 4
+  %xor1 = xor i32 %1, %2
+  store i32 %xor1, i32* @j32_2, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+define i32 @main() #0 {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  call void @i1_test()
+  %0 = load i8* @j1_1, align 1
+  %conv = sext i8 %0 to i32
+  %cmp = icmp ne i32 %conv, 1
+  br i1 %cmp, label %if.then, label %lor.lhs.false
+
+lor.lhs.false:                                    ; preds = %entry
+  %1 = load i8* @j1_2, align 1
+  %conv2 = sext i8 %1 to i32
+  %cmp3 = icmp ne i32 %conv2, 0
+  br i1 %cmp3, label %if.then, label %lor.lhs.false5
+
+lor.lhs.false5:                                   ; preds = %lor.lhs.false
+  %2 = load i8* @j1_3, align 1
+  %conv6 = sext i8 %2 to i32
+  %cmp7 = icmp ne i32 %conv6, 0
+  br i1 %cmp7, label %if.then, label %lor.lhs.false9
+
+lor.lhs.false9:                                   ; preds = %lor.lhs.false5
+  %3 = load i8* @j1_4, align 1
+  %conv10 = sext i8 %3 to i32
+  %cmp11 = icmp ne i32 %conv10, 1
+  br i1 %cmp11, label %if.then, label %if.end
+
+if.then:                                          ; preds = %lor.lhs.false9, %lor.lhs.false5, %lor.lhs.false, %entry
+  call void @abort() #2
+  unreachable
+
+if.end:                                           ; preds = %lor.lhs.false9
+  call void @i8_test()
+  %4 = load i8* @j8_1, align 1
+  %conv13 = zext i8 %4 to i32
+  %cmp14 = icmp ne i32 %conv13, 229
+  br i1 %cmp14, label %if.then20, label %lor.lhs.false16
+
+lor.lhs.false16:                                  ; preds = %if.end
+  %5 = load i8* @j8_2, align 1
+  %conv17 = zext i8 %5 to i32
+  %cmp18 = icmp ne i32 %conv17, 199
+  br i1 %cmp18, label %if.then20, label %if.end21
+
+if.then20:                                        ; preds = %lor.lhs.false16, %if.end
+  call void @abort() #2
+  unreachable
+
+if.end21:                                         ; preds = %lor.lhs.false16
+  call void @i16_test()
+  %6 = load i16* @j16_1, align 2
+  %conv22 = zext i16 %6 to i32
+  %cmp23 = icmp ne i32 %conv22, 57395
+  br i1 %cmp23, label %if.then29, label %lor.lhs.false25
+
+lor.lhs.false25:                                  ; preds = %if.end21
+  %7 = load i16* @j16_2, align 2
+  %conv26 = zext i16 %7 to i32
+  %cmp27 = icmp ne i32 %conv26, 4131
+  br i1 %cmp27, label %if.then29, label %if.end30
+
+if.then29:                                        ; preds = %lor.lhs.false25, %if.end21
+  call void @abort() #2
+  unreachable
+
+if.end30:                                         ; preds = %lor.lhs.false25
+  call void @i32_test()
+  %8 = load i32* @j32_1, align 4
+  %cmp31 = icmp ne i32 %8, -17755515
+  br i1 %cmp31, label %if.then36, label %lor.lhs.false33
+
+lor.lhs.false33:                                  ; preds = %if.end30
+  %9 = load i32* @j32_2, align 4
+  %cmp34 = icmp ne i32 %9, 16712532
+  br i1 %cmp34, label %if.then36, label %if.end37
+
+if.then36:                                        ; preds = %lor.lhs.false33, %if.end30
+  call void @abort() #2
+  unreachable
+
+if.end37:                                         ; preds = %lor.lhs.false33
+  ret i32 0
+}
+
+; Function Attrs: noreturn
+declare void @abort() #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { noreturn "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { noreturn }
+
+