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[mips][FastISel] Implement the select statement for MIPS FastISel.
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Authored by vkalintiris on Dec 23 2014, 6:20 PM.

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Summary

Implement the LLVM IR select statement for MIPS FastISel.

Based on a patch by Reed Kotler.

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rL LLVM

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rkotler updated this revision to Diff 17619.Dec 23 2014, 6:20 PM
rkotler retitled this revision from to Implement mips fast-isel select statement.
rkotler updated this object.
rkotler edited the test plan for this revision. (Show Details)
rkotler added a reviewer: dsanders.
rkotler added subscribers: rfuhler, Unknown Object (MLST).

Simple executable test case.

rkotler updated this revision to Diff 18202.Jan 14 2015, 5:43 PM
rkotler edited the test plan for this revision. (Show Details)

A regression was fixed here because it shows up in test-suite only after this patch. It's a generic problem caused by a shortcoming in tabelgen whereby you can't mark a side effect of an instruction as it making a register Dead and instead out tablegen marked the mul instruction wirh defs for LO0 and HI0 which causes a problem for the register allocator when trying to allocate register AC0 since LO0 and HI0 are dependent registers.

The solution here for this regression is probably temporary since the proper way is to fix tablegen but that will require some more work and approval.

vkalintiris commandeered this revision.Apr 16 2015, 5:33 AM
vkalintiris added a reviewer: rkotler.
dsanders added inline comments.May 12 2015, 4:06 AM
lib/Target/Mips/MipsFastISel.cpp
928–934 ↗(On Diff #18202)

We don't need to check each integer type explictly. The generated code is correct for all integers of GPR size or smaller.

947 ↗(On Diff #18202)

Nit: Useless statement

960 ↗(On Diff #18202)

I think this is only needed if Src2Reg != DestReg. Is it possible for this code to emit something like:

move $2, $2
movn $2, $3, $4
964 ↗(On Diff #18202)

TempReg isn't implicitly read. It's explicit in our instruction definition:

(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F)
1660–1679 ↗(On Diff #18202)

Why is this chunk in this patch? It looks we have two patches in one review.

test/CodeGen/Mips/Fast-ISel/sel1.ll
22 ↗(On Diff #18202)

At this point we should have support for arguments and returns. Could you simplify the test using those?

I don't mind if we clean this up later but I'd like to have as little noise as possible in the tests.

vkalintiris retitled this revision from Implement mips fast-isel select statement to [mips][FastISel] Implement the select statement for MIPS FastISel..
vkalintiris updated this object.
vkalintiris edited the test plan for this revision. (Show Details)

Addressed review comments and removed the review's portions that are not
strictly related to the implementation of the select instruction.

dsanders accepted this revision.Jun 1 2015, 6:16 AM
dsanders edited edge metadata.

LGTM with the type check corrected and the FIXMEs added.

lib/Target/Mips/MipsFastISel.cpp
906 ↗(On Diff #25768)

MVT::INVALID_SIMPLE_VALUE_TYPE and MVT::Other are included in this check and shouldn't be.

Also, you can't rely on the types being defined in this order. You could use:

VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32
test/CodeGen/Mips/Fast-ISel/sel1.ll
8 ↗(On Diff #25768)

Nit: Redundant instruction. You can leave a FIXME for now and follow up on it.

23–24 ↗(On Diff #25768)

Nit: Redundant instructions. You can leave a FIXME for now and follow up on it.

39–40 ↗(On Diff #25768)

Nit: Redundant instructions. You can leave a FIXME for now and follow up on it.

53 ↗(On Diff #25768)

Nit: Redundant instruction. You can leave a FIXME for now and follow up on it.

68 ↗(On Diff #25768)

Nit: Redundant instruction. You can leave a FIXME for now and follow up on it.

83 ↗(On Diff #25768)

Nit: Redundant instruction. You can leave a FIXME for now and follow up on it.

This revision is now accepted and ready to land.Jun 1 2015, 6:16 AM
This revision was automatically updated to reflect the committed changes.