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[mips][FastISel] Clobber HI0/LO0 registers in MUL instructions.
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Authored by vkalintiris on May 18 2015, 8:08 AM.

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Summary

The contents of the HI/LO registers are unpredictable after the execution of
the MUL instruction. In addition to implicitly defining these registers in the
MUL instruction definition, we have to mark those registers as dead too.

Without this the fast register allocator is running out of registers when the
MUL instruction is followed by another one that tries to allocate the AC0
register.

Based on a patch by Reed Kotler.

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Repository
rL LLVM

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vkalintiris retitled this revision from to [mips][FastISel] Clobber HI0/LO0 registers in MUL instructions..
vkalintiris updated this object.
vkalintiris edited the test plan for this revision. (Show Details)
vkalintiris added reviewers: dsanders, rkotler.
vkalintiris added subscribers: rfuhler, Unknown Object (MLST).
dsanders accepted this revision.May 19 2015, 6:15 AM
dsanders edited edge metadata.

LGTM

This revision is now accepted and ready to land.May 19 2015, 6:15 AM
This revision was automatically updated to reflect the committed changes.