[ARM] Make v2i1 a valid type for the MVE predicate register.

[simon_tatham]

Summary

There are MVE instructions that treat a 128-bit vector register as a
vector of two 64-bit lanes, e.g. the VLDRD.64 gather loads. To
represent predicated forms of those instructions usefully in code
generation, we'll want to use a v2i1 as the representation of the
predicate mask, because it only has one meaningful bit per 64-bit
lane.

[samparker]

Some codegen tests would be good.

[dmgreen]

Yeah... A lot of the predicate code was written with the assumption that a v2i1 would not be a legal type. (Not deliberately, I just didn't think of it at all. We don't have the compares to make it generally useful). I'll have to at least run some fuzzer tests on this.

I'm surprised a lot of the existing v2i64 tests don't complain in some way.

[simon_tatham]

Hmm. I may have underestimated the difficulty, then! My thought was that all I really needed was to arrange that if you already had a v2i1, you could use it as the predicate operand for one of the 64-bit-lane instructions and not have instruction selection fail, and perhaps if you already had a pair of them you could do bitwise ops between them just like you can with all the others.

I can write some simple codegen tests for the things I've just mentioned, but it sounds as if there are more complicated things I've overlooked that will also need testing?

[dmgreen]

It was the "buildvector" code from D65052 that I was thinking of the most (or "buildvector" is what I've been calling it at least). How to get values into and out of v2i1 vectors, how to handle shuffles of i1's vectors, sign extending a v2i1 to a v2i64, that kind of thing. The vectoriser will produce a lot of <2 x i1>'s in all kinds of weird and wonderful ways that we need to handle at least sensibly (if not always super efficiently, that's what cost models are for!).

[simon_tatham]

Abandoning this ancient revision, on the grounds that even if we did want to do it, it's surely so outdated that it would need doing all over again. (And in any case this patch had almost nothing in it.)

llvm/lib/Target/ARM/ARMISelLowering.cpp

void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
   addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
 
   // Some truncating stores are legal too.
   setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
   setTruncStoreAction(MVT::v4i32, MVT::v4i8,  Legal);
   setTruncStoreAction(MVT::v8i16, MVT::v8i8,  Legal);
 
   // Predicate types
-  const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1};
+  const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1, MVT::v2i1};
   for (auto VT : pTypes) {
     addRegisterClass(VT, &ARM::VCCRRegClass);
     setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
     setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
     setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
     setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
                                              N1->getOperand(0));
                 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
             }
         }
     }
   }
 
   if (Subtarget->hasMVEIntegerOps() &&
-      (VT == MVT::v4i1 || VT == MVT::v8i1 || VT == MVT::v16i1))
+      (VT == MVT::v2i1 || VT == MVT::v4i1 ||
+       VT == MVT::v8i1 || VT == MVT::v16i1))
     return PerformORCombine_i1(N, DCI, Subtarget);
 
   // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
   // reasonable.
   if (N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
     if (SDValue Res = PerformORCombineToBFI(N, DCI, Subtarget))
       return Res;
   }
if (Subtarget->hasNEON() && (AllowsUnaligned || Subtarget->isLittle())) {
       return true;
     }
   }
 
   if (!Subtarget->hasMVEIntegerOps())
     return false;
 
   // These are for predicates
-  if ((Ty == MVT::v16i1 || Ty == MVT::v8i1 || Ty == MVT::v4i1)) {
+  if ((Ty == MVT::v16i1 || Ty == MVT::v8i1 ||
+       Ty == MVT::v4i1 || Ty == MVT::v2i1)) {
     if (Fast)
       *Fast = true;
     return true;
   }
 
   // These are for truncated stores/narrowing loads. They are fine so long as
   // the alignment is at least the size of the item being loaded
   if ((Ty == MVT::v4i8 || Ty == MVT::v8i8 || Ty == MVT::v4i16) &&

llvm/lib/Target/ARM/ARMInstrMVE.td

 // Occasionally we need to cast between a i32 and a boolean vector, for
 // example when moving between rGPR and VPR.P0 as part of predicate vector
 // shuffles. We also sometimes need to cast between different predicate
 // vector types (v4i1<>v8i1, etc.) also as part of lowering vector shuffles.
 
 def predicate_cast : SDNode<"ARMISD::PREDICATE_CAST", SDTUnaryOp>;
 
 let Predicates = [HasMVEInt] in {
-  foreach VT = [ v4i1, v8i1, v16i1 ] in {
+  foreach VT = [ v2i1, v4i1, v8i1, v16i1 ] in {
     def : Pat<(i32 (predicate_cast (VT VCCR:$src))),
               (i32 (COPY_TO_REGCLASS (VT VCCR:$src), VCCR))>;
     def : Pat<(VT  (predicate_cast (i32 VCCR:$src))),
               (VT  (COPY_TO_REGCLASS (i32 VCCR:$src), VCCR))>;
 
-    foreach VT2 = [ v4i1, v8i1, v16i1 ] in
+    foreach VT2 = [ v2i1, v4i1, v8i1, v16i1 ] in
       def : Pat<(VT  (predicate_cast (VT2 VCCR:$src))),
                 (VT  (COPY_TO_REGCLASS (VT2 VCCR:$src), VCCR))>;
   }
 }
 
 // end of MVE compares
 
 // start of MVE_qDest_qSrc
def MVE_VPNOT : MVE_p<(outs VCCR:$P0), (ins VCCR:$P0_in), NoItinerary,
   let Unpredictable{7} = 0b1;
   let Unpredictable{5} = 0b1;
 
   let Constraints = "";
   let DecoderMethod = "DecodeMVEVPNOT";
 }
 
 let Predicates = [HasMVEInt] in {
+  def : Pat<(v2i1 (xor (v2i1 VCCR:$pred), (v2i1 (predicate_cast (i32 65535))))),
+            (v2i1 (MVE_VPNOT (v2i1 VCCR:$pred)))>;
   def : Pat<(v4i1 (xor (v4i1 VCCR:$pred), (v4i1 (predicate_cast (i32 65535))))),
             (v4i1 (MVE_VPNOT (v4i1 VCCR:$pred)))>;
   def : Pat<(v8i1 (xor (v8i1 VCCR:$pred), (v8i1 (predicate_cast (i32 65535))))),
             (v8i1 (MVE_VPNOT (v8i1 VCCR:$pred)))>;
   def : Pat<(v16i1 (xor (v16i1 VCCR:$pred), (v16i1 (predicate_cast (i32 65535))))),
             (v16i1 (MVE_VPNOT (v16i1 VCCR:$pred)))>;
 }
 
let Predicates = [HasMVEInt, IsLE] in {
   defm : MVE_unpred_vector_load<MVE_VLDRWU32, alignedload32, 2>;
 
   def  : Pat<(v16i1 (load t2addrmode_imm7<2>:$addr)),
              (v16i1 (VLDR_P0_off t2addrmode_imm7<2>:$addr))>;
   def  : Pat<(v8i1 (load t2addrmode_imm7<2>:$addr)),
              (v8i1 (VLDR_P0_off t2addrmode_imm7<2>:$addr))>;
   def  : Pat<(v4i1 (load t2addrmode_imm7<2>:$addr)),
              (v4i1 (VLDR_P0_off t2addrmode_imm7<2>:$addr))>;
+  def  : Pat<(v2i1 (load t2addrmode_imm7<2>:$addr)),
+             (v2i1 (VLDR_P0_off t2addrmode_imm7<2>:$addr))>;
 }
 
 let Predicates = [HasMVEInt, IsBE] in {
   def : MVE_unpred_vector_store_typed<v16i8, MVE_VSTRBU8, store, 0>;
   def : MVE_unpred_vector_store_typed<v8i16, MVE_VSTRHU16, alignedstore16, 1>;
   def : MVE_unpred_vector_store_typed<v8f16, MVE_VSTRHU16, alignedstore16, 1>;
   def : MVE_unpred_vector_store_typed<v4i32, MVE_VSTRWU32, alignedstore32, 2>;
   def : MVE_unpred_vector_store_typed<v4f32, MVE_VSTRWU32, alignedstore32, 2>;

llvm/lib/Target/ARM/ARMRegisterInfo.td

 
 // Condition code registers.
 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
   let CopyCost = -1;  // Don't allow copying of status registers.
   let isAllocatable = 0;
 }
 
 // MVE Condition code register.
-def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1], 32, (add VPR)> {
+def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1, v2i1], 32, (add VPR)> {
 //  let CopyCost = -1;  // Don't allow copying of status registers.
 }
 
 // FPSCR, when the flags at the top of it are used as the input or
 // output to an instruction such as MVE VADC.
 def cl_FPSCR_NZCV : RegisterClass<"ARM", [i32], 32, (add FPSCR_NZCV)>;
 
 // Scalar single precision floating point register class..