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Differential D65908

Support unary FNeg in LICM
ClosedPublic

Authored by cameron.mcinally on Aug 7 2019, 2:38 PM.

Details

Reviewers
spatel
arsenm
kpn
nicholas
nlewycky
reames
craig.topper
Commits
rG8416f20f2f55: [LICM] Support unary FNeg in LICM
rL368350: [LICM] Support unary FNeg in LICM

Diff Detail

Event Timeline

cameron.mcinally created this revision.Aug 7 2019, 2:38 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 7 2019, 2:38 PM
Herald added subscribers: llvm-commits, asbirlea, jfb and 2 others. · View Herald Transcript
cameron.mcinally edited reviewers, added: craig.topper; removed: craig.scott.Aug 7 2019, 2:39 PM
spatel accepted this revision.Aug 8 2019, 9:11 AM

LGTM

This revision is now accepted and ready to land.Aug 8 2019, 9:11 AM
Closed by commit rL368350: [LICM] Support unary FNeg in LICM (authored by mcinally). · Explain WhyAug 8 2019, 2:39 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Transforms/
Scalar/
3 lines
test/
Transforms/
LICM/
3 lines

Diff 214007

llvm/lib/Transforms/Scalar/LICM.cpp

Show First 20 Lines • Show All 1,020 Lines • ▼ Show 20 Lines
namespace { namespace {
/// Return true if-and-only-if we know how to (mechanically) both hoist and /// Return true if-and-only-if we know how to (mechanically) both hoist and
/// sink a given instruction out of a loop. Does not address legality /// sink a given instruction out of a loop. Does not address legality
/// concerns such as aliasing or speculation safety. /// concerns such as aliasing or speculation safety.
bool isHoistableAndSinkableInst(Instruction &I) { bool isHoistableAndSinkableInst(Instruction &I) {
// Only these instructions are hoistable/sinkable. // Only these instructions are hoistable/sinkable.
return (isa<LoadInst>(I) || isa<StoreInst>(I) || isa<CallInst>(I) || return (isa<LoadInst>(I) || isa<StoreInst>(I) || isa<CallInst>(I) ||
isa<FenceInst>(I) || isa<BinaryOperator>(I) || isa<CastInst>(I) || isa<FenceInst>(I) || isa<CastInst>(I) ||
isa<UnaryOperator>(I) || isa<BinaryOperator>(I) ||
isa<SelectInst>(I) || isa<GetElementPtrInst>(I) || isa<CmpInst>(I) || isa<SelectInst>(I) || isa<GetElementPtrInst>(I) || isa<CmpInst>(I) ||
isa<InsertElementInst>(I) || isa<ExtractElementInst>(I) || isa<InsertElementInst>(I) || isa<ExtractElementInst>(I) ||
isa<ShuffleVectorInst>(I) || isa<ExtractValueInst>(I) || isa<ShuffleVectorInst>(I) || isa<ExtractValueInst>(I) ||
isa<InsertValueInst>(I)); isa<InsertValueInst>(I));
} }
/// Return true if all of the alias sets within this AST are known not to /// Return true if all of the alias sets within this AST are known not to
/// contain a Mod, or if MSSA knows thare are no MemoryDefs in the loop. /// contain a Mod, or if MSSA knows thare are no MemoryDefs in the loop.
bool isReadOnly(AliasSetTracker *CurAST, const MemorySSAUpdater *MSSAU, bool isReadOnly(AliasSetTracker *CurAST, const MemorySSAUpdater *MSSAU,
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llvm/test/Transforms/LICM/hoisting.ll

Show First 20 Lines • Show All 121 Lines • ▼ Show 20 Linesthen: ; preds = %tailrecurse
%cmp2 = add i32 %i.tr, 1 %cmp2 = add i32 %i.tr, 1
br label %tailrecurse br label %tailrecurse
ifend: ; preds = %tailrecurse ifend: ; preds = %tailrecurse
ret { i32*, i32 } %d ret { i32*, i32 } %d
} }
; CHECK: define void @test6(float %f) ; CHECK: define void @test6(float %f)
; CHECK: call
; CHECK: fneg ; CHECK: fneg
; CHECK: call ; CHECK: br label %for.body
define void @test6(float %f) #2 { define void @test6(float %f) #2 {
entry: entry:
br label %for.body br label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%i = phi i32 [ 0, %entry ], [ %inc, %for.body ] %i = phi i32 [ 0, %entry ], [ %inc, %for.body ]
call void @foo_may_call_exit(i32 0) call void @foo_may_call_exit(i32 0)
%neg = fneg float %f %neg = fneg float %f
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