AArch64: support @llvm.{return,frame}address in GlobalISel

[t.p.northover]

Summary

These intrinsics expand to a variable number of instructions so just like in ISelLowering.cpp we use custom code to deal with them.

[aemerson]

LGTM with test nit.

llvm/test/CodeGen/AArch64/GlobalISel/select-frameaddr.ll

2

If you're going to use an llc test can you add -global-isel-abort=1 -verify-machineinstrs too.

[aemerson]

llvm/test/CodeGen/AArch64/GlobalISel/select-frameaddr.ll

2

s/llc/.ll

[arsenm]

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

4134

Should backends be directly consuming intrinsics like this? I would expect these to be lowered earlier, and select to never deal with a generic intrinsic

[aemerson]

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

4134

What else could these be lowered to?

[t.p.northover]

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

4134

You could probably just about expand everything in terms of @llvm.frameaddress(i32 0), but it would be pretty target-specific and not terribly efficient for @llvm.returnaddress(i32 0).

[aemerson]

Ping. Can we get this in?

[RKSimon]

reverted due to EXPENSIVE_CHECKS fails: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-ubuntu/builds/1917

[aemerson]

Fixed in 2e39ea726e9.

[aemerson]

Re-closing.

[peter.smith]

In D65656#1822347, @aemerson wrote:

Re-closing.

Apologies I've bisected an AArch64 sanitiser buildbot failure down to revision 2e39ea726e9cee20060892705164760229e0cb0b
Revert "Revert rG6078f2fedcac5797ac39ee5ef3fd7a35ef1202d5 - "[AArch64][GlobalISel]: Support @llvm.{return,frame}address selection.""
This first started failing http://lab.llvm.org:8011/builders/clang-cmake-aarch64-lld/builds/8015 with fail mails likely suppressed due to a previous failing build.

When I run the test manually I get the output:

UNCHANGED 'abcdef'
EMPTY ''
PARTIAL '0x4c3'
FIRST_FORMAT 0x4c3694  (/home/peter.smith/llvm/repos/builda64/projects/compiler-rt/test/sanitizer_common/asan-a
SECOND_FORMAT FUNC:<null> LINE:0 FILE:<null>
LONG_FORMAT LOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
GLOBAL: <null> <null>:0

Where the <null> LINE:0: File:<null> are supposed to be // CHECK: SECOND_FORMAT FUNC:main LINE:[[@LINE+1]] FILE:symbolize_pc.cpp
It looks like the symboliser is no longer able to find the function.
The test is run at -O0 so this will get global-isel on AArch64.

Can you take a look?

[aemerson]

In D65656#1830280, @peter.smith wrote:

In D65656#1822347, @aemerson wrote:

Re-closing.

Apologies I've bisected an AArch64 sanitiser buildbot failure down to revision 2e39ea726e9cee20060892705164760229e0cb0b
Revert "Revert rG6078f2fedcac5797ac39ee5ef3fd7a35ef1202d5 - "[AArch64][GlobalISel]: Support @llvm.{return,frame}address selection.""
This first started failing http://lab.llvm.org:8011/builders/clang-cmake-aarch64-lld/builds/8015 with fail mails likely suppressed due to a previous failing build.

When I run the test manually I get the output:

UNCHANGED 'abcdef'
EMPTY ''
PARTIAL '0x4c3'
FIRST_FORMAT 0x4c3694  (/home/peter.smith/llvm/repos/builda64/projects/compiler-rt/test/sanitizer_common/asan-a
SECOND_FORMAT FUNC:<null> LINE:0 FILE:<null>
LONG_FORMAT LOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
GLOBAL: <null> <null>:0

Where the <null> LINE:0: File:<null> are supposed to be // CHECK: SECOND_FORMAT FUNC:main LINE:[[@LINE+1]] FILE:symbolize_pc.cpp
It looks like the symboliser is no longer able to find the function.
The test is run at -O0 so this will get global-isel on AArch64.

Can you take a look?

Sorry, I missed this email. I'll take a look and do a quick fix if I can (don't have access to a linux machine) or revert if it'll take longer.

[aemerson]

In D65656#1830280, @peter.smith wrote:

In D65656#1822347, @aemerson wrote:

Re-closing.

Apologies I've bisected an AArch64 sanitiser buildbot failure down to revision 2e39ea726e9cee20060892705164760229e0cb0b
Revert "Revert rG6078f2fedcac5797ac39ee5ef3fd7a35ef1202d5 - "[AArch64][GlobalISel]: Support @llvm.{return,frame}address selection.""
This first started failing http://lab.llvm.org:8011/builders/clang-cmake-aarch64-lld/builds/8015 with fail mails likely suppressed due to a previous failing build.

When I run the test manually I get the output:

UNCHANGED 'abcdef'
EMPTY ''
PARTIAL '0x4c3'
FIRST_FORMAT 0x4c3694  (/home/peter.smith/llvm/repos/builda64/projects/compiler-rt/test/sanitizer_common/asan-a
SECOND_FORMAT FUNC:<null> LINE:0 FILE:<null>
LONG_FORMAT LOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
GLOBAL: <null> <null>:0

Where the <null> LINE:0: File:<null> are supposed to be // CHECK: SECOND_FORMAT FUNC:main LINE:[[@LINE+1]] FILE:symbolize_pc.cpp
It looks like the symboliser is no longer able to find the function.
The test is run at -O0 so this will get global-isel on AArch64.

Can you take a look?

I've committed 2e25d75aaa2 which should hopefully fix it.

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

bool AArch64InstructionSelector::selectIntrinsic(
   unsigned IntrinID = findIntrinsicID(I);
   if (!IntrinID)
     return false;
   MachineIRBuilder MIRBuilder(I);
 
   switch (IntrinID) {
   default:
     break;
-  case Intrinsic::aarch64_crypto_sha1h:
+  case Intrinsic::aarch64_crypto_sha1h: {
     Register DstReg = I.getOperand(0).getReg();
     Register SrcReg = I.getOperand(2).getReg();
 
     // FIXME: Should this be an assert?
     if (MRI.getType(DstReg).getSizeInBits() != 32 ||
         MRI.getType(SrcReg).getSizeInBits() != 32)
       return false;
 
if (DstReg != I.getOperand(0).getReg()) {
       MIRBuilder.buildCopy({I.getOperand(0)}, {DstReg});
       RBI.constrainGenericRegister(I.getOperand(0).getReg(),
                                    AArch64::GPR32RegClass, MRI);
     }
 
     I.eraseFromParent();
     return true;
   }
+  case Intrinsic::frameaddress:
+  case Intrinsic::returnaddress: {
+    MachineFunction &MF = *I.getParent()->getParent();
+    MachineFrameInfo &MFI = MF.getFrameInfo();
+
+    unsigned Depth = I.getOperand(2).getImm();
+    Register DstReg = I.getOperand(0).getReg();
+    RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI);
+
+    if (Depth == 0 && IntrinID == Intrinsic::returnaddress) {
+      MFI.setReturnAddressIsTaken(true);
+      MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
+      I.getParent()->addLiveIn(AArch64::LR);
+      MIRBuilder.buildCopy({DstReg}, {Register(AArch64::LR)});
+      I.eraseFromParent();
+      return true;
+    }
+
+    MFI.setFrameAddressIsTaken(true);
+    Register FrameAddr(AArch64::FP);
+    while (Depth--) {
+      Register NextFrame = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
+      MIRBuilder.buildInstr(AArch64::LDRXui, {NextFrame}, {FrameAddr}).addImm(0);
+      FrameAddr = NextFrame;
+    }
+
+    if (IntrinID == Intrinsic::frameaddress)
+      MIRBuilder.buildCopy({DstReg}, {FrameAddr});
+    else {
+      MFI.setReturnAddressIsTaken(true);
+      MIRBuilder.buildInstr(AArch64::LDRXui, {DstReg}, {FrameAddr}).addImm(1);
+    }
+
+    I.eraseFromParent();
+    return true;
+  }
+  }
   return false;
 }
 
 static Optional<uint64_t> getImmedFromMO(const MachineOperand &Root) {
   auto &MI = *Root.getParent();
   auto &MBB = *MI.getParent();
   auto &MF = *MBB.getParent();
   auto &MRI = MF.getRegInfo();

llvm/test/CodeGen/AArch64/GlobalISel/select-frameaddr.ll

+; RUN: llc -mtriple=arm64-apple-ios -global-isel -o - %s | FileCheck %s
+
+define i8* @rt0(i32 %x) nounwind readnone {
+entry:
+; CHECK-LABEL: rt0:
+; CHECK: mov x0, x29
+  %0 = tail call i8* @llvm.frameaddress(i32 0)
+  ret i8* %0
+}
+
+define i8* @rt2() nounwind readnone {
+entry:
+; CHECK-LABEL: rt2:
+; CHECK: ldr x[[reg:[0-9]+]], [x29]
+; CHECK: ldr x0, [x[[reg]]]
+  %0 = tail call i8* @llvm.frameaddress(i32 2)
+  ret i8* %0
+}
+
+declare i8* @llvm.frameaddress(i32) nounwind readnone

llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddr.ll

+; RUN: llc -mtriple=arm64-apple-ios -global-isel -o - %s | FileCheck %s
+
+define i8* @rt0(i32 %x) nounwind readnone {
+entry:
+; CHECK-LABEL: rt0:
+; CHECK-NOT: stp
+; CHECK: mov x0, x30
+  %0 = tail call i8* @llvm.returnaddress(i32 0)
+  ret i8* %0
+}
+
+define i8* @rt2() nounwind readnone {
+entry:
+; CHECK-LABEL: rt2:
+; CHECK: ldr x[[reg:[0-9]+]], [x29]
+; CHECK: ldr x[[reg]], [x[[reg]]]
+; CHECK: ldr x0, [x[[reg]], #8]
+  %0 = tail call i8* @llvm.returnaddress(i32 2)
+  ret i8* %0
+}
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone