[PowerPC] Eliminate loads/swap feeding swap/store for vector type by using big-endian load/store

[• wuzish]

Summary

In PowerPC, there is instruction to load vector in big endian element order when it's in little endian target.
So we can combine vector load + reverse into big endian load to eliminate the swap instruction. Also combine vector reverse + store into big endian store.

[• wuzish]

Gentle pin..

[jsji]

Mostly good to me.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

13109 ↗

(On Diff #211019)

Can this be a range-based for loop?

13124 ↗

(On Diff #211019)

Maybe we should check this before more expensive IsElementReverse check?

llvm/lib/Target/PowerPC/PPCISelLowering.h

462 ↗

(On Diff #211019)

This will overlap with LXVD2X above, it would be great if we can have a follow up NFC to clean up.

llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll

8 ↗

(On Diff #211019)

Can we add one RUN line to run big endian test to make sure nothing get affected?

[• wuzish]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

13109 ↗

(On Diff #211019)

It's not easy because it's reverse begin and end.

llvm/lib/Target/PowerPC/PPCISelLowering.h

462 ↗

(On Diff #211019)

Yes, it would be good to merge the implementation of LXVD2X/STXVD2X into LOAD_VEC_BE/STORE_VEC_BE. I would try to do this in another patch.

[• wuzish]

Commit testcase firstly and address comments.

[jsji]

LGTM. Thanks for exploiting.

[• wuzish]

Sorry to forget to add revision address in commit. Close it manually.

https://reviews.llvm.org/rL367382

[• wuzish]

update patch due to find issue.

[• wuzish]

Because we have PPCVSXSwapRemoval pass to hack the element order before P9 with vsx, the element order is not always standard normal order in register.
And the optimization of this patch will be conflict with PPCVSXSwapRemoval so that we can not get correct result during the process. The fix way is to not do this optmization before P9.

[jsji]

LGTM.

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h

enum NodeType : unsigned {
       /// followed by a byte-width for the store.
       STXSIX,
 
       /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
       /// Maps directly to an lxvd2x instruction that will be followed by
       /// an xxswapd.
       LXVD2X,
 
+      /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
+      /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on
+      /// the vector type to load vector in big-endian element order.
+      LOAD_VEC_BE,
+
       /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a
       /// v2f32 value into the lower half of a VSR register.
       LD_VSX_LH,
 
       /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
       /// Maps directly to an stxvd2x instruction that will be preceded by
       /// an xxswapd.
       STXVD2X,
 
+      /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
+      /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on
+      /// the vector type to store vector in big-endian element order.
+      STORE_VEC_BE,
+
       /// Store scalar integers from VSR.
       ST_VSR_SCAL_INT,
 
       /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
       /// The 4xf32 load used for v4i1 constants.
       QVLFSb,
 
       /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
private:
     SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const;
+    SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase,
+                                 DAGCombinerInfo &DCI) const;
 
     /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
     /// SETCC with integer subtraction when (1) there is a legal way of doing it
     /// (2) keeping the result of comparison in GPR has performance benefit.
     SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
 
     SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
                             int &RefinementSteps, bool &UseOneConstNR,

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
   setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
   setTargetDAGCombine(ISD::INTRINSIC_VOID);
 
   setTargetDAGCombine(ISD::SIGN_EXTEND);
   setTargetDAGCombine(ISD::ZERO_EXTEND);
   setTargetDAGCombine(ISD::ANY_EXTEND);
 
   setTargetDAGCombine(ISD::TRUNCATE);
+  setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
+
 
   if (Subtarget.useCRBits()) {
     setTargetDAGCombine(ISD::TRUNCATE);
     setTargetDAGCombine(ISD::SETCC);
     setTargetDAGCombine(ISD::SELECT_CC);
   }
 
   // Use reciprocal estimates.
const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case PPCISD::LFIWAX:          return "PPCISD::LFIWAX";
   case PPCISD::LFIWZX:          return "PPCISD::LFIWZX";
   case PPCISD::LXSIZX:          return "PPCISD::LXSIZX";
   case PPCISD::STXSIX:          return "PPCISD::STXSIX";
   case PPCISD::VEXTS:           return "PPCISD::VEXTS";
   case PPCISD::SExtVElems:      return "PPCISD::SExtVElems";
   case PPCISD::LXVD2X:          return "PPCISD::LXVD2X";
   case PPCISD::STXVD2X:         return "PPCISD::STXVD2X";
+  case PPCISD::LOAD_VEC_BE:     return "PPCISD::LOAD_VEC_BE";
+  case PPCISD::STORE_VEC_BE:    return "PPCISD::STORE_VEC_BE";
   case PPCISD::ST_VSR_SCAL_INT:
                                 return "PPCISD::ST_VSR_SCAL_INT";
   case PPCISD::COND_BRANCH:     return "PPCISD::COND_BRANCH";
   case PPCISD::BDNZ:            return "PPCISD::BDNZ";
   case PPCISD::BDZ:             return "PPCISD::BDZ";
   case PPCISD::MFFS:            return "PPCISD::MFFS";
   case PPCISD::FADDRTZ:         return "PPCISD::FADDRTZ";
   case PPCISD::TC_RETURN:       return "PPCISD::TC_RETURN";
Val = DAG.getMemIntrinsicNode(PPCISD::ST_VSR_SCAL_INT, dl,
           DAG.getVTList(MVT::Other), Ops,
           cast<StoreSDNode>(N)->getMemoryVT(),
           cast<StoreSDNode>(N)->getMemOperand());
 
   DCI.AddToWorklist(Val.getNode());
   return Val;
 }
 
+SDValue PPCTargetLowering::combineVReverseMemOP(ShuffleVectorSDNode *SVN,
+                                                LSBaseSDNode *LSBase,
+                                                DAGCombinerInfo &DCI) const {
+  assert((ISD::isNormalLoad(LSBase) || ISD::isNormalStore(LSBase)) &&
+        "Not a reverse memop pattern!");
+
+  auto IsElementReverse = [](const ShuffleVectorSDNode *SVN) -> bool {
+    auto Mask = SVN->getMask();
+    int i = 0;
+    auto I = Mask.rbegin();
+    auto E = Mask.rend();
+
+    for (; I != E; ++I) {
+      if (*I != i)
+        return false;
+      i++;
+    }
+    return true;
+  };
+
+  SelectionDAG &DAG = DCI.DAG;
+  EVT VT = SVN->getValueType(0);
+
+  if (!isTypeLegal(VT) || !Subtarget.isLittleEndian() || !Subtarget.hasVSX())
+    return SDValue();
+
+  // Before P9, we have PPCVSXSwapRemoval pass to hack the element order.
+  // See comment in PPCVSXSwapRemoval.cpp.
+  // It is conflict with PPCVSXSwapRemoval opt. So we don't do it.
+  if (!Subtarget.hasP9Vector())
+    return SDValue();
+
+  if(!IsElementReverse(SVN))
+    return SDValue();
+
+  if (LSBase->getOpcode() == ISD::LOAD) {
+    SDLoc dl(SVN);
+    SDValue LoadOps[] = {LSBase->getChain(), LSBase->getBasePtr()};
+    return DAG.getMemIntrinsicNode(
+        PPCISD::LOAD_VEC_BE, dl, DAG.getVTList(VT, MVT::Other), LoadOps,
+        LSBase->getMemoryVT(), LSBase->getMemOperand());
+  }
+
+  if (LSBase->getOpcode() == ISD::STORE) {
+    SDLoc dl(LSBase);
+    SDValue StoreOps[] = {LSBase->getChain(), SVN->getOperand(0),
+                          LSBase->getBasePtr()};
+    return DAG.getMemIntrinsicNode(
+        PPCISD::STORE_VEC_BE, dl, DAG.getVTList(MVT::Other), StoreOps,
+        LSBase->getMemoryVT(), LSBase->getMemOperand());
+  }
+
+  llvm_unreachable("Expected a load or store node here");
+}
+
 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
                                              DAGCombinerInfo &DCI) const {
   SelectionDAG &DAG = DCI.DAG;
   SDLoc dl(N);
   switch (N->getOpcode()) {
   default: break;
   case ISD::ADD:
     return combineADD(N, DCI);
case ISD::SETCC:
     if (SDValue CSCC = combineSetCC(N, DCI))
       return CSCC;
     LLVM_FALLTHROUGH;
   case ISD::SELECT_CC:
     return DAGCombineTruncBoolExt(N, DCI);
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP:
     return combineFPToIntToFP(N, DCI);
+  case ISD::VECTOR_SHUFFLE:
+    if (ISD::isNormalLoad(N->getOperand(0).getNode())) {
+      LSBaseSDNode* LSBase = cast<LSBaseSDNode>(N->getOperand(0));
+      return combineVReverseMemOP(cast<ShuffleVectorSDNode>(N), LSBase, DCI);
+    }
+    break;
   case ISD::STORE: {
 
     EVT Op1VT = N->getOperand(1).getValueType();
     unsigned Opcode = N->getOperand(1).getOpcode();
 
     if (Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT) {
       SDValue Val= combineStoreFPToInt(N, DCI);
       if (Val)
         return Val;
     }
 
+    if (Opcode == ISD::VECTOR_SHUFFLE && ISD::isNormalStore(N)) {
+      ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N->getOperand(1));
+      SDValue Val= combineVReverseMemOP(SVN, cast<LSBaseSDNode>(N), DCI);
+      if (Val)
+        return Val;
+    }
+
     // Turn STORE (BSWAP) -> sthbrx/stwbrx.
     if (cast<StoreSDNode>(N)->isUnindexed() && Opcode == ISD::BSWAP &&
         N->getOperand(1).getNode()->hasOneUse() &&
         (Op1VT == MVT::i32 || Op1VT == MVT::i16 ||
          (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) {
 
       // STBRX can only handle simple types and it makes no sense to store less
       // two bytes in byte-reversed order.

llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td

def SDT_PPCxxswapd : SDTypeProfile<1, 1, [
   SDTCisSameAs<0, 1>
 ]>;
 def SDTVecConv : SDTypeProfile<1, 2, [
   SDTCisVec<0>, SDTCisVec<1>, SDTCisPtrTy<2>
 ]>;
 def SDTVabsd : SDTypeProfile<1, 3, [
   SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<3, i32>
 ]>;
-
+def SDT_PPCld_vec_be : SDTypeProfile<1, 1, [
+  SDTCisVec<0>, SDTCisPtrTy<1>
+]>;
+def SDT_PPCst_vec_be : SDTypeProfile<0, 2, [
+  SDTCisVec<0>, SDTCisPtrTy<1>
+]>;
 
 def PPClxvd2x  : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x,
                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x,
                         [SDNPHasChain, SDNPMayStore]>;
+def PPCld_vec_be  : SDNode<"PPCISD::LOAD_VEC_BE", SDT_PPCld_vec_be,
+                        [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+def PPCst_vec_be : SDNode<"PPCISD::STORE_VEC_BE", SDT_PPCst_vec_be,
+                        [SDNPHasChain, SDNPMayStore]>;
 def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>;
 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
 def PPCmtvsra : SDNode<"PPCISD::MTVSRA", SDTUnaryOp, []>;
 def PPCmtvsrz : SDNode<"PPCISD::MTVSRZ", SDTUnaryOp, []>;
 def PPCsvec2fp : SDNode<"PPCISD::SINT_VEC_TO_FP", SDTVecConv, []>;
 def PPCuvec2fp: SDNode<"PPCISD::UINT_VEC_TO_FP", SDTVecConv, []>;
 def PPCswapNoChain : SDNode<"PPCISD::SWAP_NO_CHAIN", SDT_PPCxxswapd>;
 def PPCvabsd : SDNode<"PPCISD::VABSD", SDTVabsd, []>;

 let Predicates = [HasVSX, HasOnlySwappingMemOps] in {
   def : Pat<(v2f64 (PPClxvd2x xoaddr:$src)), (LXVD2X xoaddr:$src)>;
 
   // Stores.
   def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst),
             (STXVD2X $rS, xoaddr:$dst)>;
   def : Pat<(PPCstxvd2x v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
 }
+
+// Load vector big endian order
+let Predicates = [IsLittleEndian, HasVSX] in {
+  def : Pat<(v2f64 (PPCld_vec_be xoaddr:$src)), (LXVD2X xoaddr:$src)>;
+  def : Pat<(PPCst_vec_be v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
+  def : Pat<(v4f32 (PPCld_vec_be xoaddr:$src)), (LXVW4X xoaddr:$src)>;
+  def : Pat<(PPCst_vec_be v4f32:$rS, xoaddr:$dst), (STXVW4X $rS, xoaddr:$dst)>;
+  def : Pat<(v2i64 (PPCld_vec_be xoaddr:$src)), (LXVD2X xoaddr:$src)>;
+  def : Pat<(PPCst_vec_be v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
+  def : Pat<(v4i32 (PPCld_vec_be xoaddr:$src)), (LXVW4X xoaddr:$src)>;
+  def : Pat<(PPCst_vec_be v4i32:$rS, xoaddr:$dst), (STXVW4X $rS, xoaddr:$dst)>;
+}
+
 let Predicates = [IsBigEndian, HasVSX, HasOnlySwappingMemOps] in {
   def : Pat<(v2f64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
   def : Pat<(v2i64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
   def : Pat<(v4i32 (load xoaddr:$src)), (LXVW4X xoaddr:$src)>;
   def : Pat<(v4i32 (int_ppc_vsx_lxvw4x xoaddr:$src)), (LXVW4X xoaddr:$src)>;
   def : Pat<(store v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
   def : Pat<(store v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
   def : Pat<(store v4i32:$XT, xoaddr:$dst), (STXVW4X $XT, xoaddr:$dst)>;
let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)),
             (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>;
   def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)),
             (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>;
   def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)),
             (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>;
   def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)),
             (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>;
+
+  def : Pat<(v8i16 (PPCld_vec_be xoaddr:$src)),
+            (COPY_TO_REGCLASS (LXVH8X xoaddr:$src), VRRC)>;
+  def : Pat<(PPCst_vec_be v8i16:$rS, xoaddr:$dst),
+            (STXVH8X (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$dst)>;
+
+  def : Pat<(v16i8 (PPCld_vec_be xoaddr:$src)),
+            (COPY_TO_REGCLASS (LXVB16X xoaddr:$src), VRRC)>;
+  def : Pat<(PPCst_vec_be v16i8:$rS, xoaddr:$dst),
+            (STXVB16X (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$dst)>;
   } // IsLittleEndian, HasP9Vector
 
   let Predicates = [IsBigEndian, HasP9Vector] in {
   def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
             (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>;
   def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
             (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>;
   def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),

llvm/trunk/test/CodeGen/PowerPC/build-vector-tests.ll

 ; P9BE-NEXT:    addis r3, r2, .LCPI8_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI8_0@toc@l
 ; P9BE-NEXT:    lxvx v3, 0, r3
 ; P9BE-NEXT:    vperm v2, v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDi:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    lxv v2, 0(r3)
-; P9LE-NEXT:    addis r3, r2, .LCPI8_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI8_0@toc@l
-; P9LE-NEXT:    lxvx v3, 0, r3
-; P9LE-NEXT:    vperm v2, v2, v2, v3
+; P9LE-NEXT:    lxvw4x v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDi:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addis r4, r2, .LCPI8_0@toc@ha
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    addi r4, r4, .LCPI8_0@toc@l
 ; P8BE-NEXT:    lxvw4x v3, 0, r4

 ; P9BE-NEXT:    addis r3, r2, .LCPI41_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI41_0@toc@l
 ; P9BE-NEXT:    lxvx v3, 0, r3
 ; P9BE-NEXT:    vperm v2, v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDui:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    lxv v2, 0(r3)
-; P9LE-NEXT:    addis r3, r2, .LCPI41_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI41_0@toc@l
-; P9LE-NEXT:    lxvx v3, 0, r3
-; P9LE-NEXT:    vperm v2, v2, v2, v3
+; P9LE-NEXT:    lxvw4x v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDui:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addis r4, r2, .LCPI41_0@toc@ha
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    addi r4, r4, .LCPI41_0@toc@l
 ; P8BE-NEXT:    lxvw4x v3, 0, r4

 ; P9BE-LABEL: fromDiffMemConsDll:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lxv v2, 16(r3)
 ; P9BE-NEXT:    xxswapd v2, v2
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDll:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    lxv v2, 16(r3)
-; P9LE-NEXT:    xxswapd v2, v2
+; P9LE-NEXT:    addi r3, r3, 16
+; P9LE-NEXT:    lxvd2x v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDll:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 16
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    xxswapd v2, v2
 ; P8BE-NEXT:    blr

 ; P9BE-NEXT:    lxvx v2, r3, r4
 ; P9BE-NEXT:    xxswapd v2, v2
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemVarDll:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r4, 3
 ; P9LE-NEXT:    add r3, r3, r4
-; P9LE-NEXT:    li r4, -8
-; P9LE-NEXT:    lxvx v2, r3, r4
-; P9LE-NEXT:    xxswapd v2, v2
+; P9LE-NEXT:    addi r3, r3, -8
+; P9LE-NEXT:    lxvd2x v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemVarDll:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r4, 3
 ; P8BE-NEXT:    add r3, r3, r4
 ; P8BE-NEXT:    addi r3, r3, -8
 ; P8BE-NEXT:    lxvd2x v2, 0, r3

 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lxv vs0, 16(r3)
 ; P9BE-NEXT:    xxswapd vs0, vs0
 ; P9BE-NEXT:    xvcvdpsxds v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDConvdtoll:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    lxv vs0, 16(r3)
-; P9LE-NEXT:    xxswapd vs0, vs0
+; P9LE-NEXT:    addi r3, r3, 16
+; P9LE-NEXT:    lxvd2x vs0, 0, r3
 ; P9LE-NEXT:    xvcvdpsxds v2, vs0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDConvdtoll:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 16
 ; P8BE-NEXT:    lxvd2x vs0, 0, r3
 ; P8BE-NEXT:    xxswapd vs0, vs0

 ; P9BE-NEXT:    xxswapd vs0, vs0
 ; P9BE-NEXT:    xvcvdpsxds v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemVarDConvdtoll:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r4, 3
 ; P9LE-NEXT:    add r3, r3, r4
-; P9LE-NEXT:    li r4, -8
-; P9LE-NEXT:    lxvx vs0, r3, r4
-; P9LE-NEXT:    xxswapd vs0, vs0
+; P9LE-NEXT:    addi r3, r3, -8
+; P9LE-NEXT:    lxvd2x vs0, 0, r3
 ; P9LE-NEXT:    xvcvdpsxds v2, vs0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemVarDConvdtoll:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r4, 3
 ; P8BE-NEXT:    add r3, r3, r4
 ; P8BE-NEXT:    addi r3, r3, -8

 ; P9BE-LABEL: fromDiffMemConsDull:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lxv v2, 16(r3)
 ; P9BE-NEXT:    xxswapd v2, v2
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDull:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    lxv v2, 16(r3)
-; P9LE-NEXT:    xxswapd v2, v2
+; P9LE-NEXT:    addi r3, r3, 16
+; P9LE-NEXT:    lxvd2x v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDull:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 16
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    xxswapd v2, v2
 ; P8BE-NEXT:    blr

 ; P9BE-NEXT:    lxvx v2, r3, r4
 ; P9BE-NEXT:    xxswapd v2, v2
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemVarDull:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r4, 3
 ; P9LE-NEXT:    add r3, r3, r4
-; P9LE-NEXT:    li r4, -8
-; P9LE-NEXT:    lxvx v2, r3, r4
-; P9LE-NEXT:    xxswapd v2, v2
+; P9LE-NEXT:    addi r3, r3, -8
+; P9LE-NEXT:    lxvd2x v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemVarDull:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r4, 3
 ; P8BE-NEXT:    add r3, r3, r4
 ; P8BE-NEXT:    addi r3, r3, -8
 ; P8BE-NEXT:    lxvd2x v2, 0, r3

 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lxv vs0, 16(r3)
 ; P9BE-NEXT:    xxswapd vs0, vs0
 ; P9BE-NEXT:    xvcvdpuxds v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDConvdtoull:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    lxv vs0, 16(r3)
-; P9LE-NEXT:    xxswapd vs0, vs0
+; P9LE-NEXT:    addi r3, r3, 16
+; P9LE-NEXT:    lxvd2x vs0, 0, r3
 ; P9LE-NEXT:    xvcvdpuxds v2, vs0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDConvdtoull:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 16
 ; P8BE-NEXT:    lxvd2x vs0, 0, r3
 ; P8BE-NEXT:    xxswapd vs0, vs0

 ; P9BE-NEXT:    xxswapd vs0, vs0
 ; P9BE-NEXT:    xvcvdpuxds v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemVarDConvdtoull:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r4, 3
 ; P9LE-NEXT:    add r3, r3, r4
-; P9LE-NEXT:    li r4, -8
-; P9LE-NEXT:    lxvx vs0, r3, r4
-; P9LE-NEXT:    xxswapd vs0, vs0
+; P9LE-NEXT:    addi r3, r3, -8
+; P9LE-NEXT:    lxvd2x vs0, 0, r3
 ; P9LE-NEXT:    xvcvdpuxds v2, vs0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemVarDConvdtoull:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r4, 3
 ; P8BE-NEXT:    add r3, r3, r4
 ; P8BE-NEXT:    addi r3, r3, -8

llvm/trunk/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll

 define <2 x i64> @load_swap00(<2 x i64>* %vp1, <2 x i64>* %vp2) {
 ; CHECK-P8-LABEL: load_swap00:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap00:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    lxv v2, 0(r3)
-; CHECK-P9-NEXT:    xxswapd v2, v2
+; CHECK-P9-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap00:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-P8-BE-NEXT:    xxswapd v2, v2
 ; CHECK-P8-BE-NEXT:    blr
 ;

 define <2 x i64> @load_swap01(<2 x i64>* %vp1, <2 x i64>* %vp2) {
 ; CHECK-P8-LABEL: load_swap01:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    lxvd2x v2, 0, r4
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap01:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    lxv v2, 0(r4)
-; CHECK-P9-NEXT:    xxswapd v2, v2
+; CHECK-P9-NEXT:    lxvd2x v2, 0, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap01:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    lxvd2x v2, 0, r4
 ; CHECK-P8-BE-NEXT:    xxswapd v2, v2
 ; CHECK-P8-BE-NEXT:    blr
 ;

 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI2_0@toc@l
 ; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap10:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    lxv v2, 0(r3)
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-P9-NEXT:    lxvx v3, 0, r3
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap10:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P8-BE-NEXT:    addi r4, r4, .LCPI2_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r4

 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI3_0@toc@l
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap11:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-P9-NEXT:    lxv v2, 0(r4)
-; CHECK-P9-NEXT:    lxvx v3, 0, r3
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-NEXT:    lxvw4x v2, 0, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap11:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r4
 ; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3

 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI4_0@toc@l
 ; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap20:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    lxv v2, 0(r3)
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-P9-NEXT:    lxvx v3, 0, r3
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-NEXT:    lxvh8x v2, 0, r3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap20:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r4, r2, .LCPI4_0@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P8-BE-NEXT:    addi r4, r4, .LCPI4_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r4

 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI5_0@toc@l
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap21:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-P9-NEXT:    lxv v2, 0(r4)
-; CHECK-P9-NEXT:    lxvx v3, 0, r3
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-NEXT:    lxvh8x v2, 0, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap21:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r4
 ; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3

 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI6_0@toc@l
 ; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap30:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    lxv vs0, 0(r3)
-; CHECK-P9-NEXT:    xxbrq v2, vs0
+; CHECK-P9-NEXT:    lxvb16x v2, 0, r3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap30:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P8-BE-NEXT:    addi r4, r4, .LCPI6_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r4

 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI7_0@toc@l
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap31:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    lxv vs0, 0(r4)
-; CHECK-P9-NEXT:    xxbrq v2, vs0
+; CHECK-P9-NEXT:    lxvb16x v2, 0, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap31:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r4
 ; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI7_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3

 define <2 x double> @load_swap40(<2 x double>* %vp1, <2 x double>* %vp2) {
 ; CHECK-P8-LABEL: load_swap40:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    lxvd2x v2, 0, r4
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap40:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    lxv vs0, 0(r4)
-; CHECK-P9-NEXT:    xxswapd v2, vs0
+; CHECK-P9-NEXT:    lxvd2x v2, 0, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap40:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-BE-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-BE-NEXT:    blr
 ;

 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI9_0@toc@l
 ; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap50:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    lxv v2, 0(r3)
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI9_0@toc@l
-; CHECK-P9-NEXT:    lxvx v3, 0, r3
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap50:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r4, r2, .LCPI9_0@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P8-BE-NEXT:    addi r4, r4, .LCPI9_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r4

 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI10_0@toc@l
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap51:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI10_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI10_0@toc@l
-; CHECK-P9-NEXT:    lxv v2, 0(r4)
-; CHECK-P9-NEXT:    lxvx v3, 0, r3
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-NEXT:    lxvw4x v2, 0, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap51:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI10_0@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r4
 ; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI10_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3

 define void @swap_store00(<2 x i64> %v1, <2 x i64> %v2, <2 x i64>* %vp) {
 ; CHECK-P8-LABEL: swap_store00:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    stxvd2x v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store00:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    xxswapd vs0, v2
-; CHECK-P9-NEXT:    stxv vs0, 0(r7)
+; CHECK-P9-NEXT:    stxvd2x v2, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store00:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-BE-NEXT:    stxvd2x vs0, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;

 define void @swap_store01(<2 x i64> %v1, <2 x i64> %v2, <2 x i64>* %vp) {
 ; CHECK-P8-LABEL: swap_store01:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    stxvd2x v3, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store01:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    xxswapd vs0, v3
-; CHECK-P9-NEXT:    stxv vs0, 0(r7)
+; CHECK-P9-NEXT:    stxvd2x v3, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store01:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    xxswapd vs0, v3
 ; CHECK-P8-BE-NEXT:    stxvd2x vs0, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;

 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI13_0@toc@l
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store10:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI13_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI13_0@toc@l
-; CHECK-P9-NEXT:    lxvx v3, 0, r3
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
-; CHECK-P9-NEXT:    stxv v2, 0(r7)
+; CHECK-P9-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store10:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI13_0@toc@ha
 ; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI13_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3

 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI14_0@toc@l
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store11:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI14_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI14_0@toc@l
-; CHECK-P9-NEXT:    lxvx v2, 0, r3
-; CHECK-P9-NEXT:    vperm v2, v3, v3, v2
-; CHECK-P9-NEXT:    stxv v2, 0(r7)
+; CHECK-P9-NEXT:    stxvw4x v3, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store11:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI14_0@toc@ha
 ; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI14_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v3, v3, v2

 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI15_0@toc@l
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store20:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI15_0@toc@l
-; CHECK-P9-NEXT:    lxvx v3, 0, r3
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
-; CHECK-P9-NEXT:    stxv v2, 0(r7)
+; CHECK-P9-NEXT:    stxvh8x v2, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store20:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
 ; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI15_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3

 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI16_0@toc@l
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store21:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI16_0@toc@l
-; CHECK-P9-NEXT:    lxvx v2, 0, r3
-; CHECK-P9-NEXT:    vperm v2, v3, v3, v2
-; CHECK-P9-NEXT:    stxv v2, 0(r7)
+; CHECK-P9-NEXT:    stxvh8x v3, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store21:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
 ; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI16_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v3, v3, v2

 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI17_0@toc@l
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store30:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    xxbrq vs0, v2
-; CHECK-P9-NEXT:    stxv vs0, 0(r7)
+; CHECK-P9-NEXT:    stxvb16x v2, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store30:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI17_0@toc@ha
 ; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI17_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3

 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI18_0@toc@l
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store31:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    xxbrq vs0, v3
-; CHECK-P9-NEXT:    stxv vs0, 0(r7)
+; CHECK-P9-NEXT:    stxvb16x v3, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store31:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI18_0@toc@ha
 ; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI18_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v3, v3, v2

 define void @swap_store40(<2 x double> %v1, <2 x double> %v2, <2 x double>* %vp) {
 ; CHECK-P8-LABEL: swap_store40:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    stxvd2x v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store40:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    xxswapd vs0, v2
-; CHECK-P9-NEXT:    stxv vs0, 0(r7)
+; CHECK-P9-NEXT:    stxvd2x v2, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store40:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-BE-NEXT:    stxvd2x vs0, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;

 define void @swap_store41(<2 x double> %v1, <2 x double> %v2, <2 x double>* %vp) {
 ; CHECK-P8-LABEL: swap_store41:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    stxvd2x v3, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store41:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    xxswapd vs0, v3
-; CHECK-P9-NEXT:    stxv vs0, 0(r7)
+; CHECK-P9-NEXT:    stxvd2x v3, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store41:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    xxswapd vs0, v3
 ; CHECK-P8-BE-NEXT:    stxvd2x vs0, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;

 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI21_0@toc@l
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store50:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI21_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI21_0@toc@l
-; CHECK-P9-NEXT:    lxvx v3, 0, r3
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
-; CHECK-P9-NEXT:    stxv v2, 0(r7)
+; CHECK-P9-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store50:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI21_0@toc@ha
 ; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI21_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3

 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI22_0@toc@l
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store51:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI22_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI22_0@toc@l
-; CHECK-P9-NEXT:    lxvx v2, 0, r3
-; CHECK-P9-NEXT:    vperm v2, v3, v3, v2
-; CHECK-P9-NEXT:    stxv v2, 0(r7)
+; CHECK-P9-NEXT:    stxvw4x v3, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store51:
 ; CHECK-P8-BE:       # %bb.0:
 ; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI22_0@toc@ha
 ; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI22_0@toc@l
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v3, v3, v2

llvm/trunk/test/CodeGen/PowerPC/vsx_shuffle_le.ll

define <2 x double> @test10(<2 x double>* %p1, <2 x double>* %p2) {
   %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 1, i32 0>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test10
 ; CHECK: lxvd2x 34, 0, 3
 
 ; CHECK-P9-LABEL: @test10
-; CHECK-P9: lxv 0, 0(3)
-; CHECK-P9: xxswapd 34, 0
+; CHECK-P9: lxvd2x 34, 0, 3
 }
 
 define <2 x double> @test11(<2 x double>* %p1, <2 x double>* %p2) {
   %v1 = load <2 x double>, <2 x double>* %p1
   %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 1, i32 1>
   ret <2 x double> %v3
 
define <2 x double> @test32(<2 x double>* %p1, <2 x double>* %p2) {
   %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 3, i32 2>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test32
 ; CHECK: lxvd2x 34, 0, 4
 
 ; CHECK-P9-LABEL: @test32
-; CHECK-P9: lxv 0, 0(4)
-; CHECK-P9: xxswapd 34, 0
+; CHECK-P9: lxvd2x 34, 0, 4
 }
 
 define <2 x double> @test33(<2 x double>* %p1, <2 x double>* %p2) {
   %v1 = load <2 x double>, <2 x double>* %p1
   %v2 = load <2 x double>, <2 x double>* %p2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 3, i32 3>
   ret <2 x double> %v3
 
 ; CHECK-LABEL: @test33
 ; CHECK: lxvd2x 0, 0, 4
 ; CHECK: xxspltd 34, 0, 1
 
 ; CHECK-P9-LABEL: @test33
 ; CHECK-P9: lxv 0, 0(4)
 ; CHECK-P9: xxspltd 34, 0, 0
 }