[AMDGPU] fixed scheduler crash in gfx908

[rampitec]

Summary

For some reason scheduler can send down an SUnit without an
instruction.

[kerbowa]

lib/Target/AMDGPU/AMDGPUSubtarget.cpp

769

There is SUnit::isInstr() also

[rampitec]

lib/Target/AMDGPU/AMDGPUSubtarget.cpp

769

It's actually very strange to see anything but MI in the PostRA scheduler.

[kerbowa]

lib/Target/AMDGPU/AMDGPUSubtarget.cpp

769

Yeah I just meant as a null check.

[rampitec]

lib/Target/AMDGPU/AMDGPUSubtarget.cpp

769

Same thing, but a little bit more source ;)

[rampitec]

Added test.

[arsenm]

Where does the null come from exactly?

[rampitec]

In D64709#1585639, @arsenm wrote:

Where does the null come from exactly?

It is in the list of all dag nodes, somehow dag builder put it there. I suspect that this is for scheduling barrier. The node is neither MI nor SDNode (obviously), just plain zero initialized.

[arsenm]

I vaguely remember this being how nops are represented, and one does seem to have been inserted

lib/Target/AMDGPU/AMDGPUSubtarget.cpp

 struct FillMFMAShadowMutation : ScheduleDAGMutation {
   const SIInstrInfo *TII;
 
   ScheduleDAGMI *DAG;
 
   FillMFMAShadowMutation(const SIInstrInfo *tii) : TII(tii) {}
 
   bool isSALU(const SUnit *SU) const {
-    const MachineInstr &MI = *SU->getInstr();
-    return TII->isSALU(MI) && !MI.isTerminator();
+    const MachineInstr *MI = SU->getInstr();
+    return MI && TII->isSALU(*MI) && !MI->isTerminator();
   }
 
   bool canAddEdge(const SUnit *Succ, const SUnit *Pred) const {
     if (Pred->NodeNum < Succ->NodeNum)
       return true;
 
     SmallVector<const SUnit*, 64> Succs({Succ}), Preds({Pred});