Move three folds for FADD, FSUB and FMUL in the DAG combiner away from Unsafe to more aligned checks that reflect context

[mcberg2017]

Summary

Unsafe does not map well alone for each of these three cases as it is missing NoNan context when accessed directly with clang. I have migrated the fold guards to reflect the expectations of handing nan and zero contexts directly (NoNan, NSZ) and some tests with it. Unsafe does include NSZ, however there is already precedent for using the target option directly to reflect that context.

[arsenm]

LGTM

[lebedev.ri]

For future reference, this patch omitted llvm-commits list, looks like phabricator still
sometimes doesn't automatically does the right thing, so one needs to manually ensure that.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (isFMulNegTwo(N1)) {
     SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B, Flags);
     return DAG.getNode(ISD::FSUB, DL, VT, N0, Add, Flags);
   }
 
   // No FP constant should be created after legalization as Instruction
   // Selection pass has a hard time dealing with FP constants.
   bool AllowNewConst = (Level < AfterLegalizeDAG);
 
-  // If 'unsafe math' or nnan is enabled, fold lots of things.
-  if ((Options.UnsafeFPMath || Flags.hasNoNaNs()) && AllowNewConst) {
+  // If nnan is enabled, fold lots of things.
+  if ((Options.NoNaNsFPMath || Flags.hasNoNaNs()) && AllowNewConst) {
     // If allowed, fold (fadd (fneg x), x) -> 0.0
     if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
       return DAG.getConstantFP(0.0, DL, VT);
 
     // If allowed, fold (fadd x, (fneg x)) -> 0.0
     if (N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
       return DAG.getConstantFP(0.0, DL, VT);
   }
if (N1CFP && N1CFP->isZero()) {
     if (!N1CFP->isNegative() || Options.UnsafeFPMath ||
         Flags.hasNoSignedZeros()) {
       return N0;
     }
   }
 
   if (N0 == N1) {
     // (fsub x, x) -> 0.0
-    if (Options.UnsafeFPMath || Flags.hasNoNaNs())
+    if (Options.NoNaNsFPMath || Flags.hasNoNaNs())
       return DAG.getConstantFP(0.0f, DL, VT);
   }
 
   // (fsub -0.0, N1) -> -N1
   // NOTE: It is safe to transform an FSUB(-0.0,X) into an FNEG(X), since the
   //       FSUB does not specify the sign bit of a NaN. Also note that for
   //       the same reason, the inverse transform is not safe, unless fast math
   //       flags are in play.
SDValue DAGCombiner::visitFMUL(SDNode *N) {
 
   // fold (fmul A, 1.0) -> A
   if (N1CFP && N1CFP->isExactlyValue(1.0))
     return N0;
 
   if (SDValue NewSel = foldBinOpIntoSelect(N))
     return NewSel;
 
-  if (Options.UnsafeFPMath ||
+  if ((Options.NoNaNsFPMath && Options.NoSignedZerosFPMath) ||
       (Flags.hasNoNaNs() && Flags.hasNoSignedZeros())) {
     // fold (fmul A, 0) -> 0
     if (N1CFP && N1CFP->isZero())
       return N1;
   }
 
   if (Options.UnsafeFPMath || Flags.hasAllowReassociation()) {
     // fmul (fmul X, C1), C2 -> fmul X, C1 * C2

test/CodeGen/ARM/nnan-fsub.ll

 ; RUN: llc -mcpu=cortex-a9 < %s | FileCheck -check-prefix=SAFE %s
-; RUN: llc -mcpu=cortex-a9 -enable-unsafe-fp-math < %s | FileCheck -check-prefix=FAST %s
+; RUN: llc -mcpu=cortex-a9 --enable-no-nans-fp-math < %s | FileCheck -check-prefix=FAST %s
 
 target triple = "armv7-apple-ios"
 
 ; SAFE: test
 ; FAST: test
 define float @test(float %x, float %y) {
 entry:
 ; SAFE: vmul.f32
 ; SAFE: vsub.f32
 ; FAST: mov r0, #0
   %0 = fmul float %x, %y
   %1 = fsub float %0, %0
   ret float %1
 }
 
 

test/CodeGen/ARM/unsafe-fsub.ll

-; RUN: llc -mcpu=cortex-a9 < %s | FileCheck -check-prefix=SAFE %s
-; RUN: llc -mcpu=cortex-a9 -enable-unsafe-fp-math < %s | FileCheck -check-prefix=FAST %s
-
-target triple = "armv7-apple-ios"
-
-; SAFE: test
-; FAST: test
-define float @test(float %x, float %y) {
-entry:
-; SAFE: vmul.f32
-; SAFE: vsub.f32
-; FAST: mov r0, #0
-  %0 = fmul float %x, %y
-  %1 = fsub float %0, %0
-  ret float %1
-}
-
-

test/CodeGen/X86/fmul-combines.ll

 ; CHECK-LABEL: constant_fold_fmul_v4f32_undef:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movaps {{.*#+}} xmm0 = [8.0E+0,NaN,8.0E+0,NaN]
 ; CHECK-NEXT:    retq
   %y = fmul <4 x float> <float 4.0, float undef, float 4.0, float 4.0>, <float 2.0, float 2.0, float 2.0, float undef>
   ret <4 x float> %y
 }
 
-define <4 x float> @fmul0_v4f32(<4 x float> %x) #0 {
-; CHECK-LABEL: fmul0_v4f32:
+define <4 x float> @fmul0_v4f32_nsz_nnan(<4 x float> %x) #0 {
+; CHECK-LABEL: fmul0_v4f32_nsz_nnan:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-  %y = fmul <4 x float> %x, <float 0.0, float 0.0, float 0.0, float 0.0>
+  %y = fmul nnan nsz <4 x float> %x, <float 0.0, float 0.0, float 0.0, float 0.0>
   ret <4 x float> %y
 }
 
 define <4 x float> @fmul0_v4f32_undef(<4 x float> %x) #0 {
 ; CHECK-LABEL: fmul0_v4f32_undef:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
-  %y = fmul <4 x float> %x, <float undef, float 0.0, float undef, float 0.0>
+  %y = fmul nnan nsz <4 x float> %x, <float undef, float 0.0, float undef, float 0.0>
   ret <4 x float> %y
 }
 
 define <4 x float> @fmul_c2_c4_v4f32(<4 x float> %x) #0 {
 ; CHECK-LABEL: fmul_c2_c4_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mulps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq

test/CodeGen/X86/fp-fast.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx -enable-unsafe-fp-math < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx -enable-unsafe-fp-math --enable-no-nans-fp-math < %s | FileCheck %s
 
 define float @test1(float %a) {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %t1 = fadd float %a, %a
   %r = fadd float %t1, %t1