[ARM] Relax constraints on operands of VQxDMLxDH instructions

[miyuki]

Summary

According to a recently updated Armv8-M spec
(https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf) the
32-bit width versions of the following instructions:

• VQDMLADH
• VQDMLADHX
• VQRDMLADH
• VQRDMLADHX
• VQDMLSDH
• VQDMLSDHX
• VQRDMLSDH
• VQRDMLSDHX

are no longer unpredictable when their output register is the same as
one of the input registers.

This patch updates the assembler parser and the corresponding tests
and also removes @earlyclobber from the instruction constraints.

llvm/trunk/lib/Target/ARM/ARMInstrMVE.td

class MVE_qDest_qSrc<string iname, string suffix, dag oops, dag iops,
   let Inst{11-9} = 0b111;
   let Inst{6} = 0b0;
   let Inst{5} = Qm{3};
   let Inst{4} = 0b0;
   let Inst{3-1} = Qm{2-0};
 }
 
 class MVE_VQxDMLxDH<string iname, bit exch, bit round, bit subtract,
-                    string suffix, bits<2> size, bit earlyclobber,
-                    list<dag> pattern=[]>
+                    string suffix, bits<2> size, list<dag> pattern=[]>
   : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
                    (ins MQPR:$Qd_src, MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
-                   vpred_n,
-                   !if(earlyclobber, "@earlyclobber $Qd,", "") # "$Qd = $Qd_src",
-                   pattern> {
+                   vpred_n, "$Qd = $Qd_src", pattern> {
   bits<4> Qn;
 
   let Inst{28} = subtract;
   let Inst{21-20} = size;
   let Inst{19-17} = Qn{2-0};
   let Inst{16} = 0b0;
   let Inst{12} = exch;
   let Inst{8} = 0b0;
   let Inst{7} = Qn{3};
   let Inst{0} = round;
 }
 
 multiclass MVE_VQxDMLxDH_multi<string iname, bit exch,
                                bit round, bit subtract> {
-  def s8  : MVE_VQxDMLxDH<iname, exch, round, subtract, "s8",  0b00, 0b0>;
-  def s16 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s16", 0b01, 0b0>;
-  def s32 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s32", 0b10, 0b1>;
+  def s8  : MVE_VQxDMLxDH<iname, exch, round, subtract, "s8",  0b00>;
+  def s16 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s16", 0b01>;
+  def s32 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s32", 0b10>;
 }
 
 defm MVE_VQDMLADH   : MVE_VQxDMLxDH_multi<"vqdmladh",   0b0, 0b0, 0b0>;
 defm MVE_VQDMLADHX  : MVE_VQxDMLxDH_multi<"vqdmladhx",  0b1, 0b0, 0b0>;
 defm MVE_VQRDMLADH  : MVE_VQxDMLxDH_multi<"vqrdmladh",  0b0, 0b1, 0b0>;
 defm MVE_VQRDMLADHX : MVE_VQxDMLxDH_multi<"vqrdmladhx", 0b1, 0b1, 0b0>;
 defm MVE_VQDMLSDH   : MVE_VQxDMLxDH_multi<"vqdmlsdh",   0b0, 0b0, 0b1>;
 defm MVE_VQDMLSDHX  : MVE_VQxDMLxDH_multi<"vqdmlsdhx",  0b1, 0b0, 0b1>;

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

case ARM::VSTMDIA: {
     break;
   }
   case ARM::MVE_VQDMULLs32bh:
   case ARM::MVE_VQDMULLs32th:
   case ARM::MVE_VCMULf32:
   case ARM::MVE_VMULLs32bh:
   case ARM::MVE_VMULLs32th:
   case ARM::MVE_VMULLu32bh:
-  case ARM::MVE_VMULLu32th:
-  case ARM::MVE_VQDMLADHs32:
-  case ARM::MVE_VQDMLADHXs32:
-  case ARM::MVE_VQRDMLADHs32:
-  case ARM::MVE_VQRDMLADHXs32:
-  case ARM::MVE_VQDMLSDHs32:
-  case ARM::MVE_VQDMLSDHXs32:
-  case ARM::MVE_VQRDMLSDHs32:
-  case ARM::MVE_VQRDMLSDHXs32: {
+  case ARM::MVE_VMULLu32th: {
     if (Operands[3]->getReg() == Operands[4]->getReg()) {
       return Error (Operands[3]->getStartLoc(),
                     "Qd register and Qn register can't be identical");
     }
     if (Operands[3]->getReg() == Operands[5]->getReg()) {
       return Error (Operands[3]->getStartLoc(),
                     "Qd register and Qm register can't be identical");
     }

llvm/trunk/test/MC/ARM/mve-qdest-qsrc.s

 # CHECK: vqrdmladhx.s16 q0, q0, q1  @ encoding: [0x10,0xee,0x03,0x1e]
 # CHECK-NOFP: vqrdmladhx.s16 q0, q0, q1  @ encoding: [0x10,0xee,0x03,0x1e]
 vqrdmladhx.s16 q0, q0, q1
 
 # CHECK: vqrdmladhx.s32 q1, q0, q4  @ encoding: [0x20,0xee,0x09,0x3e]
 # CHECK-NOFP: vqrdmladhx.s32 q1, q0, q4  @ encoding: [0x20,0xee,0x09,0x3e]
 vqrdmladhx.s32 q1, q0, q4
 
-# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+# CHECK: vqrdmladhx.s32 q1, q1, q0  @ encoding: [0x22,0xee,0x01,0x3e]
+# CHECK-NOFP: vqrdmladhx.s32 q1, q1, q0  @ encoding: [0x22,0xee,0x01,0x3e]
 vqrdmladhx.s32 q1, q1, q0
 
-# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+# CHECK: vqrdmladhx.s32 q1, q0, q1  @ encoding: [0x20,0xee,0x03,0x3e]
+# CHECK-NOFP: vqrdmladhx.s32 q1, q0, q1  @ encoding: [0x20,0xee,0x03,0x3e]
 vqrdmladhx.s32 q1, q0, q1
 
 # CHECK: vqrdmladh.s8 q0, q6, q2  @ encoding: [0x0c,0xee,0x05,0x0e]
 # CHECK-NOFP: vqrdmladh.s8 q0, q6, q2  @ encoding: [0x0c,0xee,0x05,0x0e]
 vqrdmladh.s8 q0, q6, q2
 
 # CHECK: vqrdmladh.s16 q1, q5, q4  @ encoding: [0x1a,0xee,0x09,0x2e]
 # CHECK-NOFP: vqrdmladh.s16 q1, q5, q4  @ encoding: [0x1a,0xee,0x09,0x2e]

 # CHECK: vqrdmlsdh.s16 q0, q7, q4  @ encoding: [0x1e,0xfe,0x09,0x0e]
 # CHECK-NOFP: vqrdmlsdh.s16 q0, q7, q4  @ encoding: [0x1e,0xfe,0x09,0x0e]
 vqrdmlsdh.s16 q0, q7, q4
 
 # CHECK: vqrdmlsdh.s32 q0, q6, q7  @ encoding: [0x2c,0xfe,0x0f,0x0e]
 # CHECK-NOFP: vqrdmlsdh.s32 q0, q6, q7  @ encoding: [0x2c,0xfe,0x0f,0x0e]
 vqrdmlsdh.s32 q0, q6, q7
 
-# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+# CHECK: vqrdmlsdh.s32 q0, q0, q7  @ encoding: [0x20,0xfe,0x0f,0x0e]
+# CHECK-NOFP: vqrdmlsdh.s32 q0, q0, q7  @ encoding: [0x20,0xfe,0x0f,0x0e]
 vqrdmlsdh.s32 q0, q0, q7
 
-# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+# CHECK: vqrdmlsdh.s32 q0, q6, q0  @ encoding: [0x2c,0xfe,0x01,0x0e]
+# CHECK-NOFP: vqrdmlsdh.s32 q0, q6, q0  @ encoding: [0x2c,0xfe,0x01,0x0e]
 vqrdmlsdh.s32 q0, q6, q0
 
 # CHECK: vcmul.f16 q0, q1, q2, #90 @ encoding: [0x32,0xee,0x05,0x0e]
 # CHECK-NOFP-NOT: vcmul.f16 q0, q1, q2, #90 @ encoding: [0x32,0xee,0x05,0x0e]
 vcmul.f16 q0, q1, q2, #90
 
 # CHECK: vcmul.f16 q6, q2, q5, #0  @ encoding: [0x34,0xee,0x0a,0xce]
 # CHECK-NOFP-NOT: vcmul.f16 q6, q2, q5, #0  @ encoding: [0x34,0xee,0x0a,0xce]