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[ARM] Relax constraints on operands of VQxDMLxDH instructions
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Authored by miyuki on Jul 5 2019, 7:43 AM.

Details

Summary

According to a recently updated Armv8-M spec
(https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf) the
32-bit width versions of the following instructions:

  • VQDMLADH
  • VQDMLADHX
  • VQRDMLADH
  • VQRDMLADHX
  • VQDMLSDH
  • VQDMLSDHX
  • VQRDMLSDH
  • VQRDMLSDHX

are no longer unpredictable when their output register is the same as
one of the input registers.

This patch updates the assembler parser and the corresponding tests
and also removes @earlyclobber from the instruction constraints.

Diff Detail

Repository
rL LLVM

Event Timeline

miyuki created this revision.Jul 5 2019, 7:43 AM
simon_tatham accepted this revision.Jul 8 2019, 1:02 AM
This revision is now accepted and ready to land.Jul 8 2019, 1:02 AM
This revision was automatically updated to reflect the committed changes.