[ARM] Favour PL/MI over GE/LT when possible

[dmgreen]

Summary

The arm condition codes for GE is N==V (and for LT is N!=V). If the source of flags cannot set V (overflow), such as a cmp against #0, then we can use the simpler PL and MI conditions that only check N. As these PL/MI conditions are simpler than GE/LT, other passes like the peephole optimiser can have a better time optimising away the redundant CMPs.

The exception is the VSEL instruction, which cannot take these codes, so there the transform favours GE. I have added some extra tests to codegen/arm/vsel.ll to check against 0 (which are not shown here because they do not change). Some of the other tests here have been updated, for which I am showing the difference.

[efriedma]

I wrote a very similar patch at one point, but I didn't submit it because I couldn't demonstrate any significant benefit. Then again, I only tested it with Thumb1; maybe it's more useful for Thumb2?

llvm/lib/Target/ARM/ARMISelLowering.cpp

4086

isNullConstant

4730

Do you not need to check for ARMCC::MI here? Or do we avoid that somehow?

[dmgreen]

Now uses isNullConstant

[dmgreen]

Thanks for taking a look. The codesize changes here are minor, but present and consistently down. It was actually performance that I was looking for though, with this coming up on a couple of hot loops I was seeing. They do something like if ((a-b) < 0) ... a few times which previously was leaving the extra cmp instructions in. The changes in long shift also look like they may be useful.

llvm/lib/Target/ARM/ARMISelLowering.cpp

4730

The vsel can only handle GE, GT, VS and EQ apparently. The code above tries to invert the conditions to get one of these legal codes. So I don't believe that will usually be generated, and if it is then choosing MI over LT won't make much of a difference.

Without this change, we only end up generating a "vmovpl.f32 s0, s1" instead of a "vselge.f32 s0, s1, s0" in the tests I've added, so it didn't seem much worse in either case. The vsel is presumably better in general though.

[efriedma]

LGTM

llvm/lib/Target/ARM/ARMISelLowering.cpp

if (!isLegalICmpImmediate((int32_t)C)) {
              (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
     // In ARM and Thumb-2, the compare instructions can shift their second
     // operand.
     CC = ISD::getSetCCSwappedOperands(CC);
     std::swap(LHS, RHS);
   }
 
   ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
+
+  // If the RHS is a constant zero then the V (overflow) flag will never be
+  // set. This can allow us to simplify GE to PL or LT to MI, which can be
+  // simpler for other passes (like the peephole optimiser) to deal with.
+  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
+    if (RHSC->getZExtValue() == 0) {
+      switch (CondCode) {
+        default: break;
+        case ARMCC::GE:
+          CondCode = ARMCC::PL;
+          break;
+        case ARMCC::LT:
+          CondCode = ARMCC::MI;
+          break;
+      }
+    }
+  }
+
   ARMISD::NodeType CompareType;
   switch (CondCode) {
   default:
     CompareType = ARMISD::CMP;
     break;
   case ARMCC::EQ:
   case ARMCC::NE:
     // Uses only Z Flag
if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
         CC = ISD::getSetCCInverse(CC, true);
         std::swap(TrueVal, FalseVal);
       }
     }
 
     SDValue ARMcc;
     SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
     SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
+    // Choose GE over PL, which vsel does now support
+    if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
+      ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
     return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
   }
 
   ARMCC::CondCodes CondCode, CondCode2;
   bool InvalidOnQNaN;
   FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
 
   // Normalize the fp compare. If RHS is zero we prefer to keep it there so we

llvm/test/CodeGen/ARM/code-placement.ll

 entry:
 ; CHECK-LABEL: t2:
   %0 = icmp eq i32 %passes, 0                     ; <i1> [#uses=1]
   br i1 %0, label %bb5, label %bb.nph15
 
 bb1:                                              ; preds = %bb2.preheader, %bb1
 ; CHECK: LBB1_[[BB3:.]]: @ %bb3
 ; CHECK: LBB1_[[PREHDR:.]]: @ %bb2.preheader
-; CHECK: blt LBB1_[[BB3]]
+; CHECK: bmi LBB1_[[BB3]]
   %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %bb2.preheader ] ; <i32> [#uses=2]
   %sum.08 = phi i32 [ %2, %bb1 ], [ %sum.110, %bb2.preheader ] ; <i32> [#uses=1]
   %tmp17 = sub i32 %i.07, %indvar                 ; <i32> [#uses=1]
   %scevgep = getelementptr i32, i32* %src, i32 %tmp17  ; <i32*> [#uses=1]
   %1 = load i32, i32* %scevgep, align 4                ; <i32> [#uses=1]
   %2 = add nsw i32 %1, %sum.08                    ; <i32> [#uses=2]
   %indvar.next = add i32 %indvar, 1               ; <i32> [#uses=2]
   %exitcond = icmp eq i32 %indvar.next, %size     ; <i1> [#uses=1]

llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

 
 ; i64 scalar
 
 define i1 @scalar_i64_signbit_eq(i64 %x, i64 %y) nounwind {
 ; ARM6-LABEL: scalar_i64_signbit_eq:
 ; ARM6:       @ %bb.0:
 ; ARM6-NEXT:    push {r11, lr}
 ; ARM6-NEXT:    mov r12, #-2147483648
-; ARM6-NEXT:    sub lr, r2, #32
+; ARM6-NEXT:    subs lr, r2, #32
 ; ARM6-NEXT:    lsr r3, r12, r2
 ; ARM6-NEXT:    rsb r2, r2, #32
-; ARM6-NEXT:    cmp lr, #0
-; ARM6-NEXT:    lsl r2, r12, r2
-; ARM6-NEXT:    movge r3, #0
-; ARM6-NEXT:    lsrge r2, r12, lr
+; ARM6-NEXT:    movpl r3, #0
 ; ARM6-NEXT:    and r1, r3, r1
+; ARM6-NEXT:    lsl r2, r12, r2
+; ARM6-NEXT:    lsrpl r2, r12, lr
 ; ARM6-NEXT:    and r0, r2, r0
 ; ARM6-NEXT:    orr r0, r0, r1
 ; ARM6-NEXT:    clz r0, r0
 ; ARM6-NEXT:    lsr r0, r0, #5
 ; ARM6-NEXT:    pop {r11, pc}
 ;
 ; ARM78-LABEL: scalar_i64_signbit_eq:
 ; ARM78:       @ %bb.0:
 ; ARM78-NEXT:    push {r11, lr}
 ; ARM78-NEXT:    mov r12, #-2147483648
-; ARM78-NEXT:    sub lr, r2, #32
+; ARM78-NEXT:    subs lr, r2, #32
 ; ARM78-NEXT:    lsr r3, r12, r2
 ; ARM78-NEXT:    rsb r2, r2, #32
-; ARM78-NEXT:    cmp lr, #0
-; ARM78-NEXT:    lsl r2, r12, r2
-; ARM78-NEXT:    movwge r3, #0
-; ARM78-NEXT:    lsrge r2, r12, lr
+; ARM78-NEXT:    movwpl r3, #0
 ; ARM78-NEXT:    and r1, r3, r1
+; ARM78-NEXT:    lsl r2, r12, r2
+; ARM78-NEXT:    lsrpl r2, r12, lr
 ; ARM78-NEXT:    and r0, r2, r0
 ; ARM78-NEXT:    orr r0, r0, r1
 ; ARM78-NEXT:    clz r0, r0
 ; ARM78-NEXT:    lsr r0, r0, #5
 ; ARM78-NEXT:    pop {r11, pc}
 ;
 ; THUMB6-LABEL: scalar_i64_signbit_eq:
 ; THUMB6:       @ %bb.0:

 ; THUMB6-NEXT:    adcs r0, r1
 ; THUMB6-NEXT:    pop {r4, r5, r7, pc}
 ;
 ; THUMB7-LABEL: scalar_i64_signbit_eq:
 ; THUMB7:       @ %bb.0:
 ; THUMB7-NEXT:    push {r7, lr}
 ; THUMB7-NEXT:    rsb.w r3, r2, #32
 ; THUMB7-NEXT:    mov.w r12, #-2147483648
-; THUMB7-NEXT:    sub.w lr, r2, #32
+; THUMB7-NEXT:    subs.w lr, r2, #32
 ; THUMB7-NEXT:    lsr.w r2, r12, r2
 ; THUMB7-NEXT:    lsl.w r3, r12, r3
-; THUMB7-NEXT:    cmp.w lr, #0
-; THUMB7-NEXT:    it ge
-; THUMB7-NEXT:    lsrge.w r3, r12, lr
-; THUMB7-NEXT:    it ge
-; THUMB7-NEXT:    movge r2, #0
+; THUMB7-NEXT:    it pl
+; THUMB7-NEXT:    lsrpl.w r3, r12, lr
+; THUMB7-NEXT:    it pl
+; THUMB7-NEXT:    movpl r2, #0
 ; THUMB7-NEXT:    ands r0, r3
 ; THUMB7-NEXT:    ands r1, r2
 ; THUMB7-NEXT:    orrs r0, r1
 ; THUMB7-NEXT:    clz r0, r0
 ; THUMB7-NEXT:    lsrs r0, r0, #5
 ; THUMB7-NEXT:    pop {r7, pc}
 ;
 ; THUMB8-LABEL: scalar_i64_signbit_eq:
 ; THUMB8:       @ %bb.0:
-; THUMB8-NEXT:    .save {r4, lr}
-; THUMB8-NEXT:    push {r4, lr}
-; THUMB8-NEXT:    rsb.w r4, r2, #32
-; THUMB8-NEXT:    sub.w r3, r2, #32
+; THUMB8-NEXT:    .save {r7, lr}
+; THUMB8-NEXT:    push {r7, lr}
+; THUMB8-NEXT:    subs.w r3, r2, #32
 ; THUMB8-NEXT:    mov.w r12, #-2147483648
-; THUMB8-NEXT:    cmp r3, #0
-; THUMB8-NEXT:    lsl.w r4, r12, r4
-; THUMB8-NEXT:    lsr.w r2, r12, r2
 ; THUMB8-NEXT:    lsr.w lr, r12, r3
-; THUMB8-NEXT:    it ge
-; THUMB8-NEXT:    movge r4, lr
-; THUMB8-NEXT:    it ge
-; THUMB8-NEXT:    movge r2, #0
-; THUMB8-NEXT:    ands r0, r4
+; THUMB8-NEXT:    rsb.w r3, r2, #32
+; THUMB8-NEXT:    lsr.w r2, r12, r2
+; THUMB8-NEXT:    lsl.w r3, r12, r3
+; THUMB8-NEXT:    it pl
+; THUMB8-NEXT:    movpl r3, lr
+; THUMB8-NEXT:    it pl
+; THUMB8-NEXT:    movpl r2, #0
+; THUMB8-NEXT:    ands r0, r3
 ; THUMB8-NEXT:    ands r1, r2
 ; THUMB8-NEXT:    orrs r0, r1
 ; THUMB8-NEXT:    clz r0, r0
 ; THUMB8-NEXT:    lsrs r0, r0, #5
-; THUMB8-NEXT:    pop {r4, pc}
+; THUMB8-NEXT:    pop {r7, pc}
   %t0 = lshr i64 9223372036854775808, %y
   %t1 = and i64 %t0, %x
   %res = icmp eq i64 %t1, 0
   ret i1 %res
 }
 
 define i1 @scalar_i64_lowestbit_eq(i64 %x, i64 %y) nounwind {
 ; ARM6-LABEL: scalar_i64_lowestbit_eq:
 ; ARM6:       @ %bb.0:
 ; ARM6-NEXT:    mov r1, #1
 ; ARM6-NEXT:    lsr r1, r1, r2
-; ARM6-NEXT:    sub r2, r2, #32
-; ARM6-NEXT:    cmp r2, #0
-; ARM6-NEXT:    movge r1, #0
+; ARM6-NEXT:    subs r2, r2, #32
+; ARM6-NEXT:    movpl r1, #0
 ; ARM6-NEXT:    and r0, r1, r0
 ; ARM6-NEXT:    clz r0, r0
 ; ARM6-NEXT:    lsr r0, r0, #5
 ; ARM6-NEXT:    bx lr
 ;
 ; ARM78-LABEL: scalar_i64_lowestbit_eq:
 ; ARM78:       @ %bb.0:
 ; ARM78-NEXT:    mov r1, #1
 ; ARM78-NEXT:    lsr r1, r1, r2
-; ARM78-NEXT:    sub r2, r2, #32
-; ARM78-NEXT:    cmp r2, #0
-; ARM78-NEXT:    movwge r1, #0
+; ARM78-NEXT:    subs r2, r2, #32
+; ARM78-NEXT:    movwpl r1, #0
 ; ARM78-NEXT:    and r0, r1, r0
 ; ARM78-NEXT:    clz r0, r0
 ; ARM78-NEXT:    lsr r0, r0, #5
 ; ARM78-NEXT:    bx lr
 ;
 ; THUMB6-LABEL: scalar_i64_lowestbit_eq:
 ; THUMB6:       @ %bb.0:
 ; THUMB6-NEXT:    push {r4, r5, r7, lr}

 ; THUMB6-NEXT:    adcs r0, r1
 ; THUMB6-NEXT:    pop {r4, r5, r7, pc}
 ;
 ; THUMB78-LABEL: scalar_i64_lowestbit_eq:
 ; THUMB78:       @ %bb.0:
 ; THUMB78-NEXT:    movs r1, #1
 ; THUMB78-NEXT:    lsrs r1, r2
 ; THUMB78-NEXT:    subs r2, #32
-; THUMB78-NEXT:    cmp r2, #0
-; THUMB78-NEXT:    it ge
-; THUMB78-NEXT:    movge r1, #0
+; THUMB78-NEXT:    it pl
+; THUMB78-NEXT:    movpl r1, #0
 ; THUMB78-NEXT:    ands r0, r1
 ; THUMB78-NEXT:    clz r0, r0
 ; THUMB78-NEXT:    lsrs r0, r0, #5
 ; THUMB78-NEXT:    bx lr
   %t0 = lshr i64 1, %y
   %t1 = and i64 %t0, %x
   %res = icmp eq i64 %t1, 0
   ret i1 %res
 }
 
 define i1 @scalar_i64_bitsinmiddle_eq(i64 %x, i64 %y) nounwind {
 ; ARM6-LABEL: scalar_i64_bitsinmiddle_eq:
 ; ARM6:       @ %bb.0:
 ; ARM6-NEXT:    push {r11, lr}
 ; ARM6-NEXT:    mov r12, #255
-; ARM6-NEXT:    sub lr, r2, #32
+; ARM6-NEXT:    subs lr, r2, #32
 ; ARM6-NEXT:    orr r12, r12, #65280
-; ARM6-NEXT:    cmp lr, #0
 ; ARM6-NEXT:    lsr r3, r12, r2
-; ARM6-NEXT:    movge r3, #0
+; ARM6-NEXT:    movpl r3, #0
 ; ARM6-NEXT:    and r1, r3, r1
 ; ARM6-NEXT:    mov r3, #16711680
 ; ARM6-NEXT:    cmp lr, #0
 ; ARM6-NEXT:    orr r3, r3, #-16777216
 ; ARM6-NEXT:    lsr r3, r3, r2
 ; ARM6-NEXT:    rsb r2, r2, #32
 ; ARM6-NEXT:    orr r2, r3, r12, lsl r2
-; ARM6-NEXT:    lsrge r2, r12, lr
+; ARM6-NEXT:    lsrpl r2, r12, lr
 ; ARM6-NEXT:    and r0, r2, r0
 ; ARM6-NEXT:    orr r0, r0, r1
 ; ARM6-NEXT:    clz r0, r0
 ; ARM6-NEXT:    lsr r0, r0, #5
 ; ARM6-NEXT:    pop {r11, pc}
 ;
 ; ARM78-LABEL: scalar_i64_bitsinmiddle_eq:
 ; ARM78:       @ %bb.0:
 ; ARM78-NEXT:    push {r11, lr}
 ; ARM78-NEXT:    movw r12, #65535
-; ARM78-NEXT:    sub lr, r2, #32
+; ARM78-NEXT:    subs lr, r2, #32
 ; ARM78-NEXT:    lsr r3, r12, r2
-; ARM78-NEXT:    cmp lr, #0
-; ARM78-NEXT:    movwge r3, #0
+; ARM78-NEXT:    movwpl r3, #0
 ; ARM78-NEXT:    and r1, r3, r1
 ; ARM78-NEXT:    movw r3, #0
 ; ARM78-NEXT:    cmp lr, #0
 ; ARM78-NEXT:    movt r3, #65535
 ; ARM78-NEXT:    lsr r3, r3, r2
 ; ARM78-NEXT:    rsb r2, r2, #32
 ; ARM78-NEXT:    orr r2, r3, r12, lsl r2
-; ARM78-NEXT:    lsrge r2, r12, lr
+; ARM78-NEXT:    lsrpl r2, r12, lr
 ; ARM78-NEXT:    and r0, r2, r0
 ; ARM78-NEXT:    orr r0, r0, r1
 ; ARM78-NEXT:    clz r0, r0
 ; ARM78-NEXT:    lsr r0, r0, #5
 ; ARM78-NEXT:    pop {r11, pc}
 ;
 ; THUMB6-LABEL: scalar_i64_bitsinmiddle_eq:
 ; THUMB6:       @ %bb.0:

 ; THUMB7:       @ %bb.0:
 ; THUMB7-NEXT:    push {r7, lr}
 ; THUMB7-NEXT:    movs r3, #0
 ; THUMB7-NEXT:    movw lr, #65535
 ; THUMB7-NEXT:    movt r3, #65535
 ; THUMB7-NEXT:    lsr.w r12, r3, r2
 ; THUMB7-NEXT:    rsb.w r3, r2, #32
 ; THUMB7-NEXT:    lsl.w r3, lr, r3
-; THUMB7-NEXT:    orr.w r3, r3, r12
-; THUMB7-NEXT:    sub.w r12, r2, #32
+; THUMB7-NEXT:    orr.w r12, r12, r3
+; THUMB7-NEXT:    subs.w r3, r2, #32
 ; THUMB7-NEXT:    lsr.w r2, lr, r2
-; THUMB7-NEXT:    cmp.w r12, #0
-; THUMB7-NEXT:    it ge
-; THUMB7-NEXT:    lsrge.w r3, lr, r12
-; THUMB7-NEXT:    it ge
-; THUMB7-NEXT:    movge r2, #0
-; THUMB7-NEXT:    ands r0, r3
+; THUMB7-NEXT:    it pl
+; THUMB7-NEXT:    lsrpl.w r12, lr, r3
+; THUMB7-NEXT:    it pl
+; THUMB7-NEXT:    movpl r2, #0
+; THUMB7-NEXT:    and.w r0, r0, r12
 ; THUMB7-NEXT:    ands r1, r2
 ; THUMB7-NEXT:    orrs r0, r1
 ; THUMB7-NEXT:    clz r0, r0
 ; THUMB7-NEXT:    lsrs r0, r0, #5
 ; THUMB7-NEXT:    pop {r7, pc}
 ;
 ; THUMB8-LABEL: scalar_i64_bitsinmiddle_eq:
 ; THUMB8:       @ %bb.0:
-; THUMB8-NEXT:    .save {r4, lr}
-; THUMB8-NEXT:    push {r4, lr}
+; THUMB8-NEXT:    .save {r7, lr}
+; THUMB8-NEXT:    push {r7, lr}
 ; THUMB8-NEXT:    movs r3, #0
 ; THUMB8-NEXT:    movw lr, #65535
 ; THUMB8-NEXT:    movt r3, #65535
 ; THUMB8-NEXT:    lsr.w r12, r3, r2
 ; THUMB8-NEXT:    rsb.w r3, r2, #32
 ; THUMB8-NEXT:    lsl.w r3, lr, r3
 ; THUMB8-NEXT:    orr.w r12, r12, r3
-; THUMB8-NEXT:    sub.w r3, r2, #32
+; THUMB8-NEXT:    subs.w r3, r2, #32
 ; THUMB8-NEXT:    lsr.w r2, lr, r2
-; THUMB8-NEXT:    cmp r3, #0
-; THUMB8-NEXT:    lsr.w r4, lr, r3
-; THUMB8-NEXT:    it lt
-; THUMB8-NEXT:    movlt r4, r12
-; THUMB8-NEXT:    it ge
-; THUMB8-NEXT:    movge r2, #0
-; THUMB8-NEXT:    ands r0, r4
+; THUMB8-NEXT:    lsr.w r3, lr, r3
+; THUMB8-NEXT:    it mi
+; THUMB8-NEXT:    movmi r3, r12
+; THUMB8-NEXT:    it pl
+; THUMB8-NEXT:    movpl r2, #0
+; THUMB8-NEXT:    ands r0, r3
 ; THUMB8-NEXT:    ands r1, r2
 ; THUMB8-NEXT:    orrs r0, r1
 ; THUMB8-NEXT:    clz r0, r0
 ; THUMB8-NEXT:    lsrs r0, r0, #5
-; THUMB8-NEXT:    pop {r4, pc}
+; THUMB8-NEXT:    pop {r7, pc}
   %t0 = lshr i64 281474976645120, %y
   %t1 = and i64 %t0, %x
   %res = icmp eq i64 %t1, 0
   ret i1 %res
 }
 
 ;------------------------------------------------------------------------------;
 ; A few trivial vector tests

 ; ARM6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
 ; ARM6:       @ %bb.0:
 ; ARM6-NEXT:    uxtb r1, r1
 ; ARM6-NEXT:    mov r2, #24
 ; ARM6-NEXT:    and r0, r0, r2, lsr r1
 ; ARM6-NEXT:    sxtb r1, r0
 ; ARM6-NEXT:    mov r0, #0
 ; ARM6-NEXT:    cmp r1, #0
-; ARM6-NEXT:    movlt r0, #1
+; ARM6-NEXT:    movmi r0, #1
 ; ARM6-NEXT:    bx lr
 ;
 ; ARM78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
 ; ARM78:       @ %bb.0:
 ; ARM78-NEXT:    uxtb r1, r1
 ; ARM78-NEXT:    mov r2, #24
 ; ARM78-NEXT:    and r0, r0, r2, lsr r1
 ; ARM78-NEXT:    sxtb r1, r0
 ; ARM78-NEXT:    mov r0, #0
 ; ARM78-NEXT:    cmp r1, #0
-; ARM78-NEXT:    movwlt r0, #1
+; ARM78-NEXT:    movwmi r0, #1
 ; ARM78-NEXT:    bx lr
 ;
 ; THUMB6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
 ; THUMB6:       @ %bb.0:
 ; THUMB6-NEXT:    uxtb r1, r1
 ; THUMB6-NEXT:    movs r2, #24
 ; THUMB6-NEXT:    lsrs r2, r1
 ; THUMB6-NEXT:    ands r2, r0
 ; THUMB6-NEXT:    sxtb r0, r2
 ; THUMB6-NEXT:    cmp r0, #0
-; THUMB6-NEXT:    blt .LBB20_2
+; THUMB6-NEXT:    bmi .LBB20_2
 ; THUMB6-NEXT:  @ %bb.1:
 ; THUMB6-NEXT:    movs r0, #0
 ; THUMB6-NEXT:    bx lr
 ; THUMB6-NEXT:  .LBB20_2:
 ; THUMB6-NEXT:    movs r0, #1
 ; THUMB6-NEXT:    bx lr
 ;
 ; THUMB78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
 ; THUMB78:       @ %bb.0:
 ; THUMB78-NEXT:    uxtb r1, r1
 ; THUMB78-NEXT:    movs r2, #24
 ; THUMB78-NEXT:    lsr.w r1, r2, r1
 ; THUMB78-NEXT:    ands r0, r1
 ; THUMB78-NEXT:    sxtb r1, r0
 ; THUMB78-NEXT:    movs r0, #0
 ; THUMB78-NEXT:    cmp r1, #0
-; THUMB78-NEXT:    it lt
-; THUMB78-NEXT:    movlt r0, #1
+; THUMB78-NEXT:    it mi
+; THUMB78-NEXT:    movmi r0, #1
 ; THUMB78-NEXT:    bx lr
   %t0 = lshr i8 24, %y
   %t1 = and i8 %t0, %x
   %res = icmp slt i8 %t1, 0
   ret i1 %res
 }
 
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {

llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

 
 ; i64 scalar
 
 define i1 @scalar_i64_signbit_eq(i64 %x, i64 %y) nounwind {
 ; ARM6-LABEL: scalar_i64_signbit_eq:
 ; ARM6:       @ %bb.0:
 ; ARM6-NEXT:    mov r0, #-2147483648
 ; ARM6-NEXT:    lsl r0, r0, r2
-; ARM6-NEXT:    sub r2, r2, #32
-; ARM6-NEXT:    cmp r2, #0
-; ARM6-NEXT:    movge r0, #0
+; ARM6-NEXT:    subs r2, r2, #32
+; ARM6-NEXT:    movpl r0, #0
 ; ARM6-NEXT:    and r0, r0, r1
 ; ARM6-NEXT:    clz r0, r0
 ; ARM6-NEXT:    lsr r0, r0, #5
 ; ARM6-NEXT:    bx lr
 ;
 ; ARM78-LABEL: scalar_i64_signbit_eq:
 ; ARM78:       @ %bb.0:
 ; ARM78-NEXT:    mov r0, #-2147483648
 ; ARM78-NEXT:    lsl r0, r0, r2
-; ARM78-NEXT:    sub r2, r2, #32
-; ARM78-NEXT:    cmp r2, #0
-; ARM78-NEXT:    movwge r0, #0
+; ARM78-NEXT:    subs r2, r2, #32
+; ARM78-NEXT:    movwpl r0, #0
 ; ARM78-NEXT:    and r0, r0, r1
 ; ARM78-NEXT:    clz r0, r0
 ; ARM78-NEXT:    lsr r0, r0, #5
 ; ARM78-NEXT:    bx lr
 ;
 ; THUMB6-LABEL: scalar_i64_signbit_eq:
 ; THUMB6:       @ %bb.0:
 ; THUMB6-NEXT:    push {r4, r5, r7, lr}

 ; THUMB6-NEXT:    adcs r0, r1
 ; THUMB6-NEXT:    pop {r4, r5, r7, pc}
 ;
 ; THUMB78-LABEL: scalar_i64_signbit_eq:
 ; THUMB78:       @ %bb.0:
 ; THUMB78-NEXT:    mov.w r0, #-2147483648
 ; THUMB78-NEXT:    lsls r0, r2
 ; THUMB78-NEXT:    subs r2, #32
-; THUMB78-NEXT:    cmp r2, #0
-; THUMB78-NEXT:    it ge
-; THUMB78-NEXT:    movge r0, #0
+; THUMB78-NEXT:    it pl
+; THUMB78-NEXT:    movpl r0, #0
 ; THUMB78-NEXT:    ands r0, r1
 ; THUMB78-NEXT:    clz r0, r0
 ; THUMB78-NEXT:    lsrs r0, r0, #5
 ; THUMB78-NEXT:    bx lr
   %t0 = shl i64 9223372036854775808, %y
   %t1 = and i64 %t0, %x
   %res = icmp eq i64 %t1, 0
   ret i1 %res
 }
 
 define i1 @scalar_i64_lowestbit_eq(i64 %x, i64 %y) nounwind {
 ; ARM6-LABEL: scalar_i64_lowestbit_eq:
 ; ARM6:       @ %bb.0:
 ; ARM6-NEXT:    push {r11, lr}
 ; ARM6-NEXT:    mov r12, #1
-; ARM6-NEXT:    sub lr, r2, #32
+; ARM6-NEXT:    subs lr, r2, #32
 ; ARM6-NEXT:    lsl r3, r12, r2
 ; ARM6-NEXT:    rsb r2, r2, #32
-; ARM6-NEXT:    cmp lr, #0
-; ARM6-NEXT:    lsr r2, r12, r2
-; ARM6-NEXT:    movge r3, #0
-; ARM6-NEXT:    lslge r2, r12, lr
+; ARM6-NEXT:    movpl r3, #0
 ; ARM6-NEXT:    and r0, r3, r0
+; ARM6-NEXT:    lsr r2, r12, r2
+; ARM6-NEXT:    lslpl r2, r12, lr
 ; ARM6-NEXT:    and r1, r2, r1
 ; ARM6-NEXT:    orr r0, r0, r1
 ; ARM6-NEXT:    clz r0, r0
 ; ARM6-NEXT:    lsr r0, r0, #5
 ; ARM6-NEXT:    pop {r11, pc}
 ;
 ; ARM78-LABEL: scalar_i64_lowestbit_eq:
 ; ARM78:       @ %bb.0:
 ; ARM78-NEXT:    push {r11, lr}
 ; ARM78-NEXT:    mov r12, #1
-; ARM78-NEXT:    sub lr, r2, #32
+; ARM78-NEXT:    subs lr, r2, #32
 ; ARM78-NEXT:    lsl r3, r12, r2
 ; ARM78-NEXT:    rsb r2, r2, #32
-; ARM78-NEXT:    cmp lr, #0
-; ARM78-NEXT:    lsr r2, r12, r2
-; ARM78-NEXT:    movwge r3, #0
-; ARM78-NEXT:    lslge r2, r12, lr
+; ARM78-NEXT:    movwpl r3, #0
 ; ARM78-NEXT:    and r0, r3, r0
+; ARM78-NEXT:    lsr r2, r12, r2
+; ARM78-NEXT:    lslpl r2, r12, lr
 ; ARM78-NEXT:    and r1, r2, r1
 ; ARM78-NEXT:    orr r0, r0, r1
 ; ARM78-NEXT:    clz r0, r0
 ; ARM78-NEXT:    lsr r0, r0, #5
 ; ARM78-NEXT:    pop {r11, pc}
 ;
 ; THUMB6-LABEL: scalar_i64_lowestbit_eq:
 ; THUMB6:       @ %bb.0:

 ; THUMB6-NEXT:    adcs r0, r1
 ; THUMB6-NEXT:    pop {r4, r5, r7, pc}
 ;
 ; THUMB7-LABEL: scalar_i64_lowestbit_eq:
 ; THUMB7:       @ %bb.0:
 ; THUMB7-NEXT:    push {r7, lr}
 ; THUMB7-NEXT:    rsb.w r3, r2, #32
 ; THUMB7-NEXT:    mov.w r12, #1
-; THUMB7-NEXT:    sub.w lr, r2, #32
+; THUMB7-NEXT:    subs.w lr, r2, #32
 ; THUMB7-NEXT:    lsl.w r2, r12, r2
 ; THUMB7-NEXT:    lsr.w r3, r12, r3
-; THUMB7-NEXT:    cmp.w lr, #0
-; THUMB7-NEXT:    it ge
-; THUMB7-NEXT:    lslge.w r3, r12, lr
-; THUMB7-NEXT:    it ge
-; THUMB7-NEXT:    movge r2, #0
+; THUMB7-NEXT:    it pl
+; THUMB7-NEXT:    lslpl.w r3, r12, lr
+; THUMB7-NEXT:    it pl
+; THUMB7-NEXT:    movpl r2, #0
 ; THUMB7-NEXT:    ands r1, r3
 ; THUMB7-NEXT:    ands r0, r2
 ; THUMB7-NEXT:    orrs r0, r1
 ; THUMB7-NEXT:    clz r0, r0
 ; THUMB7-NEXT:    lsrs r0, r0, #5
 ; THUMB7-NEXT:    pop {r7, pc}
 ;
 ; THUMB8-LABEL: scalar_i64_lowestbit_eq:
 ; THUMB8:       @ %bb.0:
-; THUMB8-NEXT:    .save {r4, lr}
-; THUMB8-NEXT:    push {r4, lr}
-; THUMB8-NEXT:    rsb.w r4, r2, #32
-; THUMB8-NEXT:    sub.w r3, r2, #32
+; THUMB8-NEXT:    .save {r7, lr}
+; THUMB8-NEXT:    push {r7, lr}
+; THUMB8-NEXT:    subs.w r3, r2, #32
 ; THUMB8-NEXT:    mov.w r12, #1
-; THUMB8-NEXT:    cmp r3, #0
-; THUMB8-NEXT:    lsr.w r4, r12, r4
-; THUMB8-NEXT:    lsl.w r2, r12, r2
 ; THUMB8-NEXT:    lsl.w lr, r12, r3
-; THUMB8-NEXT:    it ge
-; THUMB8-NEXT:    movge r4, lr
-; THUMB8-NEXT:    it ge
-; THUMB8-NEXT:    movge r2, #0
-; THUMB8-NEXT:    ands r1, r4
+; THUMB8-NEXT:    rsb.w r3, r2, #32
+; THUMB8-NEXT:    lsl.w r2, r12, r2
+; THUMB8-NEXT:    lsr.w r3, r12, r3
+; THUMB8-NEXT:    it pl
+; THUMB8-NEXT:    movpl r3, lr
+; THUMB8-NEXT:    it pl
+; THUMB8-NEXT:    movpl r2, #0
+; THUMB8-NEXT:    ands r1, r3
 ; THUMB8-NEXT:    ands r0, r2
 ; THUMB8-NEXT:    orrs r0, r1
 ; THUMB8-NEXT:    clz r0, r0
 ; THUMB8-NEXT:    lsrs r0, r0, #5
-; THUMB8-NEXT:    pop {r4, pc}
+; THUMB8-NEXT:    pop {r7, pc}
   %t0 = shl i64 1, %y
   %t1 = and i64 %t0, %x
   %res = icmp eq i64 %t1, 0
   ret i1 %res
 }
 
 define i1 @scalar_i64_bitsinmiddle_eq(i64 %x, i64 %y) nounwind {
 ; ARM6-LABEL: scalar_i64_bitsinmiddle_eq:
 ; ARM6:       @ %bb.0:
 ; ARM6-NEXT:    push {r4, lr}
 ; ARM6-NEXT:    mov r12, #16711680
-; ARM6-NEXT:    sub lr, r2, #32
+; ARM6-NEXT:    subs lr, r2, #32
 ; ARM6-NEXT:    orr r12, r12, #-16777216
-; ARM6-NEXT:    cmp lr, #0
 ; ARM6-NEXT:    mov r4, #255
-; ARM6-NEXT:    lsl r3, r12, r2
 ; ARM6-NEXT:    orr r4, r4, #65280
-; ARM6-NEXT:    movge r3, #0
+; ARM6-NEXT:    lsl r3, r12, r2
+; ARM6-NEXT:    movpl r3, #0
 ; ARM6-NEXT:    and r0, r3, r0
 ; ARM6-NEXT:    rsb r3, r2, #32
 ; ARM6-NEXT:    cmp lr, #0
 ; ARM6-NEXT:    lsr r3, r12, r3
 ; ARM6-NEXT:    orr r2, r3, r4, lsl r2
-; ARM6-NEXT:    lslge r2, r12, lr
+; ARM6-NEXT:    lslpl r2, r12, lr
 ; ARM6-NEXT:    and r1, r2, r1
 ; ARM6-NEXT:    orr r0, r0, r1
 ; ARM6-NEXT:    clz r0, r0
 ; ARM6-NEXT:    lsr r0, r0, #5
 ; ARM6-NEXT:    pop {r4, pc}
 ;
 ; ARM78-LABEL: scalar_i64_bitsinmiddle_eq:
 ; ARM78:       @ %bb.0:
 ; ARM78-NEXT:    push {r4, lr}
 ; ARM78-NEXT:    movw r12, #0
-; ARM78-NEXT:    sub lr, r2, #32
+; ARM78-NEXT:    subs lr, r2, #32
 ; ARM78-NEXT:    movt r12, #65535
-; ARM78-NEXT:    cmp lr, #0
-; ARM78-NEXT:    lsl r3, r12, r2
 ; ARM78-NEXT:    movw r4, #65535
-; ARM78-NEXT:    movwge r3, #0
+; ARM78-NEXT:    lsl r3, r12, r2
+; ARM78-NEXT:    movwpl r3, #0
 ; ARM78-NEXT:    and r0, r3, r0
 ; ARM78-NEXT:    rsb r3, r2, #32
 ; ARM78-NEXT:    cmp lr, #0
 ; ARM78-NEXT:    lsr r3, r12, r3
 ; ARM78-NEXT:    orr r2, r3, r4, lsl r2
-; ARM78-NEXT:    lslge r2, r12, lr
+; ARM78-NEXT:    lslpl r2, r12, lr
 ; ARM78-NEXT:    and r1, r2, r1
 ; ARM78-NEXT:    orr r0, r0, r1
 ; ARM78-NEXT:    clz r0, r0
 ; ARM78-NEXT:    lsr r0, r0, #5
 ; ARM78-NEXT:    pop {r4, pc}
 ;
 ; THUMB6-LABEL: scalar_i64_bitsinmiddle_eq:
 ; THUMB6:       @ %bb.0:

 ; THUMB7:       @ %bb.0:
 ; THUMB7-NEXT:    push {r7, lr}
 ; THUMB7-NEXT:    movw r3, #65535
 ; THUMB7-NEXT:    movw lr, #0
 ; THUMB7-NEXT:    lsl.w r12, r3, r2
 ; THUMB7-NEXT:    rsb.w r3, r2, #32
 ; THUMB7-NEXT:    movt lr, #65535
 ; THUMB7-NEXT:    lsr.w r3, lr, r3
-; THUMB7-NEXT:    orr.w r3, r3, r12
-; THUMB7-NEXT:    sub.w r12, r2, #32
+; THUMB7-NEXT:    orr.w r12, r12, r3
+; THUMB7-NEXT:    subs.w r3, r2, #32
 ; THUMB7-NEXT:    lsl.w r2, lr, r2
-; THUMB7-NEXT:    cmp.w r12, #0
-; THUMB7-NEXT:    it ge
-; THUMB7-NEXT:    lslge.w r3, lr, r12
-; THUMB7-NEXT:    it ge
-; THUMB7-NEXT:    movge r2, #0
-; THUMB7-NEXT:    ands r1, r3
+; THUMB7-NEXT:    it pl
+; THUMB7-NEXT:    lslpl.w r12, lr, r3
+; THUMB7-NEXT:    it pl
+; THUMB7-NEXT:    movpl r2, #0
+; THUMB7-NEXT:    and.w r1, r1, r12
 ; THUMB7-NEXT:    ands r0, r2
 ; THUMB7-NEXT:    orrs r0, r1
 ; THUMB7-NEXT:    clz r0, r0
 ; THUMB7-NEXT:    lsrs r0, r0, #5
 ; THUMB7-NEXT:    pop {r7, pc}
 ;
 ; THUMB8-LABEL: scalar_i64_bitsinmiddle_eq:
 ; THUMB8:       @ %bb.0:
-; THUMB8-NEXT:    .save {r4, lr}
-; THUMB8-NEXT:    push {r4, lr}
+; THUMB8-NEXT:    .save {r7, lr}
+; THUMB8-NEXT:    push {r7, lr}
 ; THUMB8-NEXT:    movw r3, #65535
 ; THUMB8-NEXT:    movw lr, #0
 ; THUMB8-NEXT:    lsl.w r12, r3, r2
 ; THUMB8-NEXT:    rsb.w r3, r2, #32
 ; THUMB8-NEXT:    movt lr, #65535
 ; THUMB8-NEXT:    lsr.w r3, lr, r3
 ; THUMB8-NEXT:    orr.w r12, r12, r3
-; THUMB8-NEXT:    sub.w r3, r2, #32
+; THUMB8-NEXT:    subs.w r3, r2, #32
 ; THUMB8-NEXT:    lsl.w r2, lr, r2
-; THUMB8-NEXT:    cmp r3, #0
-; THUMB8-NEXT:    lsl.w r4, lr, r3
-; THUMB8-NEXT:    it lt
-; THUMB8-NEXT:    movlt r4, r12
-; THUMB8-NEXT:    it ge
-; THUMB8-NEXT:    movge r2, #0
-; THUMB8-NEXT:    ands r1, r4
+; THUMB8-NEXT:    lsl.w r3, lr, r3
+; THUMB8-NEXT:    it mi
+; THUMB8-NEXT:    movmi r3, r12
+; THUMB8-NEXT:    it pl
+; THUMB8-NEXT:    movpl r2, #0
+; THUMB8-NEXT:    ands r1, r3
 ; THUMB8-NEXT:    ands r0, r2
 ; THUMB8-NEXT:    orrs r0, r1
 ; THUMB8-NEXT:    clz r0, r0
 ; THUMB8-NEXT:    lsrs r0, r0, #5
-; THUMB8-NEXT:    pop {r4, pc}
+; THUMB8-NEXT:    pop {r7, pc}
   %t0 = shl i64 281474976645120, %y
   %t1 = and i64 %t0, %x
   %res = icmp eq i64 %t1, 0
   ret i1 %res
 }
 
 ;------------------------------------------------------------------------------;
 ; A few trivial vector tests

 ; ARM6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
 ; ARM6:       @ %bb.0:
 ; ARM6-NEXT:    uxtb r1, r1
 ; ARM6-NEXT:    mov r2, #24
 ; ARM6-NEXT:    and r0, r0, r2, lsl r1
 ; ARM6-NEXT:    sxtb r1, r0
 ; ARM6-NEXT:    mov r0, #0
 ; ARM6-NEXT:    cmp r1, #0
-; ARM6-NEXT:    movlt r0, #1
+; ARM6-NEXT:    movmi r0, #1
 ; ARM6-NEXT:    bx lr
 ;
 ; ARM78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
 ; ARM78:       @ %bb.0:
 ; ARM78-NEXT:    uxtb r1, r1
 ; ARM78-NEXT:    mov r2, #24
 ; ARM78-NEXT:    and r0, r0, r2, lsl r1
 ; ARM78-NEXT:    sxtb r1, r0
 ; ARM78-NEXT:    mov r0, #0
 ; ARM78-NEXT:    cmp r1, #0
-; ARM78-NEXT:    movwlt r0, #1
+; ARM78-NEXT:    movwmi r0, #1
 ; ARM78-NEXT:    bx lr
 ;
 ; THUMB6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
 ; THUMB6:       @ %bb.0:
 ; THUMB6-NEXT:    uxtb r1, r1
 ; THUMB6-NEXT:    movs r2, #24
 ; THUMB6-NEXT:    lsls r2, r1
 ; THUMB6-NEXT:    ands r2, r0
 ; THUMB6-NEXT:    sxtb r0, r2
 ; THUMB6-NEXT:    cmp r0, #0
-; THUMB6-NEXT:    blt .LBB20_2
+; THUMB6-NEXT:    bmi .LBB20_2
 ; THUMB6-NEXT:  @ %bb.1:
 ; THUMB6-NEXT:    movs r0, #0
 ; THUMB6-NEXT:    bx lr
 ; THUMB6-NEXT:  .LBB20_2:
 ; THUMB6-NEXT:    movs r0, #1
 ; THUMB6-NEXT:    bx lr
 ;
 ; THUMB78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
 ; THUMB78:       @ %bb.0:
 ; THUMB78-NEXT:    uxtb r1, r1
 ; THUMB78-NEXT:    movs r2, #24
 ; THUMB78-NEXT:    lsl.w r1, r2, r1
 ; THUMB78-NEXT:    ands r0, r1
 ; THUMB78-NEXT:    sxtb r1, r0
 ; THUMB78-NEXT:    movs r0, #0
 ; THUMB78-NEXT:    cmp r1, #0
-; THUMB78-NEXT:    it lt
-; THUMB78-NEXT:    movlt r0, #1
+; THUMB78-NEXT:    it mi
+; THUMB78-NEXT:    movmi r0, #1
 ; THUMB78-NEXT:    bx lr
   %t0 = shl i8 24, %y
   %t1 = and i8 %t0, %x
   %res = icmp slt i8 %t1, 0
   ret i1 %res
 }
 
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {

llvm/test/CodeGen/ARM/long_shift.ll

; CHECK-BE-NEXT:    mov pc, lr
   %tmp2 = lshr i64 %B, 1
   %tmp3 = sub i64 %tmp, %tmp2
   ret i64 %tmp3
 }
 
 define i32 @f1(i64 %x, i64 %y) {
 ; CHECK-LE-LABEL: f1:
 ; CHECK-LE:       @ %bb.0:
-; CHECK-LE-NEXT:    sub r1, r2, #32
 ; CHECK-LE-NEXT:    lsl r0, r0, r2
-; CHECK-LE-NEXT:    cmp r1, #0
-; CHECK-LE-NEXT:    movge r0, #0
+; CHECK-LE-NEXT:    subs r1, r2, #32
+; CHECK-LE-NEXT:    movpl r0, #0
 ; CHECK-LE-NEXT:    mov pc, lr
 ;
 ; CHECK-BE-LABEL: f1:
 ; CHECK-BE:       @ %bb.0:
 ; CHECK-BE-NEXT:    lsl r0, r1, r3
-; CHECK-BE-NEXT:    sub r1, r3, #32
-; CHECK-BE-NEXT:    cmp r1, #0
-; CHECK-BE-NEXT:    movge r0, #0
+; CHECK-BE-NEXT:    subs r1, r3, #32
+; CHECK-BE-NEXT:    movpl r0, #0
 ; CHECK-BE-NEXT:    mov pc, lr
 
   %a = shl i64 %x, %y
   %b = trunc i64 %a to i32
   ret i32 %b
 }
 
 define i32 @f2(i64 %x, i64 %y) {
 ; CHECK-LE-LABEL: f2:
 ; CHECK-LE:       @ %bb.0:
 ; CHECK-LE-NEXT:    rsb r3, r2, #32
 ; CHECK-LE-NEXT:    lsr r0, r0, r2
-; CHECK-LE-NEXT:    sub r2, r2, #32
+; CHECK-LE-NEXT:    subs r2, r2, #32
 ; CHECK-LE-NEXT:    orr r0, r0, r1, lsl r3
-; CHECK-LE-NEXT:    cmp r2, #0
-; CHECK-LE-NEXT:    asrge r0, r1, r2
+; CHECK-LE-NEXT:    asrpl r0, r1, r2
 ; CHECK-LE-NEXT:    mov pc, lr
 ;
 ; CHECK-BE-LABEL: f2:
 ; CHECK-BE:       @ %bb.0:
 ; CHECK-BE-NEXT:    rsb r2, r3, #32
 ; CHECK-BE-NEXT:    lsr r1, r1, r3
 ; CHECK-BE-NEXT:    orr r1, r1, r0, lsl r2
-; CHECK-BE-NEXT:    sub r2, r3, #32
-; CHECK-BE-NEXT:    cmp r2, #0
-; CHECK-BE-NEXT:    asrge r1, r0, r2
+; CHECK-BE-NEXT:    subs r2, r3, #32
+; CHECK-BE-NEXT:    asrpl r1, r0, r2
 ; CHECK-BE-NEXT:    mov r0, r1
 ; CHECK-BE-NEXT:    mov pc, lr
 
   %a = ashr i64 %x, %y
   %b = trunc i64 %a to i32
   ret i32 %b
 }
 
 define i32 @f3(i64 %x, i64 %y) {
 ; CHECK-LE-LABEL: f3:
 ; CHECK-LE:       @ %bb.0:
 ; CHECK-LE-NEXT:    rsb r3, r2, #32
 ; CHECK-LE-NEXT:    lsr r0, r0, r2
-; CHECK-LE-NEXT:    sub r2, r2, #32
+; CHECK-LE-NEXT:    subs r2, r2, #32
 ; CHECK-LE-NEXT:    orr r0, r0, r1, lsl r3
-; CHECK-LE-NEXT:    cmp r2, #0
-; CHECK-LE-NEXT:    lsrge r0, r1, r2
+; CHECK-LE-NEXT:    lsrpl r0, r1, r2
 ; CHECK-LE-NEXT:    mov pc, lr
 ;
 ; CHECK-BE-LABEL: f3:
 ; CHECK-BE:       @ %bb.0:
 ; CHECK-BE-NEXT:    rsb r2, r3, #32
 ; CHECK-BE-NEXT:    lsr r1, r1, r3
 ; CHECK-BE-NEXT:    orr r1, r1, r0, lsl r2
-; CHECK-BE-NEXT:    sub r2, r3, #32
-; CHECK-BE-NEXT:    cmp r2, #0
-; CHECK-BE-NEXT:    lsrge r1, r0, r2
+; CHECK-BE-NEXT:    subs r2, r3, #32
+; CHECK-BE-NEXT:    lsrpl r1, r0, r2
 ; CHECK-BE-NEXT:    mov r0, r1
 ; CHECK-BE-NEXT:    mov pc, lr
 
   %a = lshr i64 %x, %y
   %b = trunc i64 %a to i32
   ret i32 %b
 }

llvm/test/CodeGen/ARM/sat-to-bitop.ll

 ; x < 0 ? 0 : x
 ; 16-bit base test
 define i16 @sat0_base_16bit(i16 %x) #0 {
 ; CHECK-ARM-LABEL: sat0_base_16bit:
 ; CHECK-ARM:       @ %bb.0: @ %entry
 ; CHECK-ARM-NEXT:    lsl r1, r0, #16
 ; CHECK-ARM-NEXT:    asr r1, r1, #16
 ; CHECK-ARM-NEXT:    cmp r1, #0
-; CHECK-ARM-NEXT:    movlt r0, #0
+; CHECK-ARM-NEXT:    movmi r0, #0
 ; CHECK-ARM-NEXT:    mov pc, lr
 ;
 ; CHECK-T-LABEL: sat0_base_16bit:
 ; CHECK-T:       @ %bb.0: @ %entry
 ; CHECK-T-NEXT:    lsls r1, r0, #16
 ; CHECK-T-NEXT:    asrs r1, r1, #16
-; CHECK-T-NEXT:    cmp r1, #0
-; CHECK-T-NEXT:    bge .LBB1_2
+; CHECK-T-NEXT:    bpl .LBB1_2
 ; CHECK-T-NEXT:  @ %bb.1:
 ; CHECK-T-NEXT:    movs r0, #0
 ; CHECK-T-NEXT:  .LBB1_2: @ %entry
 ; CHECK-T-NEXT:    bx lr
 ;
 ; CHECK-T2-LABEL: sat0_base_16bit:
 ; CHECK-T2:       @ %bb.0: @ %entry
 ; CHECK-T2-NEXT:    sxth r1, r0
 ; CHECK-T2-NEXT:    cmp r1, #0
-; CHECK-T2-NEXT:    it lt
-; CHECK-T2-NEXT:    movlt r0, #0
+; CHECK-T2-NEXT:    it mi
+; CHECK-T2-NEXT:    movmi r0, #0
 ; CHECK-T2-NEXT:    bx lr
 entry:
   %cmpLow = icmp slt i16 %x, 0
   %saturateLow = select i1 %cmpLow, i16 0, i16 %x
   ret i16 %saturateLow
 }
 
 ; x < 0 ? 0 : x
 ; 8-bit base test
 define i8 @sat0_base_8bit(i8 %x) #0 {
 ; CHECK-ARM-LABEL: sat0_base_8bit:
 ; CHECK-ARM:       @ %bb.0: @ %entry
 ; CHECK-ARM-NEXT:    lsl r1, r0, #24
 ; CHECK-ARM-NEXT:    asr r1, r1, #24
 ; CHECK-ARM-NEXT:    cmp r1, #0
-; CHECK-ARM-NEXT:    movlt r0, #0
+; CHECK-ARM-NEXT:    movmi r0, #0
 ; CHECK-ARM-NEXT:    mov pc, lr
 ;
 ; CHECK-T-LABEL: sat0_base_8bit:
 ; CHECK-T:       @ %bb.0: @ %entry
 ; CHECK-T-NEXT:    lsls r1, r0, #24
 ; CHECK-T-NEXT:    asrs r1, r1, #24
-; CHECK-T-NEXT:    cmp r1, #0
-; CHECK-T-NEXT:    bge .LBB2_2
+; CHECK-T-NEXT:    bpl .LBB2_2
 ; CHECK-T-NEXT:  @ %bb.1:
 ; CHECK-T-NEXT:    movs r0, #0
 ; CHECK-T-NEXT:  .LBB2_2: @ %entry
 ; CHECK-T-NEXT:    bx lr
 ;
 ; CHECK-T2-LABEL: sat0_base_8bit:
 ; CHECK-T2:       @ %bb.0: @ %entry
 ; CHECK-T2-NEXT:    sxtb r1, r0
 ; CHECK-T2-NEXT:    cmp r1, #0
-; CHECK-T2-NEXT:    it lt
-; CHECK-T2-NEXT:    movlt r0, #0
+; CHECK-T2-NEXT:    it mi
+; CHECK-T2-NEXT:    movmi r0, #0
 ; CHECK-T2-NEXT:    bx lr
 entry:
   %cmpLow = icmp slt i8 %x, 0
   %saturateLow = select i1 %cmpLow, i8 0, i8 %x
   ret i8 %saturateLow
 }
 
 ; Test where the conditional is formed in a different way

 ; The following tests for patterns that should not transform into bitops
 ; but that are similar enough that could confuse the selector.
 
 ; x < 0 ? 0 : y where x and y does not properly match
 define i32 @no_sat0_incorrect_variable(i32 %x, i32 %y) #0 {
 ; CHECK-ARM-LABEL: no_sat0_incorrect_variable:
 ; CHECK-ARM:       @ %bb.0: @ %entry
 ; CHECK-ARM-NEXT:    cmp r0, #0
-; CHECK-ARM-NEXT:    movlt r1, #0
+; CHECK-ARM-NEXT:    movmi r1, #0
 ; CHECK-ARM-NEXT:    mov r0, r1
 ; CHECK-ARM-NEXT:    mov pc, lr
 ;
 ; CHECK-T-LABEL: no_sat0_incorrect_variable:
 ; CHECK-T:       @ %bb.0: @ %entry
 ; CHECK-T-NEXT:    cmp r0, #0
-; CHECK-T-NEXT:    bge .LBB8_2
+; CHECK-T-NEXT:    bpl .LBB8_2
 ; CHECK-T-NEXT:  @ %bb.1:
 ; CHECK-T-NEXT:    movs r1, #0
 ; CHECK-T-NEXT:  .LBB8_2: @ %entry
 ; CHECK-T-NEXT:    movs r0, r1
 ; CHECK-T-NEXT:    bx lr
 ;
 ; CHECK-T2-LABEL: no_sat0_incorrect_variable:
 ; CHECK-T2:       @ %bb.0: @ %entry
 ; CHECK-T2-NEXT:    cmp r0, #0
-; CHECK-T2-NEXT:    it lt
-; CHECK-T2-NEXT:    movlt r1, #0
+; CHECK-T2-NEXT:    it mi
+; CHECK-T2-NEXT:    movmi r1, #0
 ; CHECK-T2-NEXT:    mov r0, r1
 ; CHECK-T2-NEXT:    bx lr
 entry:
   %cmpLow = icmp slt i32 %x, 0
   %saturateLow = select i1 %cmpLow, i32 0, i32 %y
   ret i32 %saturateLow
 }
 
 ; x < 0 ? -1 : x
 define i32 @no_sat0_incorrect_constant(i32 %x) {
 ; CHECK-ARM-LABEL: no_sat0_incorrect_constant:
 ; CHECK-ARM:       @ %bb.0: @ %entry
 ; CHECK-ARM-NEXT:    cmp r0, #0
-; CHECK-ARM-NEXT:    mvnlt r0, #0
+; CHECK-ARM-NEXT:    mvnmi r0, #0
 ; CHECK-ARM-NEXT:    mov pc, lr
 ;
 ; CHECK-T-LABEL: no_sat0_incorrect_constant:
 ; CHECK-T:       @ %bb.0: @ %entry
 ; CHECK-T-NEXT:    cmp r0, #0
-; CHECK-T-NEXT:    bge .LBB9_2
+; CHECK-T-NEXT:    bpl .LBB9_2
 ; CHECK-T-NEXT:  @ %bb.1:
 ; CHECK-T-NEXT:    movs r0, #0
 ; CHECK-T-NEXT:    mvns r0, r0
 ; CHECK-T-NEXT:  .LBB9_2: @ %entry
 ; CHECK-T-NEXT:    bx lr
 ;
 ; CHECK-T2-LABEL: no_sat0_incorrect_constant:
 ; CHECK-T2:       @ %bb.0: @ %entry
 ; CHECK-T2-NEXT:    cmp r0, #0
-; CHECK-T2-NEXT:    it lt
-; CHECK-T2-NEXT:    movlt.w r0, #-1
+; CHECK-T2-NEXT:    it mi
+; CHECK-T2-NEXT:    movmi.w r0, #-1
 ; CHECK-T2-NEXT:    bx lr
 entry:
   %cmpLow = icmp slt i32 %x, 0
   %saturateLow = select i1 %cmpLow, i32 -1, i32 %x
   ret i32 %saturateLow
 }

llvm/test/CodeGen/ARM/select.ll

 entry:
     %tmp = icmp ugt i32 %a.u, %b.u
     %tmp1.s = select i1 %tmp, i32 2, i32 3
     ret i32 %tmp1.s
 }
 
 define double @f7(double %a, double %b) {
 ;CHECK-LABEL: f7:
-;CHECK: movlt
-;CHECK: movge
+;CHECK: movmi
+;CHECK: movpl
 ;CHECK-VFP-LABEL: f7:
 ;CHECK-VFP: vmovmi
     %tmp = fcmp olt double %a, 1.234e+00
     %tmp1 = select i1 %tmp, double -1.000e+00, double %b
     ret double %tmp1
 }
 
 ; <rdar://problem/7260094>

llvm/test/CodeGen/ARM/shift-i64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
 ; RUN: llc -mtriple=armv6m-eabi %s -o - | FileCheck %s --check-prefix=EXPAND
 
 define i64 @test_shl(i64 %val, i64 %amt) {
 ; CHECK-LABEL: test_shl:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    rsb r3, r2, #32
 ; CHECK-NEXT:    lsr r3, r0, r3
 ; CHECK-NEXT:    orr r1, r3, r1, lsl r2
-; CHECK-NEXT:    sub r3, r2, #32
-; CHECK-NEXT:    cmp r3, #0
-; CHECK-NEXT:    lslge r1, r0, r3
+; CHECK-NEXT:    subs r3, r2, #32
+; CHECK-NEXT:    lslpl r1, r0, r3
 ; CHECK-NEXT:    lsl r0, r0, r2
-; CHECK-NEXT:    movge r0, #0
+; CHECK-NEXT:    movpl r0, #0
 ; CHECK-NEXT:    mov pc, lr
 ;
 ; EXPAND-LABEL: test_shl:
 ; EXPAND:       @ %bb.0:
 ; EXPAND-NEXT:    .save {r7, lr}
 ; EXPAND-NEXT:    push {r7, lr}
 ; EXPAND-NEXT:    bl __aeabi_llsl
 ; EXPAND-NEXT:    pop {r7, pc}
   %res = shl i64 %val, %amt
   ret i64 %res
 }
 
 ; Explanation for lshr is pretty much the reverse of shl.
 define i64 @test_lshr(i64 %val, i64 %amt) {
 ; CHECK-LABEL: test_lshr:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    rsb r3, r2, #32
 ; CHECK-NEXT:    lsr r0, r0, r2
 ; CHECK-NEXT:    orr r0, r0, r1, lsl r3
-; CHECK-NEXT:    sub r3, r2, #32
-; CHECK-NEXT:    cmp r3, #0
-; CHECK-NEXT:    lsrge r0, r1, r3
+; CHECK-NEXT:    subs r3, r2, #32
+; CHECK-NEXT:    lsrpl r0, r1, r3
 ; CHECK-NEXT:    lsr r1, r1, r2
-; CHECK-NEXT:    movge r1, #0
+; CHECK-NEXT:    movpl r1, #0
 ; CHECK-NEXT:    mov pc, lr
 ;
 ; EXPAND-LABEL: test_lshr:
 ; EXPAND:       @ %bb.0:
 ; EXPAND-NEXT:    .save {r7, lr}
 ; EXPAND-NEXT:    push {r7, lr}
 ; EXPAND-NEXT:    bl __aeabi_llsr
 ; EXPAND-NEXT:    pop {r7, pc}
   %res = lshr i64 %val, %amt
   ret i64 %res
 }
 
 ; One minor difference for ashr: the high bits must be "hi >> 31" if the shift
 ; amount is large to get the right sign bit.
 define i64 @test_ashr(i64 %val, i64 %amt) {
 ; CHECK-LABEL: test_ashr:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    sub r12, r2, #32
 ; CHECK-NEXT:    asr r3, r1, r2
+; CHECK-NEXT:    subs r12, r2, #32
 ; CHECK-NEXT:    lsr r0, r0, r2
 ; CHECK-NEXT:    rsb r2, r2, #32
-; CHECK-NEXT:    cmp r12, #0
+; CHECK-NEXT:    asrpl r3, r1, #31
 ; CHECK-NEXT:    orr r0, r0, r1, lsl r2
-; CHECK-NEXT:    asrge r3, r1, #31
-; CHECK-NEXT:    asrge r0, r1, r12
+; CHECK-NEXT:    asrpl r0, r1, r12
 ; CHECK-NEXT:    mov r1, r3
 ; CHECK-NEXT:    mov pc, lr
 ;
 ; EXPAND-LABEL: test_ashr:
 ; EXPAND:       @ %bb.0:
 ; EXPAND-NEXT:    .save {r7, lr}
 ; EXPAND-NEXT:    push {r7, lr}
 ; EXPAND-NEXT:    bl __aeabi_lasr
 ; EXPAND-NEXT:    pop {r7, pc}
   %res = ashr i64 %val, %amt
   ret i64 %res
 }

llvm/test/CodeGen/Thumb/select.ll

 ; CHECK-EABI: bhi
 
 define double @f7(double %a, double %b) {
     %tmp = fcmp olt double %a, 1.234e+00
     %tmp1 = select i1 %tmp, double -1.000e+00, double %b
     ret double %tmp1
 }
 ; CHECK-LABEL: f7:
-; CHECK: {{blt|bge}}
-; CHECK: {{blt|bge}}
+; CHECK: {{bmi|bpl}}
+; CHECK: {{bmi|bpl}}
 ; CHECK: __ltdf2
 ; CHECK-EABI-LABEL: f7:
 ; CHECK-EABI: __aeabi_dcmplt
 ; CHECK-EABI: {{bne|beq}}
 ; CHECK-EABI: {{bne|beq}}
 
 define {i32, i32} @f8(i32 %a, i32 %b, i32 %c, i32 %d) {
 entry: