[PowerPC][NFC] Move current peephole optimization of RLDICR into a method

[lkail]

Summary

There might be more peephole optimizations on RLDICR, move current opt into a method.

[steven.zhang]

As talked, please confirm why we didn't set the Simplified flags. FWIK, this is a flag to indicate that, we have done some changes. We should set it.

[jsji]

LGTM. Please address the Simplified flag problem in another patch. Thanks.

[lkail]

This comment was removed by lkail.

[lkail]

llvm-svn: 364372

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

private:
   void initialize(MachineFunction &MFParm);
 
   // Perform peepholes.
   bool simplifyCode(void);
 
   // Perform peepholes.
   bool eliminateRedundantCompare(void);
   bool eliminateRedundantTOCSaves(std::map<MachineInstr *, bool> &TOCSaves);
+  void emitRLDICWhenLoweringJumpTables(MachineInstr &MI);
   void UpdateTOCSaves(std::map<MachineInstr *, bool> &TOCSaves,
                       MachineInstr *MI);
 
 public:
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<MachineDominatorTree>();
     AU.addPreserved<MachineDominatorTree>();
for (MachineInstr &MI : MBB) {
                 MI.getOperand(0).getReg())
             .add(Op1);
         ToErase = &MI;
         Simplified = true;
         NumOptADDLIs++;
         break;
       }
       case PPC::RLDICR: {
-        // We miss the opportunity to emit an RLDIC when lowering jump tables
-        // since ISEL sees only a single basic block. When selecting, the clear
-        // and shift left will be in different blocks.
-        unsigned SrcReg = MI.getOperand(1).getReg();
-        if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
-          break;
-
-        MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
-        if (SrcMI->getOpcode() != PPC::RLDICL)
-          break;
-        MachineOperand MOpSHSrc = SrcMI->getOperand(2);
-        MachineOperand MOpMBSrc = SrcMI->getOperand(3);
-        MachineOperand MOpSHMI = MI.getOperand(2);
-        MachineOperand MOpMEMI = MI.getOperand(3);
-        if (!(MOpSHSrc.isImm() && MOpMBSrc.isImm() &&
-              MOpSHMI.isImm() && MOpMEMI.isImm()))
-          break;
-        uint64_t SHSrc = MOpSHSrc.getImm();
-        uint64_t MBSrc = MOpMBSrc.getImm();
-        uint64_t SHMI = MOpSHMI.getImm();
-        uint64_t MEMI = MOpMEMI.getImm();
-        uint64_t NewSH = SHSrc + SHMI;
-        uint64_t NewMB = MBSrc - SHMI;
-        if (NewMB > 63 || NewSH > 63)
-          break;
-
-        // The bits cleared with RLDICL are [0, MBSrc).
-        // The bits cleared with RLDICR are (MEMI, 63].
-        // After the sequence, the bits cleared are:
-        // [0, MBSrc-SHMI) and (MEMI, 63).
-        //
-        // The bits cleared with RLDIC are [0, NewMB) and (63-NewSH, 63].
-        if ((63 - NewSH) != MEMI)
-          break;
-
-        LLVM_DEBUG(dbgs() << "Converting pair: ");
-        LLVM_DEBUG(SrcMI->dump());
-        LLVM_DEBUG(MI.dump());
-
-        MI.setDesc(TII->get(PPC::RLDIC));
-        MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
-        MI.getOperand(2).setImm(NewSH);
-        MI.getOperand(3).setImm(NewMB);
-
-        LLVM_DEBUG(dbgs() << "To: ");
-        LLVM_DEBUG(MI.dump());
-        NumRotatesCollapsed++;
+        emitRLDICWhenLoweringJumpTables(MI);
         break;
       }
       }
     }
 
     // If the last instruction was marked for elimination,
     // remove it now.
     if (ToErase) {
for (MachineBasicBlock &MBB2 : *MF) {
     }
 
     Simplified = true;
   }
 
   return Simplified;
 }
 
+// We miss the opportunity to emit an RLDIC when lowering jump tables
+// since ISEL sees only a single basic block. When selecting, the clear
+// and shift left will be in different blocks.
+void PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) {
+  if (MI.getOpcode() != PPC::RLDICR)
+    return;
+
+  unsigned SrcReg = MI.getOperand(1).getReg();
+  if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
+    return;
+
+  MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
+  if (SrcMI->getOpcode() != PPC::RLDICL)
+    return;
+
+  MachineOperand MOpSHSrc = SrcMI->getOperand(2);
+  MachineOperand MOpMBSrc = SrcMI->getOperand(3);
+  MachineOperand MOpSHMI = MI.getOperand(2);
+  MachineOperand MOpMEMI = MI.getOperand(3);
+  if (!(MOpSHSrc.isImm() && MOpMBSrc.isImm() && MOpSHMI.isImm() &&
+        MOpMEMI.isImm()))
+    return;
+
+  uint64_t SHSrc = MOpSHSrc.getImm();
+  uint64_t MBSrc = MOpMBSrc.getImm();
+  uint64_t SHMI = MOpSHMI.getImm();
+  uint64_t MEMI = MOpMEMI.getImm();
+  uint64_t NewSH = SHSrc + SHMI;
+  uint64_t NewMB = MBSrc - SHMI;
+  if (NewMB > 63 || NewSH > 63)
+    return;
+
+  // The bits cleared with RLDICL are [0, MBSrc).
+  // The bits cleared with RLDICR are (MEMI, 63].
+  // After the sequence, the bits cleared are:
+  // [0, MBSrc-SHMI) and (MEMI, 63).
+  //
+  // The bits cleared with RLDIC are [0, NewMB) and (63-NewSH, 63].
+  if ((63 - NewSH) != MEMI)
+    return;
+
+  LLVM_DEBUG(dbgs() << "Converting pair: ");
+  LLVM_DEBUG(SrcMI->dump());
+  LLVM_DEBUG(MI.dump());
+
+  MI.setDesc(TII->get(PPC::RLDIC));
+  MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
+  MI.getOperand(2).setImm(NewSH);
+  MI.getOperand(3).setImm(NewMB);
+
+  LLVM_DEBUG(dbgs() << "To: ");
+  LLVM_DEBUG(MI.dump());
+  NumRotatesCollapsed++;
+}
+
 } // end default namespace
 
 INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE,
                       "PowerPC MI Peephole Optimization", false, false)
 INITIALIZE_PASS_END(PPCMIPeephole, DEBUG_TYPE,
                     "PowerPC MI Peephole Optimization", false, false)
 
 char PPCMIPeephole::ID = 0;
 FunctionPass*
 llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); }