This is an archive of the discontinued LLVM Phabricator instance.

Differential D63711

[ARM] MVE VPT Blocks
ClosedPublic

Authored by SjoerdMeijer on Jun 24 2019, 5:36 AM.

Details

Reviewers
samparker
dmgreen
simon_tatham
t.p.northover
Commits
rG74ec25a197ab: [ARM] MVE VPT Blocks
rL364298: [ARM] MVE VPT Blocks
Summary

A minor iteration enabling more efficient VPT Block code generation: consecutive VPT
predicated statements, predicated on the same condition, will be placed within
the same VPT Block. This essentially is an exercise to write some more tests
for the next step, which should be more generic also merging instructions when
they are not consecutive.

Diff Detail

Event Timeline

SjoerdMeijer created this revision.Jun 24 2019, 5:36 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 24 2019, 5:36 AM
Herald added subscribers: hiraditya, kristof.beyls, javed.absar. · View Herald Transcript
samparker added inline comments.Jun 24 2019, 6:35 AM
llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
403

Do we need to keep track of LastMI? Looks like it's only used to get an iterator once out of the loop, but it is derived from MBIter anyway...

llvm/test/CodeGen/ARM/mve-vpt-block5.mir
66

So why do we have two bundles here? I'm missing something...

SjoerdMeijer marked 2 inline comments as done.Jun 24 2019, 6:46 AM
SjoerdMeijer added inline comments.
llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
403

cheers, that looks like a good clean-up, will look into that.

llvm/test/CodeGen/ARM/mve-vpt-block5.mir
66

because there is a MOV in between the 2nd and 3rd MVE_VMINNMf32 instructions:

$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
SjoerdMeijer updated this revision to Diff 206209.Jun 24 2019, 7:05 AM

Feedback addressed

samparker added inline comments.Jun 24 2019, 8:53 AM
llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
408–409

But we don't need LastMI at all :)

llvm/test/CodeGen/ARM/mve-vpt-block5.mir
66

cheers!

SjoerdMeijer marked an inline comment as done.Jun 24 2019, 9:17 AM
SjoerdMeijer added inline comments.
llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
408–409

I think I see what you mean, you want to see:

finalizeBundle(Block, VPSTInsertPos.getInstrIterator(), MBIter);

But they are different iterators:

  • MBIter is a MachineBasicBlock::iterator
  • and finalizeBundle expects a MachineBasicBlock::instr_iterator

I didn't really investigate the difference to be honest, but must be related to iterating over instructions of blocks or bundles.

samparker accepted this revision.Jun 24 2019, 9:17 AM

Ok, please ignore my nonsense. LGTM

This revision is now accepted and ready to land.Jun 24 2019, 9:17 AM
SjoerdMeijer added a comment.Jun 24 2019, 9:20 AM

No worries, thanks a lot for reviewing!

Closed by commit rL364298: [ARM] MVE VPT Blocks (authored by SjoerdMeijer). · Explain WhyJun 25 2019, 5:08 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
15 lines
test/
CodeGen/
ARM/
77 lines
82 lines
90 lines
88 lines
84 lines

Diff 206202

llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp

Show First 20 Lines • Show All 382 Lines • ▼ Show 20 Lines while (MBIter != EndIter) {
if (Pred == ARMVCC::None) { if (Pred == ARMVCC::None) {
++MBIter; ++MBIter;
continue; continue;
} }
MachineInstrBuilder MIBuilder = MachineInstrBuilder MIBuilder =
BuildMI(Block, MBIter, dl, TII->get(ARM::MVE_VPST)); BuildMI(Block, MBIter, dl, TII->get(ARM::MVE_VPST));
// The mask value for the VPST instruction is T = 0b1000 = 8
MIBuilder.addImm(VPTMaskValue::T);
MachineInstr *LastMI = MI; MachineInstr *LastMI = MI;
MachineBasicBlock::iterator InsertPos = MIBuilder.getInstr(); MachineBasicBlock::iterator InsertPos = MIBuilder.getInstr();
int VPTInstCnt = 1;
ARMVCC::VPTCodes NextPred;
// The mask value for the VPST instruction is T = 0b1000 = 8 do {
MIBuilder.addImm(VPTMaskValue::T); ++MBIter;
MachineInstr *NextInst = &*MBIter;
NextPred = getVPTInstrPredicate(*NextInst, PredReg);
LastMI = NextInst;
samparkerUnsubmitted
Not Done
ReplyInline Actions

Do we need to keep track of LastMI? Looks like it's only used to get an iterator once out of the loop, but it is derived from MBIter anyway...

samparker: Do we need to keep track of LastMI? Looks like it's only used to get an iterator once out of…
SjoerdMeijerAuthorUnsubmitted
Done
ReplyInline Actions

cheers, that looks like a good clean-up, will look into that.

SjoerdMeijer: cheers, that looks like a good clean-up, will look into that.
VPTInstCnt++;
} while (NextPred != ARMVCC::None && NextPred == Pred && VPTInstCnt < 4);
finalizeBundle(Block, InsertPos.getInstrIterator(), finalizeBundle(Block, InsertPos.getInstrIterator(),
++LastMI->getIterator()); ++LastMI->getIterator());
samparkerUnsubmitted
Not Done
ReplyInline Actions

But we don't need LastMI at all :)

samparker: But we don't need LastMI at all :)
SjoerdMeijerAuthorUnsubmitted
Done
ReplyInline Actions

I think I see what you mean, you want to see:

finalizeBundle(Block, VPSTInsertPos.getInstrIterator(), MBIter);

But they are different iterators:

  • MBIter is a MachineBasicBlock::iterator
  • and finalizeBundle expects a MachineBasicBlock::instr_iterator

I didn't really investigate the difference to be honest, but must be related to iterating over instructions of blocks or bundles.

SjoerdMeijer: I think I see what you mean, you want to see: finalizeBundle(Block, VPSTInsertPos.
Modified = true; Modified = true;
LLVM_DEBUG(dbgs() << "VPT block created for: "; MI->dump();); LLVM_DEBUG(dbgs() << "VPT block created for: "; MI->dump(););
++MBIter; ++MBIter;
} }
return Modified; return Modified;
} }
Show All 24 Lines

llvm/test/CodeGen/ARM/mve-vpt-block2.mir

  • This file was added.
# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
entry:
%conv.i = zext i16 %p to i32
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
%1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive2, <4 x float> %0, <4 x float> %b, i32 %conv.i) #2
ret <4 x float> %1
}
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
declare void @llvm.stackprotector(i8*, i8**) #2
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
...
---
name: test_vminnmq_m_f32_v2
alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins:
- { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' }
- { reg: '$q3', virtual-reg: '' }
- { reg: '$r0', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack: []
constants: []
body: |
bb.0.entry:
liveins: $q0, $q1, $q2, $q3, $r0
; CHECK: MVE_VPST 8, implicit-def $p0
; CHECK-NEXT: renamable $q0 = nnan ninf nsz MVE_VMINNMf32
; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VMINNMf32
$vpr = VMSR_P0 killed $r0, 14, $noreg
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1
$q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
tBX_RET 14, $noreg, implicit $q0
...

llvm/test/CodeGen/ARM/mve-vpt-block3.mir

  • This file was added.
# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
entry:
%conv.i = zext i16 %p to i32
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
%1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %0, <4 x float> %0, i32 %conv.i) #2
%2 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %1, <4 x float> %b, i32 %conv.i) #2
%3 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive2, <4 x float> %2, <4 x float> %b, i32 %conv.i) #2
ret <4 x float> %3
}
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
declare void @llvm.stackprotector(i8*, i8**) #2
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
...
---
name: test_vminnmq_m_f32_v2
alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins:
- { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' }
- { reg: '$q3', virtual-reg: '' }
- { reg: '$r0', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack: []
constants: []
body: |
bb.0.entry:
liveins: $q0, $q1, $q2, $q3, $r0
; CHECK: MVE_VPST 8, implicit-def $p0
; CHECK-NEXT: renamable $q2 = nnan ninf nsz MVE_VMINNMf32
; CHECK-NEXT: renamable $q2 = nnan ninf nsz MVE_VMINNMf32
; CHECK-NEXT: renamable $q0 = nnan ninf nsz MVE_VMINNMf32
; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VMINNMf32
$vpr = VMSR_P0 killed $r0, 14, $noreg
renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2
renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q2, 1, renamable $vpr, undef renamable $q2
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1
$q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
tBX_RET 14, $noreg, implicit $q0
...

llvm/test/CodeGen/ARM/mve-vpt-block4.mir

  • This file was added.
# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
entry:
%conv.i = zext i16 %p to i32
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
%1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %0, <4 x float> %0, i32 %conv.i) #2
%2 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %1, <4 x float> %b, i32 %conv.i) #2
%3 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %2, <4 x float> %b, i32 %conv.i) #2
%4 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive2, <4 x float> %3, <4 x float> %b, i32 %conv.i) #2
ret <4 x float> %4
}
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
declare void @llvm.stackprotector(i8*, i8**) #2
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
...
---
name: test_vminnmq_m_f32_v2
alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins:
- { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' }
- { reg: '$q3', virtual-reg: '' }
- { reg: '$r0', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack: []
constants: []
body: |
bb.0.entry:
liveins: $q0, $q1, $q2, $q3, $r0
; CHECK: MVE_VPST 8, implicit-def $p0
; CHECK-NEXT: renamable $q2 = nnan ninf nsz MVE_VMINNMf32
; CHECK-NEXT: renamable $q2 = nnan ninf nsz MVE_VMINNMf32
; CHECK-NEXT: renamable $q0 = nnan ninf nsz MVE_VMINNMf32
; CHECK-NEXT: renamable $q0 = nnan ninf nsz MVE_VMINNMf32
; CHECK-NEXT: }
; CHECK-NEXT: BUNDLE {{.*}} {
; CHECK-NEXT: MVE_VPST 8, implicit-def $p0
; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VMINNMf32
; CHECK-NEXT: $q0 = MVE_VORR
; CHECK-NEXT: }
$vpr = VMSR_P0 killed $r0, 14, $noreg
renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2
renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q2, 1, renamable $vpr, undef renamable $q2
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, renamable $q3, 1, renamable $vpr, undef renamable $q0
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1
$q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
tBX_RET 14, $noreg, implicit $q0
...

llvm/test/CodeGen/ARM/mve-vpt-block5.mir

  • This file was added.
# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
entry:
%conv.i = zext i16 %p to i32
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
%1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %0, <4 x float> %0, i32 %conv.i) #2
%2 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %1, <4 x float> %b, i32 %conv.i) #2
%3 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %2, <4 x float> %b, i32 %conv.i) #2
ret <4 x float> %3
}
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
...
---
name: test_vminnmq_m_f32_v2
alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins:
- { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' }
- { reg: '$r0', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack: []
constants: []
body: |
bb.0.entry:
liveins: $q0, $q1, $q2, $r0
; CHECK: BUNDLE {{.*}} {
samparkerUnsubmitted
Not Done
ReplyInline Actions

So why do we have two bundles here? I'm missing something...

samparker: So why do we have two bundles here? I'm missing something...
SjoerdMeijerAuthorUnsubmitted
Done
ReplyInline Actions

because there is a MOV in between the 2nd and 3rd MVE_VMINNMf32 instructions:

$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
SjoerdMeijer: because there is a MOV in between the 2nd and 3rd MVE_VMINNMf32 instructions: $q3 = MVE_VORR…
samparkerUnsubmitted
Not Done
ReplyInline Actions

cheers!

samparker: cheers!
; CHECK-NEXT: MVE_VPST 8, implicit-def $p0
; CHECK-NEXT: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, internal renamable $q3, 1, renamable $vpr, undef renamable $q1
; CHECK-NEXT: $q3 = MVE_VORR $q0, $q0, 0, $noreg, internal undef $q3
; CHECK-NEXT: }
; CHECK-NEXT: BUNDLE {{.*}} {
; CHECK-NEXT: MVE_VPST 8, implicit-def $p0
; CHECK-NEXT: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
; CHECK-NEXT: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
; CHECK-NEXT: tBX_RET 14, $noreg, implicit internal $q0
; CHECK-NEXT: }
$vpr = VMSR_P0 killed $r0, 14, $noreg
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
tBX_RET 14, $noreg, implicit $q0
...

llvm/test/CodeGen/ARM/mve-vpt-block6.mir

  • This file was added.
# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p1, i16 zeroext %p2) local_unnamed_addr #0 {
entry:
%conv.i = zext i16 %p1 to i32
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
%conv.i5 = zext i16 %p2 to i32
%1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %0, <4 x float> %b, i32 %conv.i5) #2
ret <4 x float> %1
}
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
...
---
name: test_vminnmq_m_f32_v2
alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins:
- { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' }
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack: []
constants: []
body: |
bb.0.entry:
liveins: $q0, $q1, $q2, $r0, $r1
; CHECK: BUNDLE {{.*}} {
; CHECK-NEXT: MVE_VPST 8, implicit-def $p0
; CHECK-NEXT: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed renamable $vpr, killed renamable $q3
; CHECK-NEXT: $vpr = VMSR_P0 killed $r1, 14, $noreg
; CHECK-NEXT: }
; CHECK-NEXT: BUNDLE {{.*}} {
; CHECK-NEXT: MVE_VPST 8, implicit-def $p0
; CHECK-NEXT: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
; CHECK-NEXT: tBX_RET 14, $noreg, implicit internal $q0
; CHECK-NEXT: }
$vpr = VMSR_P0 killed $r0, 14, $noreg
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed renamable $vpr, killed renamable $q3
$vpr = VMSR_P0 killed $r1, 14, $noreg
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
tBX_RET 14, $noreg, implicit $q0
...