AArch64: Add support for reading pc using llvm.read_register.

[pcc]

Summary

This is useful for allowing code to efficiently take an address
that can be later mapped onto debug info. Currently the hwasan
pass achieves this by taking the address of the current function:
http://llvm-cs.pcc.me.uk/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp#921

but this costs two instructions (plus a GOT entry in PIC code) per function
with stack variables. This will allow the cost to be reduced to a single
instruction.

[pcc]

• Instead of defining a pseudo-instruction, simply use the immediate form of the ADR instruction

[eugenis]

LGTM

llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp

void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
   case TargetOpcode::PATCHABLE_TAIL_CALL:
     LowerPATCHABLE_TAIL_CALL(*MI);
     return;
 
   case AArch64::HWASAN_CHECK_MEMACCESS:
     LowerHWASAN_CHECK_MEMACCESS(*MI);
     return;
 
+  case AArch64::ADR_PC: {
+    auto Sym = OutContext.createTempSymbol();
+    OutStreamer->EmitLabel(Sym);
+    EmitToStreamer(*OutStreamer,
+                   MCInstBuilder(AArch64::ADR)
+                       .addReg(MI->getOperand(0).getReg())
+                       .addExpr(MCSymbolRefExpr::create(Sym, OutContext)));
+    return;
+  }
+
   case AArch64::SEH_StackAlloc:
     TS->EmitARM64WinCFIAllocStack(MI->getOperand(0).getImm());
     return;
 
   case AArch64::SEH_SaveFPLR:
     TS->EmitARM64WinCFISaveFPLR(MI->getOperand(0).getImm());
     return;
 

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

bool AArch64DAGToDAGISel::tryReadRegister(SDNode *N) {
   if (Reg != -1) {
     ReplaceNode(N, CurDAG->getMachineNode(
                        AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other,
                        CurDAG->getTargetConstant(Reg, DL, MVT::i32),
                        N->getOperand(0)));
     return true;
   }
 
+  if (RegString->getString() == "pc") {
+    ReplaceNode(N, CurDAG->getMachineNode(AArch64::ADR_PC, DL,
+                                          N->getSimpleValueType(0), MVT::Other,
+                                          N->getOperand(0)));
+    return true;
+  }
+
   return false;
 }
 
 // Lower the write_register intrinsic to an MSR instruction node if the special
 // register string argument is either of the form detailed in the ALCE (the
 // form described in getIntOperandsFromRegsterString) or is a named register
 // known by the MSR SysReg mapper.
 bool AArch64DAGToDAGISel::tryWriteRegister(SDNode *N) {

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 def : Pat<(AArch64adr tconstpool:$cp), (ADR tconstpool:$cp)>;
 def : Pat<(AArch64adr tblockaddress:$cp), (ADR tblockaddress:$cp)>;
 def : Pat<(AArch64adr texternalsym:$sym), (ADR texternalsym:$sym)>;
 def : Pat<(AArch64adr tjumptable:$sym), (ADR tjumptable:$sym)>;
 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
 def : Pat<(AArch64adrp texternalsym:$sym), (ADRP texternalsym:$sym)>;
 
+// An ADR pseudo-instruction that returns the address of itself.
+// Used to implement read_register("pc").
+def ADR_PC : Pseudo<(outs GPR64:$addr), (ins), []>, Sched<[WriteI]>;
+
 //===----------------------------------------------------------------------===//
 // Unconditional branch (register) instructions.
 //===----------------------------------------------------------------------===//
 
 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
 def RET  : BranchReg<0b0010, "ret", []>;
 def DRPS : SpecialReturn<0b0101, "drps">;
 def ERET : SpecialReturn<0b0100, "eret">;

llvm/test/CodeGen/AArch64/read-pc.ll

+; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s
+
+define i64 @read_pc() {
+  ; CHECK: .Ltmp0:
+  ; CHECK-NEXT: adr x0, .Ltmp0
+  %pc = call i64 @llvm.read_register.i64(metadata !0)
+  ret i64 %pc
+}
+
+declare i64 @llvm.read_register.i64(metadata) nounwind
+
+!0 = !{!"pc"}