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Differential D62941

[PATCH 1/2] [AArch64][AsmParser] Provide better diagnostics for SVE predicates
ClosedPublic

Authored by c-rhodes on Jun 6 2019, 1:32 AM.

Details

Reviewers
sdesmalen
SjoerdMeijer
rovka
Commits
rGf7305484841f: [AArch64][AsmParser] Provide better diagnostics for SVE predicates
rL362779: [AArch64][AsmParser] Provide better diagnostics for SVE predicates

Diff Detail

Event Timeline

c-rhodes created this revision.Jun 6 2019, 1:32 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 6 2019, 1:32 AM
Herald added subscribers: kristof.beyls, tschuett, javed.absar. · View Herald Transcript
c-rhodes added a child revision: D62942: [PATCH 2/2] [AArch64][AsmParser] error on unexpected SVE predicate type suffix.Jun 6 2019, 1:35 AM
SjoerdMeijer accepted this revision.Jun 6 2019, 1:39 AM

Looks like a good improvement to me.

This revision is now accepted and ready to land.Jun 6 2019, 1:39 AM
Closed by commit rGf7305484841f: [AArch64][AsmParser] Provide better diagnostics for SVE predicates (authored by c-rhodes). · Explain WhyJun 7 2019, 1:35 AM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: hiraditya. · View Herald TranscriptJun 7 2019, 1:35 AM

Revision Contents

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Diff 203511

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Show First 20 Lines • Show All 4,464 Lines • ▼ Show 20 Lines case Match_InvalidSVEPattern:
return Error(Loc, "invalid predicate pattern"); return Error(Loc, "invalid predicate pattern");
case Match_InvalidSVEPredicateAnyReg: case Match_InvalidSVEPredicateAnyReg:
case Match_InvalidSVEPredicateBReg: case Match_InvalidSVEPredicateBReg:
case Match_InvalidSVEPredicateHReg: case Match_InvalidSVEPredicateHReg:
case Match_InvalidSVEPredicateSReg: case Match_InvalidSVEPredicateSReg:
case Match_InvalidSVEPredicateDReg: case Match_InvalidSVEPredicateDReg:
return Error(Loc, "invalid predicate register."); return Error(Loc, "invalid predicate register.");
case Match_InvalidSVEPredicate3bAnyReg: case Match_InvalidSVEPredicate3bAnyReg:
return Error(Loc, "invalid restricted predicate register, expected p0..p7 (without element suffix)");
case Match_InvalidSVEPredicate3bBReg: case Match_InvalidSVEPredicate3bBReg:
return Error(Loc, "invalid restricted predicate register, expected p0.b..p7.b");
case Match_InvalidSVEPredicate3bHReg: case Match_InvalidSVEPredicate3bHReg:
return Error(Loc, "invalid restricted predicate register, expected p0.h..p7.h");
case Match_InvalidSVEPredicate3bSReg: case Match_InvalidSVEPredicate3bSReg:
return Error(Loc, "invalid restricted predicate register, expected p0.s..p7.s");
case Match_InvalidSVEPredicate3bDReg: case Match_InvalidSVEPredicate3bDReg:
return Error(Loc, "restricted predicate has range [0, 7]."); return Error(Loc, "invalid restricted predicate register, expected p0.d..p7.d");
case Match_InvalidSVEExactFPImmOperandHalfOne: case Match_InvalidSVEExactFPImmOperandHalfOne:
return Error(Loc, "Invalid floating point constant, expected 0.5 or 1.0."); return Error(Loc, "Invalid floating point constant, expected 0.5 or 1.0.");
case Match_InvalidSVEExactFPImmOperandHalfTwo: case Match_InvalidSVEExactFPImmOperandHalfTwo:
return Error(Loc, "Invalid floating point constant, expected 0.5 or 2.0."); return Error(Loc, "Invalid floating point constant, expected 0.5 or 2.0.");
case Match_InvalidSVEExactFPImmOperandZeroOne: case Match_InvalidSVEExactFPImmOperandZeroOne:
return Error(Loc, "Invalid floating point constant, expected 0.0 or 1.0."); return Error(Loc, "Invalid floating point constant, expected 0.0 or 1.0.");
default: default:
llvm_unreachable("unexpected error code!"); llvm_unreachable("unexpected error code!");
▲ Show 20 Lines • Show All 1,272 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SVE/abs-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Element size specifiers should match. // Element size specifiers should match.
abs z0.h, p0/m, z0.b abs z0.h, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: abs z0.h, p0/m, z0.b // CHECK-NEXT: abs z0.h, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Missing predicate suffix // Missing predicate suffix
abs z29.d, p7, z29.d abs z29.d, p7, z29.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: abs z29.d, p7, z29.d // CHECK-NEXT: abs z29.d, p7, z29.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
abs z0.b, p8/m, z0.b abs z0.b, p8/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: abs z0.b, p8/m, z0.b // CHECK-NEXT: abs z0.b, p8/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
abs z0.h, p8/m, z0.h abs z0.h, p8/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: abs z0.h, p8/m, z0.h // CHECK-NEXT: abs z0.h, p8/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
abs z0.s, p8/m, z0.s abs z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: abs z0.s, p8/m, z0.s // CHECK-NEXT: abs z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
abs z0.d, p8/m, z0.d abs z0.d, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: abs z0.d, p8/m, z0.d // CHECK-NEXT: abs z0.d, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/add-diagnostics.s

Show All 25 Lines
// Missing predicate suffix // Missing predicate suffix
add z29.d, p7, z29.d, z8.d add z29.d, p7, z29.d, z8.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: add z29.d, p7, z29.d, z8.d // CHECK-NEXT: add z29.d, p7, z29.d, z8.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
add z22.b, p8/m, z22.b, z11.b add z22.b, p8/m, z22.b, z11.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: add z22.b, p8/m, z22.b, z11.b // CHECK-NEXT: add z22.b, p8/m, z22.b, z11.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
add z22.h, p8/m, z22.h, z6.h add z22.h, p8/m, z22.h, z6.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: add z22.h, p8/m, z22.h, z6.h // CHECK-NEXT: add z22.h, p8/m, z22.h, z6.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
add z30.s, p8/m, z30.s, z13.s add z30.s, p8/m, z30.s, z13.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: add z30.s, p8/m, z30.s, z13.s // CHECK-NEXT: add z30.s, p8/m, z30.s, z13.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
add z29.d, p8/m, z29.d, z8.d add z29.d, p8/m, z29.d, z8.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: add z29.d, p8/m, z29.d, z8.d // CHECK-NEXT: add z29.d, p8/m, z29.d, z8.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Source and Destination Registers must match // Source and Destination Registers must match
add z19.b, p4/m, z20.b, z13.b add z19.b, p4/m, z20.b, z13.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
▲ Show 20 Lines • Show All 108 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SVE/and-diagnostics.s

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
// CHECK-NEXT: and z21.d, z5.d, z26.b // CHECK-NEXT: and z21.d, z5.d, z26.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate out of restricted predicate range // Predicate out of restricted predicate range
and z0.d, p8/z, z0.d, z1.d and z0.d, p8/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: and z0.d, p8/z, z0.d, z1.d // CHECK-NEXT: and z0.d, p8/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate register must have .b suffix // Predicate register must have .b suffix
and p0.h, p0/z, p0.h, p1.h and p0.h, p0/z, p0.h, p1.h
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SVE/andv-diagnostics.s

Show All 23 Lines
// CHECK-NEXT: andv v0.2d, p7, z31.d // CHECK-NEXT: andv v0.2d, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
andv h0, p8, z31.h andv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: andv h0, p8, z31.h // CHECK-NEXT: andv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d movprfx z31.d, p7/z, z6.d
andv d0, p7, z31.d andv d0, p7, z31.d
Show All 9 Lines

llvm/test/MC/AArch64/SVE/asr-diagnostics.s

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
// CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.h // CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
asr z0.b, p8/m, z0.b, z1.b asr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: asr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: asr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
Show All 23 Lines

llvm/test/MC/AArch64/SVE/asrr-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
asrr z0.b, p8/m, z0.b, z0.b asrr z0.b, p8/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: asrr z0.b, p8/m, z0.b, z0.b // CHECK-NEXT: asrr z0.b, p8/m, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
asrr z0.b, p0/m, z0.b, z0.d asrr z0.b, p0/m, z0.b, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: asrr z0.b, p0/m, z0.b, z0.d // CHECK-NEXT: asrr z0.b, p0/m, z0.b, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Show All 9 Lines

llvm/test/MC/AArch64/SVE/bic-diagnostics.s

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
// CHECK-NEXT: bic z21.d, z5.d, z26.b // CHECK-NEXT: bic z21.d, z5.d, z26.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate out of restricted predicate range // Predicate out of restricted predicate range
bic z0.d, p8/z, z0.d, z1.d bic z0.d, p8/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: bic z0.d, p8/z, z0.d, z1.d // CHECK-NEXT: bic z0.d, p8/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate register must have .b suffix // Predicate register must have .b suffix
bic p0.h, p0/z, p0.h, p1.h bic p0.h, p0/z, p0.h, p1.h
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SVE/clasta-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
clasta w0, p8, w0, z31.b clasta w0, p8, w0, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: clasta w0, p8, w0, z31.b // CHECK-NEXT: clasta w0, p8, w0, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
clasta w0, p7, x0, z31.b clasta w0, p7, x0, z31.b
▲ Show 20 Lines • Show All 97 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SVE/clastb-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
clastb w0, p8, w0, z31.b clastb w0, p8, w0, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: clastb w0, p8, w0, z31.b // CHECK-NEXT: clastb w0, p8, w0, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
clastb w0, p7, x0, z31.b clastb w0, p7, x0, z31.b
▲ Show 20 Lines • Show All 97 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SVE/cls-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
cls z31.b, p8/m, z31.b cls z31.b, p8/m, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: cls z31.b, p8/m, z31.b // CHECK-NEXT: cls z31.b, p8/m, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
cls z31.b, p7/m, z31.h cls z31.b, p7/m, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: cls z31.b, p7/m, z31.h // CHECK-NEXT: cls z31.b, p7/m, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/clz-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
clz z31.b, p8/m, z31.b clz z31.b, p8/m, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: clz z31.b, p8/m, z31.b // CHECK-NEXT: clz z31.b, p8/m, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
clz z31.b, p7/m, z31.h clz z31.b, p7/m, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: clz z31.b, p7/m, z31.h // CHECK-NEXT: clz z31.b, p7/m, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/cmpeq-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate out of range. // Restricted predicate out of range.
cmpeq p0.b, p8/z, z0.b, z0.b cmpeq p0.b, p8/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: cmpeq p0.b, p8/z, z0.b, z0.b // CHECK-NEXT: cmpeq p0.b, p8/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid predicate operation // Invalid predicate operation
cmpeq p0.b, p0/m, z0.b, z0.b cmpeq p0.b, p0/m, z0.b, z0.b
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llvm/test/MC/AArch64/SVE/cmpge-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate out of range. // Restricted predicate out of range.
cmpge p0.b, p8/z, z0.b, z0.b cmpge p0.b, p8/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: cmpge p0.b, p8/z, z0.b, z0.b // CHECK-NEXT: cmpge p0.b, p8/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid predicate operation // Invalid predicate operation
cmpge p0.b, p0/m, z0.b, z0.b cmpge p0.b, p0/m, z0.b, z0.b
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llvm/test/MC/AArch64/SVE/cmpgt-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate out of range. // Restricted predicate out of range.
cmpgt p0.b, p8/z, z0.b, z0.b cmpgt p0.b, p8/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: cmpgt p0.b, p8/z, z0.b, z0.b // CHECK-NEXT: cmpgt p0.b, p8/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid predicate operation // Invalid predicate operation
cmpgt p0.b, p0/m, z0.b, z0.b cmpgt p0.b, p0/m, z0.b, z0.b
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llvm/test/MC/AArch64/SVE/cmphi-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate out of range. // Restricted predicate out of range.
cmphi p0.b, p8/z, z0.b, z0.b cmphi p0.b, p8/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: cmphi p0.b, p8/z, z0.b, z0.b // CHECK-NEXT: cmphi p0.b, p8/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid predicate operation // Invalid predicate operation
cmphi p0.b, p0/m, z0.b, z0.b cmphi p0.b, p0/m, z0.b, z0.b
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llvm/test/MC/AArch64/SVE/cmphs-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate out of range. // Restricted predicate out of range.
cmphs p0.b, p8/z, z0.b, z0.b cmphs p0.b, p8/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: cmphs p0.b, p8/z, z0.b, z0.b // CHECK-NEXT: cmphs p0.b, p8/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid predicate operation // Invalid predicate operation
cmphs p0.b, p0/m, z0.b, z0.b cmphs p0.b, p0/m, z0.b, z0.b
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llvm/test/MC/AArch64/SVE/cmple-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate out of range. // Restricted predicate out of range.
cmple p0.b, p8/z, z0.b, z0.b cmple p0.b, p8/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: cmple p0.b, p8/z, z0.b, z0.b // CHECK-NEXT: cmple p0.b, p8/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid predicate operation // Invalid predicate operation
cmple p0.b, p0/m, z0.b, z0.b cmple p0.b, p0/m, z0.b, z0.b
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llvm/test/MC/AArch64/SVE/cmplo-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate out of range. // Restricted predicate out of range.
cmplo p0.b, p8/z, z0.b, z0.b cmplo p0.b, p8/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: cmplo p0.b, p8/z, z0.b, z0.b // CHECK-NEXT: cmplo p0.b, p8/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid predicate operation // Invalid predicate operation
cmplo p0.b, p0/m, z0.b, z0.b cmplo p0.b, p0/m, z0.b, z0.b
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llvm/test/MC/AArch64/SVE/cmpls-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate out of range. // Restricted predicate out of range.
cmpls p0.b, p8/z, z0.b, z0.b cmpls p0.b, p8/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: cmpls p0.b, p8/z, z0.b, z0.b // CHECK-NEXT: cmpls p0.b, p8/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid predicate operation // Invalid predicate operation
cmpls p0.b, p0/m, z0.b, z0.b cmpls p0.b, p0/m, z0.b, z0.b
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llvm/test/MC/AArch64/SVE/cmplt-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate out of range. // Restricted predicate out of range.
cmplt p0.b, p8/z, z0.b, z0.b cmplt p0.b, p8/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: cmplt p0.b, p8/z, z0.b, z0.b // CHECK-NEXT: cmplt p0.b, p8/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid predicate operation // Invalid predicate operation
cmplt p0.b, p0/m, z0.b, z0.b cmplt p0.b, p0/m, z0.b, z0.b
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llvm/test/MC/AArch64/SVE/cmpne-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate out of range. // Restricted predicate out of range.
cmpne p0.b, p8/z, z0.b, z0.b cmpne p0.b, p8/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: cmpne p0.b, p8/z, z0.b, z0.b // CHECK-NEXT: cmpne p0.b, p8/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid predicate operation // Invalid predicate operation
cmpne p0.b, p0/m, z0.b, z0.b cmpne p0.b, p0/m, z0.b, z0.b
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llvm/test/MC/AArch64/SVE/cnot-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
cnot z31.b, p8/m, z31.b cnot z31.b, p8/m, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: cnot z31.b, p8/m, z31.b // CHECK-NEXT: cnot z31.b, p8/m, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
cnot z31.b, p7/m, z31.h cnot z31.b, p7/m, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: cnot z31.b, p7/m, z31.h // CHECK-NEXT: cnot z31.b, p7/m, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/cnt-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
cnt z31.b, p8/m, z31.b cnt z31.b, p8/m, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: cnt z31.b, p8/m, z31.b // CHECK-NEXT: cnt z31.b, p8/m, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
cnt z31.b, p7/m, z31.h cnt z31.b, p7/m, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: cnt z31.b, p7/m, z31.h // CHECK-NEXT: cnt z31.b, p7/m, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/compact-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid predicate // Invalid predicate
compact z23.d, p8, z13.d compact z23.d, p8, z13.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: compact z23.d, p8, z13.d // CHECK-NEXT: compact z23.d, p8, z13.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid element widths // Invalid element widths
compact z31.s, p7, z31.d compact z31.s, p7, z31.d
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llvm/test/MC/AArch64/SVE/eor-diagnostics.s

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// CHECK-NEXT: eor z21.d, z5.d, z26.b // CHECK-NEXT: eor z21.d, z5.d, z26.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate out of restricted predicate range // Predicate out of restricted predicate range
eor z0.d, p8/z, z0.d, z1.d eor z0.d, p8/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: eor z0.d, p8/z, z0.d, z1.d // CHECK-NEXT: eor z0.d, p8/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate register must have .b suffix // Predicate register must have .b suffix
eor p0.h, p0/z, p0.h, p1.h eor p0.h, p0/z, p0.h, p1.h
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llvm/test/MC/AArch64/SVE/eorv-diagnostics.s

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// CHECK-NEXT: eorv v0.2d, p7, z31.d // CHECK-NEXT: eorv v0.2d, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
eorv h0, p8, z31.h eorv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: eorv h0, p8, z31.h // CHECK-NEXT: eorv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d movprfx z31.d, p7/z, z6.d
eorv d0, p7, z31.d eorv d0, p7, z31.d
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llvm/test/MC/AArch64/SVE/fabd-diagnostics.s

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// CHECK-NEXT: fabd z0.h, p7/m, z0.h, z31.s // CHECK-NEXT: fabd z0.h, p7/m, z0.h, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fabd z0.h, p8/m, z0.h, z31.h fabd z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fabd z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fabd z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fabs-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fabs z31.h, p8/m, z31.h fabs z31.h, p8/m, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fabs z31.h, p8/m, z31.h // CHECK-NEXT: fabs z31.h, p8/m, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
fabs z31.b, p7/m, z31.b fabs z31.b, p7/m, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fabs z31.b, p7/m, z31.b // CHECK-NEXT: fabs z31.b, p7/m, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fabs z31.h, p7/m, z31.s fabs z31.h, p7/m, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fabs z31.h, p7/m, z31.s // CHECK-NEXT: fabs z31.h, p7/m, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fadd-diagnostics.s

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fadd z0.h, z1.s, z2.s // CHECK-NEXT: fadd z0.h, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fadd z0.h, p8/m, z0.h, z31.h fadd z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fadd z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fadd z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d movprfx z0.d, p0/z, z7.d
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llvm/test/MC/AArch64/SVE/fadda-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
fadda b0, p7, b0, z31.b fadda b0, p7, b0, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fadda b0, p7, b0, z31.b // CHECK-NEXT: fadda b0, p7, b0, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fadda h0, p7, h1, z31.h fadda h0, p7, h1, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: fadda h0, p7, h1, z31.h // CHECK-NEXT: fadda h0, p7, h1, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fadda h0, p8, h0, z31.h fadda h0, p8, h0, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fadda h0, p8, h0, z31.h // CHECK-NEXT: fadda h0, p8, h0, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fadda v0.8h, p7, v0.8h, z31.h fadda v0.8h, p7, v0.8h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fadda v0.8h, p7, v0.8h, z31.h // CHECK-NEXT: fadda v0.8h, p7, v0.8h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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llvm/test/MC/AArch64/SVE/faddv-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
faddv b0, p7, z31.b faddv b0, p7, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: faddv b0, p7, z31.b // CHECK-NEXT: faddv b0, p7, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
faddv h0, p8, z31.h faddv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: faddv h0, p8, z31.h // CHECK-NEXT: faddv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Result must be a valid FP register. // Result must be a valid FP register.
faddv v0, p7, z31.h faddv v0, p7, z31.h
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llvm/test/MC/AArch64/SVE/fcadd-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Source and Destination Registers must match // Source and Destination Registers must match
fcadd z0.d, p2/m, z1.d, z2.d, #90 fcadd z0.d, p2/m, z1.d, z2.d, #90
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: fcadd z0.d, p2/m, z1.d, z2.d, #90 // CHECK-NEXT: fcadd z0.d, p2/m, z1.d, z2.d, #90
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate out of range. // Restricted predicate out of range.
fcadd z0.d, p8/m, z0.d, z1.d, #90 fcadd z0.d, p8/m, z0.d, z1.d, #90
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fcadd z0.d, p8/m, z0.d, z1.d, #90 // CHECK-NEXT: fcadd z0.d, p8/m, z0.d, z1.d, #90
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid rotation // Invalid rotation
fcadd z0.d, p0/m, z0.d, z1.d, #0 fcadd z0.d, p0/m, z0.d, z1.d, #0
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llvm/test/MC/AArch64/SVE/fcmla-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate out of range. // Restricted predicate out of range.
fcmla z0.d, p8/m, z1.d, z2.d, #0 fcmla z0.d, p8/m, z1.d, z2.d, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fcmla z0.d, p8/m, z1.d, z2.d, #0 // CHECK-NEXT: fcmla z0.d, p8/m, z1.d, z2.d, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid rotation // Invalid rotation
fcmla z0.d, p0/m, z1.d, z2.d, #360 fcmla z0.d, p0/m, z1.d, z2.d, #360
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llvm/test/MC/AArch64/SVE/fcvt-diagnostics.s

Show All 11 Lines
fcvt z0.d, p0/m, z0.d fcvt z0.d, p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvt z0.d, p0/m, z0.d // CHECK-NEXT: fcvt z0.d, p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
fcvt z0.h, p8/m, z0.s fcvt z0.h, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fcvt z0.h, p8/m, z0.s // CHECK-NEXT: fcvt z0.h, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fcvtzs-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
fcvtzs z0.h, p0/m, z0.s fcvtzs z0.h, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtzs z0.h, p0/m, z0.s // CHECK-NEXT: fcvtzs z0.h, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtzs z0.h, p0/m, z0.d fcvtzs z0.h, p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtzs z0.h, p0/m, z0.d // CHECK-NEXT: fcvtzs z0.h, p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
fcvtzs z0.h, p8/m, z0.h fcvtzs z0.h, p8/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fcvtzs z0.h, p8/m, z0.h // CHECK-NEXT: fcvtzs z0.h, p8/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fcvtzu-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
fcvtzu z0.h, p0/m, z0.s fcvtzu z0.h, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtzu z0.h, p0/m, z0.s // CHECK-NEXT: fcvtzu z0.h, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtzu z0.h, p0/m, z0.d fcvtzu z0.h, p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtzu z0.h, p0/m, z0.d // CHECK-NEXT: fcvtzu z0.h, p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
fcvtzu z0.h, p8/m, z0.h fcvtzu z0.h, p8/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fcvtzu z0.h, p8/m, z0.h // CHECK-NEXT: fcvtzu z0.h, p8/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fdiv-diagnostics.s

Show All 22 Lines
// CHECK-NEXT: fdiv z0.h, p7/m, z0.h, z31.s // CHECK-NEXT: fdiv z0.h, p7/m, z0.h, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fdiv z0.h, p8/m, z0.h, z31.h fdiv z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fdiv z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fdiv z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fdivr-diagnostics.s

Show All 22 Lines
// CHECK-NEXT: fdivr z0.h, p7/m, z0.h, z31.s // CHECK-NEXT: fdivr z0.h, p7/m, z0.h, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fdivr z0.h, p8/m, z0.h, z31.h fdivr z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fdivr z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fdivr z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fmad-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fmad z0.h, p8/m, z1.h, z2.h fmad z0.h, p8/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmad z0.h, p8/m, z1.h, z2.h // CHECK-NEXT: fmad z0.h, p8/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
fmad z0.s, p7/m, z1.h, z2.h fmad z0.s, p7/m, z1.h, z2.h
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llvm/test/MC/AArch64/SVE/fmax-diagnostics.s

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
// CHECK-NEXT: fmax z0.h, p7/m, z0.h, z31.s // CHECK-NEXT: fmax z0.h, p7/m, z0.h, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fmax z0.h, p8/m, z0.h, z31.h fmax z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmax z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fmax z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fmaxnm-diagnostics.s

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
// CHECK-NEXT: fmaxnm z0.h, p7/m, z0.h, z31.s // CHECK-NEXT: fmaxnm z0.h, p7/m, z0.h, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fmaxnm z0.h, p8/m, z0.h, z31.h fmaxnm z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmaxnm z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fmaxnm z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
fmaxnmv b0, p7, z31.b fmaxnmv b0, p7, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmaxnmv b0, p7, z31.b // CHECK-NEXT: fmaxnmv b0, p7, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmaxnmv h0, p8, z31.h fmaxnmv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmaxnmv h0, p8, z31.h // CHECK-NEXT: fmaxnmv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Result must be a valid FP register. // Result must be a valid FP register.
fmaxnmv v0, p7, z31.h fmaxnmv v0, p7, z31.h
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llvm/test/MC/AArch64/SVE/fmaxv-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
fmaxv b0, p7, z31.b fmaxv b0, p7, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmaxv b0, p7, z31.b // CHECK-NEXT: fmaxv b0, p7, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmaxv h0, p8, z31.h fmaxv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmaxv h0, p8, z31.h // CHECK-NEXT: fmaxv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Result must be a valid FP register. // Result must be a valid FP register.
fmaxv v0, p7, z31.h fmaxv v0, p7, z31.h
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llvm/test/MC/AArch64/SVE/fmin-diagnostics.s

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
// CHECK-NEXT: fmin z0.h, p7/m, z0.h, z31.s // CHECK-NEXT: fmin z0.h, p7/m, z0.h, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fmin z0.h, p8/m, z0.h, z31.h fmin z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmin z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fmin z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fminnm-diagnostics.s

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
// CHECK-NEXT: fminnm z0.h, p7/m, z0.h, z31.s // CHECK-NEXT: fminnm z0.h, p7/m, z0.h, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fminnm z0.h, p8/m, z0.h, z31.h fminnm z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fminnm z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fminnm z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fminnmv-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
fminnmv b0, p7, z31.b fminnmv b0, p7, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fminnmv b0, p7, z31.b // CHECK-NEXT: fminnmv b0, p7, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fminnmv h0, p8, z31.h fminnmv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fminnmv h0, p8, z31.h // CHECK-NEXT: fminnmv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Result must be a valid FP register. // Result must be a valid FP register.
fminnmv v0, p7, z31.h fminnmv v0, p7, z31.h
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llvm/test/MC/AArch64/SVE/fminv-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
fminv b0, p7, z31.b fminv b0, p7, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fminv b0, p7, z31.b // CHECK-NEXT: fminv b0, p7, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fminv h0, p8, z31.h fminv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fminv h0, p8, z31.h // CHECK-NEXT: fminv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Result must be a valid FP register. // Result must be a valid FP register.
fminv v0, p7, z31.h fminv v0, p7, z31.h
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llvm/test/MC/AArch64/SVE/fmla-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fmla z0.h, p8/m, z1.h, z2.h fmla z0.h, p8/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmla z0.h, p8/m, z1.h, z2.h // CHECK-NEXT: fmla z0.h, p8/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
fmla z0.s, p7/m, z1.h, z2.h fmla z0.s, p7/m, z1.h, z2.h
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llvm/test/MC/AArch64/SVE/fmls-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fmls z0.h, p8/m, z1.h, z2.h fmls z0.h, p8/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmls z0.h, p8/m, z1.h, z2.h // CHECK-NEXT: fmls z0.h, p8/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
fmls z0.s, p7/m, z1.h, z2.h fmls z0.s, p7/m, z1.h, z2.h
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llvm/test/MC/AArch64/SVE/fmsb-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fmsb z0.h, p8/m, z1.h, z2.h fmsb z0.h, p8/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmsb z0.h, p8/m, z1.h, z2.h // CHECK-NEXT: fmsb z0.h, p8/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
fmsb z0.s, p7/m, z1.h, z2.h fmsb z0.s, p7/m, z1.h, z2.h
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llvm/test/MC/AArch64/SVE/fmul-diagnostics.s

Show First 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
// CHECK-NEXT: fmul z0.h, z1.s, z2.s // CHECK-NEXT: fmul z0.h, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fmul z0.h, p8/m, z0.h, z31.h fmul z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmul z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fmul z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d movprfx z0.d, p0/z, z7.d
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llvm/test/MC/AArch64/SVE/fmulx-diagnostics.s

Show All 22 Lines
// CHECK-NEXT: fmulx z0.h, p7/m, z0.h, z31.s // CHECK-NEXT: fmulx z0.h, p7/m, z0.h, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fmulx z0.h, p8/m, z0.h, z31.h fmulx z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmulx z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fmulx z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fneg-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fneg z31.h, p8/m, z31.h fneg z31.h, p8/m, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fneg z31.h, p8/m, z31.h // CHECK-NEXT: fneg z31.h, p8/m, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
fneg z31.b, p7/m, z31.b fneg z31.b, p7/m, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fneg z31.b, p7/m, z31.b // CHECK-NEXT: fneg z31.b, p7/m, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fneg z31.h, p7/m, z31.s fneg z31.h, p7/m, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fneg z31.h, p7/m, z31.s // CHECK-NEXT: fneg z31.h, p7/m, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fnmad-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fnmad z0.h, p8/m, z1.h, z2.h fnmad z0.h, p8/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fnmad z0.h, p8/m, z1.h, z2.h // CHECK-NEXT: fnmad z0.h, p8/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
fnmad z0.s, p7/m, z1.h, z2.h fnmad z0.s, p7/m, z1.h, z2.h
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llvm/test/MC/AArch64/SVE/fnmla-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fnmla z0.h, p8/m, z1.h, z2.h fnmla z0.h, p8/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fnmla z0.h, p8/m, z1.h, z2.h // CHECK-NEXT: fnmla z0.h, p8/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
fnmla z0.s, p7/m, z1.h, z2.h fnmla z0.s, p7/m, z1.h, z2.h
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llvm/test/MC/AArch64/SVE/fnmls-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fnmls z0.h, p8/m, z1.h, z2.h fnmls z0.h, p8/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fnmls z0.h, p8/m, z1.h, z2.h // CHECK-NEXT: fnmls z0.h, p8/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
fnmls z0.s, p7/m, z1.h, z2.h fnmls z0.s, p7/m, z1.h, z2.h
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llvm/test/MC/AArch64/SVE/fnmsb-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fnmsb z0.h, p8/m, z1.h, z2.h fnmsb z0.h, p8/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fnmsb z0.h, p8/m, z1.h, z2.h // CHECK-NEXT: fnmsb z0.h, p8/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
fnmsb z0.s, p7/m, z1.h, z2.h fnmsb z0.s, p7/m, z1.h, z2.h
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llvm/test/MC/AArch64/SVE/frecpx-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
frecpx z0.b, p0/m, z0.b frecpx z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: frecpx z0.b, p0/m, z0.b // CHECK-NEXT: frecpx z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frecpx z0.s, p0/z, z0.s frecpx z0.s, p0/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: frecpx z0.s, p0/z, z0.s // CHECK-NEXT: frecpx z0.s, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frecpx z0.s, p8/m, z0.s frecpx z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: frecpx z0.s, p8/m, z0.s // CHECK-NEXT: frecpx z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/frinta-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
frinta z0.b, p0/m, z0.b frinta z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: frinta z0.b, p0/m, z0.b // CHECK-NEXT: frinta z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frinta z0.s, p0/z, z0.s frinta z0.s, p0/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: frinta z0.s, p0/z, z0.s // CHECK-NEXT: frinta z0.s, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frinta z0.s, p8/m, z0.s frinta z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: frinta z0.s, p8/m, z0.s // CHECK-NEXT: frinta z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/frinti-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
frinti z0.b, p0/m, z0.b frinti z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: frinti z0.b, p0/m, z0.b // CHECK-NEXT: frinti z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frinti z0.s, p0/z, z0.s frinti z0.s, p0/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: frinti z0.s, p0/z, z0.s // CHECK-NEXT: frinti z0.s, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frinti z0.s, p8/m, z0.s frinti z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: frinti z0.s, p8/m, z0.s // CHECK-NEXT: frinti z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/frintm-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
frintm z0.b, p0/m, z0.b frintm z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: frintm z0.b, p0/m, z0.b // CHECK-NEXT: frintm z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frintm z0.s, p0/z, z0.s frintm z0.s, p0/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: frintm z0.s, p0/z, z0.s // CHECK-NEXT: frintm z0.s, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frintm z0.s, p8/m, z0.s frintm z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: frintm z0.s, p8/m, z0.s // CHECK-NEXT: frintm z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/frintn-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
frintn z0.b, p0/m, z0.b frintn z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: frintn z0.b, p0/m, z0.b // CHECK-NEXT: frintn z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frintn z0.s, p0/z, z0.s frintn z0.s, p0/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: frintn z0.s, p0/z, z0.s // CHECK-NEXT: frintn z0.s, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frintn z0.s, p8/m, z0.s frintn z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: frintn z0.s, p8/m, z0.s // CHECK-NEXT: frintn z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/frintp-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
frintp z0.b, p0/m, z0.b frintp z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: frintp z0.b, p0/m, z0.b // CHECK-NEXT: frintp z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frintp z0.s, p0/z, z0.s frintp z0.s, p0/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: frintp z0.s, p0/z, z0.s // CHECK-NEXT: frintp z0.s, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frintp z0.s, p8/m, z0.s frintp z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: frintp z0.s, p8/m, z0.s // CHECK-NEXT: frintp z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/frintx-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
frintx z0.b, p0/m, z0.b frintx z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: frintx z0.b, p0/m, z0.b // CHECK-NEXT: frintx z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frintx z0.s, p0/z, z0.s frintx z0.s, p0/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: frintx z0.s, p0/z, z0.s // CHECK-NEXT: frintx z0.s, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frintx z0.s, p8/m, z0.s frintx z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: frintx z0.s, p8/m, z0.s // CHECK-NEXT: frintx z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/frintz-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
frintz z0.b, p0/m, z0.b frintz z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: frintz z0.b, p0/m, z0.b // CHECK-NEXT: frintz z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frintz z0.s, p0/z, z0.s frintz z0.s, p0/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: frintz z0.s, p0/z, z0.s // CHECK-NEXT: frintz z0.s, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
frintz z0.s, p8/m, z0.s frintz z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: frintz z0.s, p8/m, z0.s // CHECK-NEXT: frintz z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fscale-diagnostics.s

Show All 22 Lines
// CHECK-NEXT: fscale z0.h, p7/m, z0.h, z31.s // CHECK-NEXT: fscale z0.h, p7/m, z0.h, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fscale z0.h, p8/m, z0.h, z31.h fscale z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fscale z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fscale z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fsqrt-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
fsqrt z0.b, p0/m, z0.b fsqrt z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fsqrt z0.b, p0/m, z0.b // CHECK-NEXT: fsqrt z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fsqrt z0.s, p0/z, z0.s fsqrt z0.s, p0/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: fsqrt z0.s, p0/z, z0.s // CHECK-NEXT: fsqrt z0.s, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fsqrt z0.s, p8/m, z0.s fsqrt z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fsqrt z0.s, p8/m, z0.s // CHECK-NEXT: fsqrt z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/fsub-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fsub z0.h, z1.s, z2.s // CHECK-NEXT: fsub z0.h, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fsub z0.h, p8/m, z0.h, z31.h fsub z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fsub z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fsub z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d movprfx z0.d, p0/z, z7.d
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llvm/test/MC/AArch64/SVE/fsubr-diagnostics.s

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// CHECK-NEXT: fsubr z0.h, p7/m, z0.h, z31.s // CHECK-NEXT: fsubr z0.h, p7/m, z0.h, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
fsubr z0.h, p8/m, z0.h, z31.h fsubr z0.h, p8/m, z0.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fsubr z0.h, p8/m, z0.h, z31.h // CHECK-NEXT: fsubr z0.h, p8/m, z0.h, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/lasta-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
lasta w0, p8, z31.b lasta w0, p8, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: lasta w0, p8, z31.b // CHECK-NEXT: lasta w0, p8, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
lasta x0, p7, z31.b lasta x0, p7, z31.b
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llvm/test/MC/AArch64/SVE/lastb-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
lastb w0, p8, z31.b lastb w0, p8, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: lastb w0, p8, z31.b // CHECK-NEXT: lastb w0, p8, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
lastb x0, p7, z31.b lastb x0, p7, z31.b
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llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s

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// CHECK-NEXT: ld1b z27.d, p1/z, [x26, #8, MUL VL] // CHECK-NEXT: ld1b z27.d, p1/z, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1b z27.b, p8/z, [x29, #1, MUL VL] ld1b z27.b, p8/z, [x29, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1b z27.b, p8/z, [x29, #1, MUL VL] // CHECK-NEXT: ld1b z27.b, p8/z, [x29, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1b z9.h, p8/z, [x25, #1, MUL VL] ld1b z9.h, p8/z, [x25, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1b z9.h, p8/z, [x25, #1, MUL VL] // CHECK-NEXT: ld1b z9.h, p8/z, [x25, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1b z12.s, p8/z, [x13, #1, MUL VL] ld1b z12.s, p8/z, [x13, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1b z12.s, p8/z, [x13, #1, MUL VL] // CHECK-NEXT: ld1b z12.s, p8/z, [x13, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1b z4.d, p8/z, [x11, #1, MUL VL] ld1b z4.d, p8/z, [x11, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1b z4.d, p8/z, [x11, #1, MUL VL] // CHECK-NEXT: ld1b z4.d, p8/z, [x11, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld1b { }, p0/z, [x1, #1, MUL VL] ld1b { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s

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// CHECK-NEXT: ld1d z27.d, p1/z, [x26, #8, MUL VL] // CHECK-NEXT: ld1d z27.d, p1/z, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1d z4.d, p8/z, [x11, #1, MUL VL] ld1d z4.d, p8/z, [x11, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1d z4.d, p8/z, [x11, #1, MUL VL] // CHECK-NEXT: ld1d z4.d, p8/z, [x11, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld1d { }, p0/z, [x1, #1, MUL VL] ld1d { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s

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// CHECK-NEXT: ld1h z27.d, p1/z, [x26, #8, MUL VL] // CHECK-NEXT: ld1h z27.d, p1/z, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1h z9.h, p8/z, [x25, #1, MUL VL] ld1h z9.h, p8/z, [x25, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1h z9.h, p8/z, [x25, #1, MUL VL] // CHECK-NEXT: ld1h z9.h, p8/z, [x25, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1h z12.s, p8/z, [x13, #1, MUL VL] ld1h z12.s, p8/z, [x13, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1h z12.s, p8/z, [x13, #1, MUL VL] // CHECK-NEXT: ld1h z12.s, p8/z, [x13, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1h z4.d, p8/z, [x11, #1, MUL VL] ld1h z4.d, p8/z, [x11, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1h z4.d, p8/z, [x11, #1, MUL VL] // CHECK-NEXT: ld1h z4.d, p8/z, [x11, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld1h { }, p0/z, [x1, #1, MUL VL] ld1h { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ld1rb-diagnostics.s

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// CHECK-NEXT: ld1rb z0.b, p1/z, [x0, #64] // CHECK-NEXT: ld1rb z0.b, p1/z, [x0, #64]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1rb z0.b, p8/z, [x0] ld1rb z0.b, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1rb z0.b, p8/z, [x0] // CHECK-NEXT: ld1rb z0.b, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d movprfx z31.d, p7/z, z6.d
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llvm/test/MC/AArch64/SVE/ld1rd-diagnostics.s

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// CHECK-NEXT: ld1rd z0.s, p1/z, [x0] // CHECK-NEXT: ld1rd z0.s, p1/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1rd z0.d, p8/z, [x0] ld1rd z0.d, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1rd z0.d, p8/z, [x0] // CHECK-NEXT: ld1rd z0.d, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d movprfx z31.d, p7/z, z6.d
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llvm/test/MC/AArch64/SVE/ld1rh-diagnostics.s

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// CHECK-NEXT: ld1rh z0.b, p1/z, [x0] // CHECK-NEXT: ld1rh z0.b, p1/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1rh z0.h, p8/z, [x0] ld1rh z0.h, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1rh z0.h, p8/z, [x0] // CHECK-NEXT: ld1rh z0.h, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d movprfx z31.d, p7/z, z6.d
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llvm/test/MC/AArch64/SVE/ld1rsb-diagnostics.s

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// CHECK-NEXT: ld1rsb z0.b, p1/z, [x0] // CHECK-NEXT: ld1rsb z0.b, p1/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1rsb z0.h, p8/z, [x0] ld1rsb z0.h, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1rsb z0.h, p8/z, [x0] // CHECK-NEXT: ld1rsb z0.h, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d movprfx z31.d, p7/z, z6.d
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llvm/test/MC/AArch64/SVE/ld1rsh-diagnostics.s

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// CHECK-NEXT: ld1rsh z0.h, p1/z, [x0] // CHECK-NEXT: ld1rsh z0.h, p1/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1rsh z0.s, p8/z, [x0] ld1rsh z0.s, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1rsh z0.s, p8/z, [x0] // CHECK-NEXT: ld1rsh z0.s, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d movprfx z31.d, p7/z, z6.d
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llvm/test/MC/AArch64/SVE/ld1rsw-diagnostics.s

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// CHECK-NEXT: ld1rsw z0.s, p1/z, [x0] // CHECK-NEXT: ld1rsw z0.s, p1/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1rsw z0.d, p8/z, [x0] ld1rsw z0.d, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1rsw z0.d, p8/z, [x0] // CHECK-NEXT: ld1rsw z0.d, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d movprfx z31.d, p7/z, z6.d
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llvm/test/MC/AArch64/SVE/ld1rw-diagnostics.s

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// CHECK-NEXT: ld1rw z0.h, p1/z, [x0] // CHECK-NEXT: ld1rw z0.h, p1/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1rw z0.s, p8/z, [x0] ld1rw z0.s, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1rw z0.s, p8/z, [x0] // CHECK-NEXT: ld1rw z0.s, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d movprfx z31.d, p7/z, z6.d
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llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s

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// CHECK-NEXT: ld1sb z27.d, p1/z, [x26, #8, MUL VL] // CHECK-NEXT: ld1sb z27.d, p1/z, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1sb z9.h, p8/z, [x25, #1, MUL VL] ld1sb z9.h, p8/z, [x25, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1sb z9.h, p8/z, [x25, #1, MUL VL] // CHECK-NEXT: ld1sb z9.h, p8/z, [x25, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sb z12.s, p8/z, [x13, #1, MUL VL] ld1sb z12.s, p8/z, [x13, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1sb z12.s, p8/z, [x13, #1, MUL VL] // CHECK-NEXT: ld1sb z12.s, p8/z, [x13, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sb z4.d, p8/z, [x11, #1, MUL VL] ld1sb z4.d, p8/z, [x11, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1sb z4.d, p8/z, [x11, #1, MUL VL] // CHECK-NEXT: ld1sb z4.d, p8/z, [x11, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld1sb { }, p0/z, [x1, #1, MUL VL] ld1sb { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s

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// CHECK-NEXT: ld1sh z27.d, p1/z, [x26, #8, MUL VL] // CHECK-NEXT: ld1sh z27.d, p1/z, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1sh z12.s, p8/z, [x13, #1, MUL VL] ld1sh z12.s, p8/z, [x13, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1sh z12.s, p8/z, [x13, #1, MUL VL] // CHECK-NEXT: ld1sh z12.s, p8/z, [x13, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1sh z4.d, p8/z, [x11, #1, MUL VL] ld1sh z4.d, p8/z, [x11, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1sh z4.d, p8/z, [x11, #1, MUL VL] // CHECK-NEXT: ld1sh z4.d, p8/z, [x11, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld1sh { }, p0/z, [x1, #1, MUL VL] ld1sh { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s

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// CHECK-NEXT: ld1sw z27.d, p1/z, [x26, #8, MUL VL] // CHECK-NEXT: ld1sw z27.d, p1/z, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1sw z4.d, p8/z, [x11, #1, MUL VL] ld1sw z4.d, p8/z, [x11, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1sw z4.d, p8/z, [x11, #1, MUL VL] // CHECK-NEXT: ld1sw z4.d, p8/z, [x11, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld1sw { }, p0/z, [x1, #1, MUL VL] ld1sw { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s

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// CHECK-NEXT: ld1w z27.d, p1/z, [x26, #8, MUL VL] // CHECK-NEXT: ld1w z27.d, p1/z, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ld1w z12.s, p8/z, [x13, #1, MUL VL] ld1w z12.s, p8/z, [x13, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1w z12.s, p8/z, [x13, #1, MUL VL] // CHECK-NEXT: ld1w z12.s, p8/z, [x13, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld1w z4.d, p8/z, [x11, #1, MUL VL] ld1w z4.d, p8/z, [x11, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld1w z4.d, p8/z, [x11, #1, MUL VL] // CHECK-NEXT: ld1w z4.d, p8/z, [x11, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld1w { }, p0/z, [x1, #1, MUL VL] ld1w { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ld2b-diagnostics.s

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ld2b { z0.b, z1.b }, p0/z, [x0, w0, uxtw] ld2b { z0.b, z1.b }, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
// CHECK-NEXT: ld2b { z0.b, z1.b }, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld2b { z0.b, z1.b }, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
ld2b {z2.b, z3.b}, p8/z, [x15, #10, MUL VL] ld2b {z2.b, z3.b}, p8/z, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld2b {z2.b, z3.b}, p8/z, [x15, #10, MUL VL] // CHECK-NEXT: ld2b {z2.b, z3.b}, p8/z, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld2b { }, p0/z, [x0] ld2b { }, p0/z, [x0]
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llvm/test/MC/AArch64/SVE/ld2d-diagnostics.s

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ld2d { z0.d, z1.d }, p0/z, [x0, w0, uxtw] ld2d { z0.d, z1.d }, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
// CHECK-NEXT: ld2d { z0.d, z1.d }, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld2d { z0.d, z1.d }, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
ld2d {z2.d, z3.d}, p8/z, [x15, #10, MUL VL] ld2d {z2.d, z3.d}, p8/z, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld2d {z2.d, z3.d}, p8/z, [x15, #10, MUL VL] // CHECK-NEXT: ld2d {z2.d, z3.d}, p8/z, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld2d { }, p0/z, [x0] ld2d { }, p0/z, [x0]
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llvm/test/MC/AArch64/SVE/ld2h-diagnostics.s

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ld2h { z0.h, z1.h }, p0/z, [x0, w0, uxtw] ld2h { z0.h, z1.h }, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
ld2h {z2.h, z3.h}, p8/z, [x15, #10, MUL VL] ld2h {z2.h, z3.h}, p8/z, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld2h {z2.h, z3.h}, p8/z, [x15, #10, MUL VL] // CHECK-NEXT: ld2h {z2.h, z3.h}, p8/z, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld2h { }, p0/z, [x0] ld2h { }, p0/z, [x0]
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llvm/test/MC/AArch64/SVE/ld2w-diagnostics.s

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ld2w { z0.s, z1.s }, p0/z, [x0, w0, uxtw] ld2w { z0.s, z1.s }, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
// CHECK-NEXT: ld2w { z0.s, z1.s }, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld2w { z0.s, z1.s }, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
ld2w {z2.s, z3.s}, p8/z, [x15, #10, MUL VL] ld2w {z2.s, z3.s}, p8/z, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld2w {z2.s, z3.s}, p8/z, [x15, #10, MUL VL] // CHECK-NEXT: ld2w {z2.s, z3.s}, p8/z, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld2w { }, p0/z, [x0] ld2w { }, p0/z, [x0]
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llvm/test/MC/AArch64/SVE/ld3b-diagnostics.s

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ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, w0, uxtw] ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
// CHECK-NEXT: ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
ld3b {z2.b, z3.b, z4.b}, p8/z, [x15, #10, MUL VL] ld3b {z2.b, z3.b, z4.b}, p8/z, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld3b {z2.b, z3.b, z4.b}, p8/z, [x15, #10, MUL VL] // CHECK-NEXT: ld3b {z2.b, z3.b, z4.b}, p8/z, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld3b { }, p0/z, [x0] ld3b { }, p0/z, [x0]
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llvm/test/MC/AArch64/SVE/ld3d-diagnostics.s

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ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, w0, uxtw] ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
// CHECK-NEXT: ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
ld3d {z2.d, z3.d, z4.d}, p8/z, [x15, #10, MUL VL] ld3d {z2.d, z3.d, z4.d}, p8/z, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld3d {z2.d, z3.d, z4.d}, p8/z, [x15, #10, MUL VL] // CHECK-NEXT: ld3d {z2.d, z3.d, z4.d}, p8/z, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld3d { }, p0/z, [x0] ld3d { }, p0/z, [x0]
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llvm/test/MC/AArch64/SVE/ld3h-diagnostics.s

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ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, w0, uxtw] ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
ld3h {z2.h, z3.h, z4.h}, p8/z, [x15, #10, MUL VL] ld3h {z2.h, z3.h, z4.h}, p8/z, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld3h {z2.h, z3.h, z4.h}, p8/z, [x15, #10, MUL VL] // CHECK-NEXT: ld3h {z2.h, z3.h, z4.h}, p8/z, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld3h { }, p0/z, [x0] ld3h { }, p0/z, [x0]
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llvm/test/MC/AArch64/SVE/ld3w-diagnostics.s

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ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, w0, uxtw] ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
// CHECK-NEXT: ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
ld3w {z2.s, z3.s, z4.s}, p8/z, [x15, #10, MUL VL] ld3w {z2.s, z3.s, z4.s}, p8/z, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld3w {z2.s, z3.s, z4.s}, p8/z, [x15, #10, MUL VL] // CHECK-NEXT: ld3w {z2.s, z3.s, z4.s}, p8/z, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld3w { }, p0/z, [x0] ld3w { }, p0/z, [x0]
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llvm/test/MC/AArch64/SVE/ld4b-diagnostics.s

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ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, w0, uxtw] ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
// CHECK-NEXT: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
ld4b {z2.b, z3.b, z4.b, z5.b}, p8/z, [x15, #10, MUL VL] ld4b {z2.b, z3.b, z4.b, z5.b}, p8/z, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld4b {z2.b, z3.b, z4.b, z5.b}, p8/z, [x15, #10, MUL VL] // CHECK-NEXT: ld4b {z2.b, z3.b, z4.b, z5.b}, p8/z, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld4b { }, p0/z, [x0] ld4b { }, p0/z, [x0]
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llvm/test/MC/AArch64/SVE/ld4d-diagnostics.s

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ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0, uxtw] ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
// CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
ld4d {z2.d, z3.d, z4.d, z5.d}, p8/z, [x15, #10, MUL VL] ld4d {z2.d, z3.d, z4.d, z5.d}, p8/z, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld4d {z2.d, z3.d, z4.d, z5.d}, p8/z, [x15, #10, MUL VL] // CHECK-NEXT: ld4d {z2.d, z3.d, z4.d, z5.d}, p8/z, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld4d { }, p0/z, [x0] ld4d { }, p0/z, [x0]
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llvm/test/MC/AArch64/SVE/ld4h-diagnostics.s

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ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, w0, uxtw] ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
ld4h {z2.h, z3.h, z4.h, z5.h}, p8/z, [x15, #10, MUL VL] ld4h {z2.h, z3.h, z4.h, z5.h}, p8/z, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld4h {z2.h, z3.h, z4.h, z5.h}, p8/z, [x15, #10, MUL VL] // CHECK-NEXT: ld4h {z2.h, z3.h, z4.h, z5.h}, p8/z, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld4h { }, p0/z, [x0] ld4h { }, p0/z, [x0]
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llvm/test/MC/AArch64/SVE/ld4w-diagnostics.s

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ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, w0, uxtw] ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
// CHECK-NEXT: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, w0, uxtw] // CHECK-NEXT: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
ld4w {z2.s, z3.s, z4.s, z5.s}, p8/z, [x15, #10, MUL VL] ld4w {z2.s, z3.s, z4.s, z5.s}, p8/z, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld4w {z2.s, z3.s, z4.s, z5.s}, p8/z, [x15, #10, MUL VL] // CHECK-NEXT: ld4w {z2.s, z3.s, z4.s, z5.s}, p8/z, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ld4w { }, p0/z, [x0] ld4w { }, p0/z, [x0]
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llvm/test/MC/AArch64/SVE/ldff1b-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldff1b z27.b, p8/z, [x0] ldff1b z27.b, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1b z27.b, p8/z, [x0] // CHECK-NEXT: ldff1b z27.b, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1b z9.h, p8/z, [x0] ldff1b z9.h, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1b z9.h, p8/z, [x0] // CHECK-NEXT: ldff1b z9.h, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1b z12.s, p8/z, [x0] ldff1b z12.s, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1b z12.s, p8/z, [x0] // CHECK-NEXT: ldff1b z12.s, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1b z4.d, p8/z, [x0] ldff1b z4.d, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1b z4.d, p8/z, [x0] // CHECK-NEXT: ldff1b z4.d, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
ldff1b z0.b, p0/z, [x0, sp] ldff1b z0.b, p0/z, [x0, sp]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
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llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldff1d z4.s, p7/z, [x0] // CHECK-NEXT: ldff1d z4.s, p7/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldff1d z4.d, p8/z, [x0] ldff1d z4.d, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1d z4.d, p8/z, [x0] // CHECK-NEXT: ldff1d z4.d, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
ldff1d z0.d, p0/z, [x0, sp] ldff1d z0.d, p0/z, [x0, sp]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
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llvm/test/MC/AArch64/SVE/ldff1h-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid operand (.b) // Invalid operand (.b)
ldff1h z9.b, p7/z, [x0] ldff1h z9.b, p7/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldff1h z9.b, p7/z, [x0] // CHECK-NEXT: ldff1h z9.b, p7/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldff1h z9.h, p8/z, [x0] ldff1h z9.h, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1h z9.h, p8/z, [x0] // CHECK-NEXT: ldff1h z9.h, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1h z12.s, p8/z, [x0] ldff1h z12.s, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1h z12.s, p8/z, [x0] // CHECK-NEXT: ldff1h z12.s, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1h z4.d, p8/z, [x0] ldff1h z4.d, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1h z4.d, p8/z, [x0] // CHECK-NEXT: ldff1h z4.d, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
ldff1h z0.h, p0/z, [x0, sp] ldff1h z0.h, p0/z, [x0, sp]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
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llvm/test/MC/AArch64/SVE/ldff1sb-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid operand (.b) // Invalid operand (.b)
ldff1sb z27.b, p7/z, [x0] ldff1sb z27.b, p7/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldff1sb z27.b, p7/z, [x0] // CHECK-NEXT: ldff1sb z27.b, p7/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldff1sb z9.h, p8/z, [x0] ldff1sb z9.h, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1sb z9.h, p8/z, [x0] // CHECK-NEXT: ldff1sb z9.h, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1sb z12.s, p8/z, [x0] ldff1sb z12.s, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1sb z12.s, p8/z, [x0] // CHECK-NEXT: ldff1sb z12.s, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1sb z4.d, p8/z, [x0] ldff1sb z4.d, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1sb z4.d, p8/z, [x0] // CHECK-NEXT: ldff1sb z4.d, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
ldff1sb z0.h, p0/z, [x0, sp] ldff1sb z0.h, p0/z, [x0, sp]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
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llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid operand (.h) // Invalid operand (.h)
ldff1sh z9.h, p7/z, [x0] ldff1sh z9.h, p7/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldff1sh z9.h, p7/z, [x0] // CHECK-NEXT: ldff1sh z9.h, p7/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldff1sh z12.s, p8/z, [x0] ldff1sh z12.s, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1sh z12.s, p8/z, [x0] // CHECK-NEXT: ldff1sh z12.s, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1sh z4.d, p8/z, [x0] ldff1sh z4.d, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1sh z4.d, p8/z, [x0] // CHECK-NEXT: ldff1sh z4.d, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
ldff1sh z0.s, p0/z, [x0, sp] ldff1sh z0.s, p0/z, [x0, sp]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
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llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid operand (.s) // Invalid operand (.s)
ldff1sw z12.s, p7/z, [x0] ldff1sw z12.s, p7/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldff1sw z12.s, p7/z, [x0] // CHECK-NEXT: ldff1sw z12.s, p7/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldff1sw z4.d, p8/z, [x0] ldff1sw z4.d, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1sw z4.d, p8/z, [x0] // CHECK-NEXT: ldff1sw z4.d, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
ldff1sw z0.d, p0/z, [x0, sp] ldff1sw z0.d, p0/z, [x0, sp]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
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llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s

Show All 11 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ldff1w z4.h, p7/z, [x0] // CHECK-NEXT: ldff1w z4.h, p7/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldff1w z12.s, p8/z, [x0] ldff1w z12.s, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1w z12.s, p8/z, [x0] // CHECK-NEXT: ldff1w z12.s, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1w z4.d, p8/z, [x0] ldff1w z4.d, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldff1w z4.d, p8/z, [x0] // CHECK-NEXT: ldff1w z4.d, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes // Invalid scalar + scalar addressing modes
ldff1w z0.s, p0/z, [x0, sp] ldff1w z0.s, p0/z, [x0, sp]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
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llvm/test/MC/AArch64/SVE/ldnf1b-diagnostics.s

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
// CHECK-NEXT: ldnf1b z27.d, p1/z, [x26, #8, MUL VL] // CHECK-NEXT: ldnf1b z27.d, p1/z, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnf1b z27.b, p8/z, [x29, #1, MUL VL] ldnf1b z27.b, p8/z, [x29, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1b z27.b, p8/z, [x29, #1, MUL VL] // CHECK-NEXT: ldnf1b z27.b, p8/z, [x29, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1b z9.h, p8/z, [x25, #1, MUL VL] ldnf1b z9.h, p8/z, [x25, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1b z9.h, p8/z, [x25, #1, MUL VL] // CHECK-NEXT: ldnf1b z9.h, p8/z, [x25, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1b z12.s, p8/z, [x13, #1, MUL VL] ldnf1b z12.s, p8/z, [x13, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1b z12.s, p8/z, [x13, #1, MUL VL] // CHECK-NEXT: ldnf1b z12.s, p8/z, [x13, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1b z4.d, p8/z, [x11, #1, MUL VL] ldnf1b z4.d, p8/z, [x11, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1b z4.d, p8/z, [x11, #1, MUL VL] // CHECK-NEXT: ldnf1b z4.d, p8/z, [x11, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnf1b { }, p0/z, [x1, #1, MUL VL] ldnf1b { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ldnf1d-diagnostics.s

Show All 12 Lines
// CHECK-NEXT: ldnf1d z27.d, p1/z, [x26, #8, MUL VL] // CHECK-NEXT: ldnf1d z27.d, p1/z, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnf1d z4.d, p8/z, [x11, #1, MUL VL] ldnf1d z4.d, p8/z, [x11, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1d z4.d, p8/z, [x11, #1, MUL VL] // CHECK-NEXT: ldnf1d z4.d, p8/z, [x11, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnf1d { }, p0/z, [x1, #1, MUL VL] ldnf1d { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ldnf1h-diagnostics.s

Show All 32 Lines
// CHECK-NEXT: ldnf1h z27.d, p1/z, [x26, #8, MUL VL] // CHECK-NEXT: ldnf1h z27.d, p1/z, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnf1h z9.h, p8/z, [x25, #1, MUL VL] ldnf1h z9.h, p8/z, [x25, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1h z9.h, p8/z, [x25, #1, MUL VL] // CHECK-NEXT: ldnf1h z9.h, p8/z, [x25, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1h z12.s, p8/z, [x13, #1, MUL VL] ldnf1h z12.s, p8/z, [x13, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1h z12.s, p8/z, [x13, #1, MUL VL] // CHECK-NEXT: ldnf1h z12.s, p8/z, [x13, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1h z4.d, p8/z, [x11, #1, MUL VL] ldnf1h z4.d, p8/z, [x11, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1h z4.d, p8/z, [x11, #1, MUL VL] // CHECK-NEXT: ldnf1h z4.d, p8/z, [x11, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnf1h { }, p0/z, [x1, #1, MUL VL] ldnf1h { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
// CHECK-NEXT: ldnf1sb z27.d, p1/z, [x26, #8, MUL VL] // CHECK-NEXT: ldnf1sb z27.d, p1/z, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnf1sb z9.h, p8/z, [x25, #1, MUL VL] ldnf1sb z9.h, p8/z, [x25, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1sb z9.h, p8/z, [x25, #1, MUL VL] // CHECK-NEXT: ldnf1sb z9.h, p8/z, [x25, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1sb z12.s, p8/z, [x13, #1, MUL VL] ldnf1sb z12.s, p8/z, [x13, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1sb z12.s, p8/z, [x13, #1, MUL VL] // CHECK-NEXT: ldnf1sb z12.s, p8/z, [x13, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1sb z4.d, p8/z, [x11, #1, MUL VL] ldnf1sb z4.d, p8/z, [x11, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1sb z4.d, p8/z, [x11, #1, MUL VL] // CHECK-NEXT: ldnf1sb z4.d, p8/z, [x11, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnf1sb { }, p0/z, [x1, #1, MUL VL] ldnf1sb { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s

Show All 36 Lines
// CHECK-NEXT: ldnf1sh z27.d, p1/z, [x26, #8, MUL VL] // CHECK-NEXT: ldnf1sh z27.d, p1/z, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnf1sh z12.s, p8/z, [x13, #1, MUL VL] ldnf1sh z12.s, p8/z, [x13, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1sh z12.s, p8/z, [x13, #1, MUL VL] // CHECK-NEXT: ldnf1sh z12.s, p8/z, [x13, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1sh z4.d, p8/z, [x11, #1, MUL VL] ldnf1sh z4.d, p8/z, [x11, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1sh z4.d, p8/z, [x11, #1, MUL VL] // CHECK-NEXT: ldnf1sh z4.d, p8/z, [x11, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnf1sh { }, p0/z, [x1, #1, MUL VL] ldnf1sh { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s

Show All 26 Lines
// CHECK-NEXT: ldnf1sw z27.d, p1/z, [x26, #8, MUL VL] // CHECK-NEXT: ldnf1sw z27.d, p1/z, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnf1sw z4.d, p8/z, [x11, #1, MUL VL] ldnf1sw z4.d, p8/z, [x11, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1sw z4.d, p8/z, [x11, #1, MUL VL] // CHECK-NEXT: ldnf1sw z4.d, p8/z, [x11, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnf1sw { }, p0/z, [x1, #1, MUL VL] ldnf1sw { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ldnf1w-diagnostics.s

Show All 22 Lines
// CHECK-NEXT: ldnf1w z27.d, p1/z, [x26, #8, MUL VL] // CHECK-NEXT: ldnf1w z27.d, p1/z, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnf1w z12.s, p8/z, [x13, #1, MUL VL] ldnf1w z12.s, p8/z, [x13, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1w z12.s, p8/z, [x13, #1, MUL VL] // CHECK-NEXT: ldnf1w z12.s, p8/z, [x13, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldnf1w z4.d, p8/z, [x11, #1, MUL VL] ldnf1w z4.d, p8/z, [x11, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnf1w z4.d, p8/z, [x11, #1, MUL VL] // CHECK-NEXT: ldnf1w z4.d, p8/z, [x11, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnf1w { }, p0/z, [x1, #1, MUL VL] ldnf1w { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ldnt1b-diagnostics.s

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// CHECK-NEXT: ldnt1b z0.d, p0/z, [x0] // CHECK-NEXT: ldnt1b z0.d, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnt1b z27.b, p8/z, [x0] ldnt1b z27.b, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnt1b z27.b, p8/z, [x0] // CHECK-NEXT: ldnt1b z27.b, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnt1b { }, p0/z, [x1, #1, MUL VL] ldnt1b { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ldnt1d-diagnostics.s

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// CHECK-NEXT: ldnt1d z0.s, p0/z, [x0] // CHECK-NEXT: ldnt1d z0.s, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnt1d z27.d, p8/z, [x0] ldnt1d z27.d, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnt1d z27.d, p8/z, [x0] // CHECK-NEXT: ldnt1d z27.d, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnt1d { }, p0/z, [x1, #1, MUL VL] ldnt1d { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ldnt1h-diagnostics.s

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// CHECK-NEXT: ldnt1h z0.d, p0/z, [x0] // CHECK-NEXT: ldnt1h z0.d, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnt1h z27.h, p8/z, [x0] ldnt1h z27.h, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnt1h z27.h, p8/z, [x0] // CHECK-NEXT: ldnt1h z27.h, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnt1h { }, p0/z, [x1, #1, MUL VL] ldnt1h { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/ldnt1w-diagnostics.s

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// CHECK-NEXT: ldnt1w z0.d, p0/z, [x0] // CHECK-NEXT: ldnt1w z0.d, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnt1w z27.s, p8/z, [x0] ldnt1w z27.s, p8/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnt1w z27.s, p8/z, [x0] // CHECK-NEXT: ldnt1w z27.s, p8/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnt1w { }, p0/z, [x1, #1, MUL VL] ldnt1w { }, p0/z, [x1, #1, MUL VL]
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llvm/test/MC/AArch64/SVE/lsl-diagnostics.s

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.h // CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
lsl z0.b, p8/m, z0.b, z1.b lsl z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: lsl z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: lsl z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d movprfx z31.d, p0/z, z6.d
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llvm/test/MC/AArch64/SVE/lslr-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
lslr z0.b, p8/m, z0.b, z0.b lslr z0.b, p8/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: lslr z0.b, p8/m, z0.b, z0.b // CHECK-NEXT: lslr z0.b, p8/m, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
lslr z0.b, p0/m, z0.b, z0.d lslr z0.b, p0/m, z0.b, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: lslr z0.b, p0/m, z0.b, z0.d // CHECK-NEXT: lslr z0.b, p0/m, z0.b, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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llvm/test/MC/AArch64/SVE/lsr-diagnostics.s

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
// CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.h // CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
lsr z0.b, p8/m, z0.b, z1.b lsr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: lsr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: lsr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d movprfx z31.d, p0/z, z6.d
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llvm/test/MC/AArch64/SVE/lsrr-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
lsrr z0.b, p8/m, z0.b, z0.b lsrr z0.b, p8/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: lsrr z0.b, p8/m, z0.b, z0.b // CHECK-NEXT: lsrr z0.b, p8/m, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
lsrr z0.b, p0/m, z0.b, z0.d lsrr z0.b, p0/m, z0.b, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: lsrr z0.b, p0/m, z0.b, z0.d // CHECK-NEXT: lsrr z0.b, p0/m, z0.b, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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llvm/test/MC/AArch64/SVE/mad-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
mad z0.h, p8/m, z1.h, z2.h mad z0.h, p8/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: mad z0.h, p8/m, z1.h, z2.h // CHECK-NEXT: mad z0.h, p8/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
mad z0.s, p7/m, z1.h, z2.h mad z0.s, p7/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: mad z0.s, p7/m, z1.h, z2.h // CHECK-NEXT: mad z0.s, p7/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/mla-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
mla z0.h, p8/m, z1.h, z2.h mla z0.h, p8/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: mla z0.h, p8/m, z1.h, z2.h // CHECK-NEXT: mla z0.h, p8/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
mla z0.s, p7/m, z1.h, z2.h mla z0.s, p7/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: mla z0.s, p7/m, z1.h, z2.h // CHECK-NEXT: mla z0.s, p7/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/mls-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
mls z0.h, p8/m, z1.h, z2.h mls z0.h, p8/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: mls z0.h, p8/m, z1.h, z2.h // CHECK-NEXT: mls z0.h, p8/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
mls z0.s, p7/m, z1.h, z2.h mls z0.s, p7/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: mls z0.s, p7/m, z1.h, z2.h // CHECK-NEXT: mls z0.s, p7/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/msb-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
msb z0.h, p8/m, z1.h, z2.h msb z0.h, p8/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: msb z0.h, p8/m, z1.h, z2.h // CHECK-NEXT: msb z0.h, p8/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
msb z0.s, p7/m, z1.h, z2.h msb z0.s, p7/m, z1.h, z2.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: msb z0.s, p7/m, z1.h, z2.h // CHECK-NEXT: msb z0.s, p7/m, z1.h, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/mul-diagnostics.s

Show All 27 Lines
// CHECK-NEXT: mul z0.b, p7/m, z1.b, z2.b // CHECK-NEXT: mul z0.b, p7/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
mul z0.b, p8/m, z0.b, z1.b mul z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: mul z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: mul z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d movprfx z31.d, p0/z, z6.d
mul z31.d, z31.d, #127 mul z31.d, z31.d, #127
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: mul z31.d, z31.d, #127 // CHECK-NEXT: mul z31.d, z31.d, #127
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/neg-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Element size specifiers should match. // Element size specifiers should match.
neg z0.h, p0/m, z0.b neg z0.h, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: neg z0.h, p0/m, z0.b // CHECK-NEXT: neg z0.h, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Missing predicate suffix // Missing predicate suffix
neg z29.d, p7, z29.d neg z29.d, p7, z29.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: neg z29.d, p7, z29.d // CHECK-NEXT: neg z29.d, p7, z29.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
neg z0.b, p8/m, z0.b neg z0.b, p8/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: neg z0.b, p8/m, z0.b // CHECK-NEXT: neg z0.b, p8/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
neg z0.h, p8/m, z0.h neg z0.h, p8/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: neg z0.h, p8/m, z0.h // CHECK-NEXT: neg z0.h, p8/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
neg z0.s, p8/m, z0.s neg z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: neg z0.s, p8/m, z0.s // CHECK-NEXT: neg z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
neg z0.d, p8/m, z0.d neg z0.d, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: neg z0.d, p8/m, z0.d // CHECK-NEXT: neg z0.d, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/not-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
not z31.b, p8/m, z31.b not z31.b, p8/m, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: not z31.b, p8/m, z31.b // CHECK-NEXT: not z31.b, p8/m, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
not z31.b, p7/m, z31.h not z31.b, p7/m, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: not z31.b, p7/m, z31.h // CHECK-NEXT: not z31.b, p7/m, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/orr-diagnostics.s

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
// CHECK-NEXT: orr z21.d, z5.d, z26.b // CHECK-NEXT: orr z21.d, z5.d, z26.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate out of restricted predicate range // Predicate out of restricted predicate range
orr z0.d, p8/z, z0.d, z1.d orr z0.d, p8/z, z0.d, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: orr z0.d, p8/z, z0.d, z1.d // CHECK-NEXT: orr z0.d, p8/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate register must have .b suffix // Predicate register must have .b suffix
orr p0.h, p0/z, p0.h, p1.h orr p0.h, p0/z, p0.h, p1.h
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llvm/test/MC/AArch64/SVE/orv-diagnostics.s

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// CHECK-NEXT: orv v0.2d, p7, z31.d // CHECK-NEXT: orv v0.2d, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
orv h0, p8, z31.h orv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: orv h0, p8, z31.h // CHECK-NEXT: orv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d movprfx z31.d, p7/z, z6.d
orv d0, p7, z31.d orv d0, p7, z31.d
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llvm/test/MC/AArch64/SVE/prfb-diagnostics.s

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// CHECK-NEXT: prfb #0, p0, [z0.d, #32] // CHECK-NEXT: prfb #0, p0, [z0.d, #32]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// invalid predicate // invalid predicate
prfb #0, p8, [x0] prfb #0, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: prfb #0, p8, [x0] // CHECK-NEXT: prfb #0, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d movprfx z0.d, p0/z, z7.d
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llvm/test/MC/AArch64/SVE/prfd-diagnostics.s

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// CHECK-NEXT: prfd #0, p0, [z0.d, #3] // CHECK-NEXT: prfd #0, p0, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// invalid predicate // invalid predicate
prfd #0, p8, [x0] prfd #0, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: prfd #0, p8, [x0] // CHECK-NEXT: prfd #0, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d movprfx z0.d, p0/z, z7.d
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llvm/test/MC/AArch64/SVE/prfh-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
// CHECK-NEXT: prfh #0, p0, [z0.d, #3] // CHECK-NEXT: prfh #0, p0, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// invalid predicate // invalid predicate
prfh #0, p8, [x0] prfh #0, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: prfh #0, p8, [x0] // CHECK-NEXT: prfh #0, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d movprfx z0.d, p0/z, z7.d
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llvm/test/MC/AArch64/SVE/prfw-diagnostics.s

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// CHECK-NEXT: prfw #0, p0, [z0.d, #3] // CHECK-NEXT: prfw #0, p0, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// invalid predicate // invalid predicate
prfw #0, p8, [x0] prfw #0, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: prfw #0, p8, [x0] // CHECK-NEXT: prfw #0, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z8.d, p3/z, z15.d movprfx z8.d, p3/z, z15.d
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llvm/test/MC/AArch64/SVE/rbit-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
rbit z0.d, p8/m, z0.d rbit z0.d, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: rbit z0.d, p8/m, z0.d // CHECK-NEXT: rbit z0.d, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/revb-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
revb z0.d, p8/m, z0.d revb z0.d, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: revb z0.d, p8/m, z0.d // CHECK-NEXT: revb z0.d, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element size // Invalid element size
revb z0.b, p0/m, z0.b revb z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: revb z0.b, p0/m, z0.b // CHECK-NEXT: revb z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/revh-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
revh z0.d, p8/m, z0.d revh z0.d, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: revh z0.d, p8/m, z0.d // CHECK-NEXT: revh z0.d, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element size // Invalid element size
revh z0.b, p0/m, z0.b revh z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: revh z0.b, p0/m, z0.b // CHECK-NEXT: revh z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
revh z0.h, p0/m, z0.h revh z0.h, p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: revh z0.h, p0/m, z0.h // CHECK-NEXT: revh z0.h, p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/revw-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
revw z0.d, p8/m, z0.d revw z0.d, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: revw z0.d, p8/m, z0.d // CHECK-NEXT: revw z0.d, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element size // Invalid element size
revw z0.b, p0/m, z0.b revw z0.b, p0/m, z0.b
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llvm/test/MC/AArch64/SVE/sabd-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
sabd z0.b, p8/m, z0.b, z0.b sabd z0.b, p8/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sabd z0.b, p8/m, z0.b, z0.b // CHECK-NEXT: sabd z0.b, p8/m, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/saddv-diagnostics.s

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// CHECK-NEXT: saddv d0, p7, z31.d // CHECK-NEXT: saddv d0, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
saddv d0, p8, z31.b saddv d0, p8, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: saddv d0, p8, z31.b // CHECK-NEXT: saddv d0, p8, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.s, p7/z, z6.s movprfx z31.s, p7/z, z6.s
saddv d0, p7, z31.s saddv d0, p7, z31.s
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llvm/test/MC/AArch64/SVE/scvtf-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
scvtf z0.s, p0/m, z0.h scvtf z0.s, p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: scvtf z0.s, p0/m, z0.h // CHECK-NEXT: scvtf z0.s, p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
scvtf z0.d, p0/m, z0.h scvtf z0.d, p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: scvtf z0.d, p0/m, z0.h // CHECK-NEXT: scvtf z0.d, p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
scvtf z0.h, p8/m, z0.h scvtf z0.h, p8/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: scvtf z0.h, p8/m, z0.h // CHECK-NEXT: scvtf z0.h, p8/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/sdiv-diagnostics.s

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// CHECK-NEXT: sdiv z0.s, p7/m, z1.s, z2.s // CHECK-NEXT: sdiv z0.s, p7/m, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
sdiv z0.s, p8/m, z0.s, z1.s sdiv z0.s, p8/m, z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sdiv z0.s, p8/m, z0.s, z1.s // CHECK-NEXT: sdiv z0.s, p8/m, z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/sdivr-diagnostics.s

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// CHECK-NEXT: sdivr z0.s, p7/m, z1.s, z2.s // CHECK-NEXT: sdivr z0.s, p7/m, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
sdivr z0.s, p8/m, z0.s, z1.s sdivr z0.s, p8/m, z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sdivr z0.s, p8/m, z0.s, z1.s // CHECK-NEXT: sdivr z0.s, p8/m, z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/smax-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
smax z0.b, z0.b, #-129 smax z0.b, z0.b, #-129
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127].
// CHECK-NEXT: smax z0.b, z0.b, #-129 // CHECK-NEXT: smax z0.b, z0.b, #-129
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smax z31.b, z31.b, #128 smax z31.b, z31.b, #128
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127].
// CHECK-NEXT: smax z31.b, z31.b, #128 // CHECK-NEXT: smax z31.b, z31.b, #128
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smax z0.b, p8/m, z0.b, z0.b smax z0.b, p8/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: smax z0.b, p8/m, z0.b, z0.b // CHECK-NEXT: smax z0.b, p8/m, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d movprfx z31.d, p0/z, z6.d
smax z31.d, z31.d, #127 smax z31.d, z31.d, #127
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: smax z31.d, z31.d, #127 // CHECK-NEXT: smax z31.d, z31.d, #127
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/smaxv-diagnostics.s

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// CHECK-NEXT: smaxv v0.2d, p7, z31.d // CHECK-NEXT: smaxv v0.2d, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
smaxv h0, p8, z31.h smaxv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: smaxv h0, p8, z31.h // CHECK-NEXT: smaxv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d movprfx z31.d, p7/z, z6.d
smaxv d0, p7, z31.d smaxv d0, p7, z31.d
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llvm/test/MC/AArch64/SVE/smin-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
smin z0.b, z0.b, #-129 smin z0.b, z0.b, #-129
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127].
// CHECK-NEXT: smin z0.b, z0.b, #-129 // CHECK-NEXT: smin z0.b, z0.b, #-129
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smin z31.b, z31.b, #128 smin z31.b, z31.b, #128
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127].
// CHECK-NEXT: smin z31.b, z31.b, #128 // CHECK-NEXT: smin z31.b, z31.b, #128
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smin z0.b, p8/m, z0.b, z0.b smin z0.b, p8/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: smin z0.b, p8/m, z0.b, z0.b // CHECK-NEXT: smin z0.b, p8/m, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p0/z, z6.d movprfx z31.d, p0/z, z6.d
smin z31.d, z31.d, #127 smin z31.d, z31.d, #127
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: smin z31.d, z31.d, #127 // CHECK-NEXT: smin z31.d, z31.d, #127
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/sminv-diagnostics.s

Show All 23 Lines
// CHECK-NEXT: sminv v0.2d, p7, z31.d // CHECK-NEXT: sminv v0.2d, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
sminv h0, p8, z31.h sminv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sminv h0, p8, z31.h // CHECK-NEXT: sminv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d movprfx z31.d, p7/z, z6.d
sminv d0, p7, z31.d sminv d0, p7, z31.d
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llvm/test/MC/AArch64/SVE/smulh-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Tied operands must match // Tied operands must match
smulh z0.b, p7/m, z1.b, z2.b smulh z0.b, p7/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: smulh z0.b, p7/m, z1.b, z2.b // CHECK-NEXT: smulh z0.b, p7/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
smulh z0.b, p8/m, z0.b, z1.b smulh z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: smulh z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: smulh z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/splice-diagnostics.s

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// CHECK-NEXT: splice z0.b, p0, z0.b, z2.h // CHECK-NEXT: splice z0.b, p0, z0.b, z2.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
splice z0.b, p8, z0.b, z1.b splice z0.b, p8, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: splice z0.b, p8, z0.b, z1.b // CHECK-NEXT: splice z0.b, p8, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z4.d, p7/z, z6.d movprfx z4.d, p7/z, z6.d
splice z4.d, p7, z4.d, z31.d splice z4.d, p7, z4.d, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: splice z4.d, p7, z4.d, z31.d // CHECK-NEXT: splice z4.d, p7, z4.d, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/st1b-diagnostics.s

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
// CHECK-NEXT: st1b z27.d, p1, [x12, #8, MUL VL] // CHECK-NEXT: st1b z27.d, p1, [x12, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate has range [0, 7]. // Restricted predicate has range [0, 7].
st1b z12.b, p8, [x27, #6, MUL VL] st1b z12.b, p8, [x27, #6, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st1b z12.b, p8, [x27, #6, MUL VL] // CHECK-NEXT: st1b z12.b, p8, [x27, #6, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1b z23.h, p8, [x20, #1, MUL VL] st1b z23.h, p8, [x20, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st1b z23.h, p8, [x20, #1, MUL VL] // CHECK-NEXT: st1b z23.h, p8, [x20, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1b z6.s, p8, [x0, #8, MUL VL] st1b z6.s, p8, [x0, #8, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st1b z6.s, p8, [x0, #8, MUL VL] // CHECK-NEXT: st1b z6.s, p8, [x0, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1b z14.d, p8, [x6, #5, MUL VL] st1b z14.d, p8, [x6, #5, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st1b z14.d, p8, [x6, #5, MUL VL] // CHECK-NEXT: st1b z14.d, p8, [x6, #5, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list // Invalid vector list
st1b { }, p0, [x0] st1b { }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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llvm/test/MC/AArch64/SVE/st1d-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
// CHECK-NEXT: st1d z16.d, p4, [x2, #8, MUL VL] // CHECK-NEXT: st1d z16.d, p4, [x2, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate has range [0, 7]. // Restricted predicate has range [0, 7].
st1d z12.d, p8, [x4, #14, MUL VL] st1d z12.d, p8, [x4, #14, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st1d z12.d, p8, [x4, #14, MUL VL] // CHECK-NEXT: st1d z12.d, p8, [x4, #14, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list // Invalid vector list
st1d { }, p0, [x0] st1d { }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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llvm/test/MC/AArch64/SVE/st1h-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
// CHECK-NEXT: st1h z24.d, p3, [x16, #8, MUL VL] // CHECK-NEXT: st1h z24.d, p3, [x16, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate has range [0, 7]. // Restricted predicate has range [0, 7].
st1h z15.h, p8, [x0, #8, MUL VL] st1h z15.h, p8, [x0, #8, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st1h z15.h, p8, [x0, #8, MUL VL] // CHECK-NEXT: st1h z15.h, p8, [x0, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1h z17.s, p8, [x20, #2, MUL VL] st1h z17.s, p8, [x20, #2, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st1h z17.s, p8, [x20, #2, MUL VL] // CHECK-NEXT: st1h z17.s, p8, [x20, #2, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1h z15.d, p8, [x0, #8, MUL VL] st1h z15.d, p8, [x0, #8, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st1h z15.d, p8, [x0, #8, MUL VL] // CHECK-NEXT: st1h z15.d, p8, [x0, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list // Invalid vector list
st1h { }, p0, [x0] st1h { }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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llvm/test/MC/AArch64/SVE/st1w-diagnostics.s

Show All 24 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
// CHECK-NEXT: st1w z10.d, p5, [x26, #8, MUL VL] // CHECK-NEXT: st1w z10.d, p5, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate has range [0, 7]. // Restricted predicate has range [0, 7].
st1w z1.s, p8, [x3, #1, MUL VL] st1w z1.s, p8, [x3, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st1w z1.s, p8, [x3, #1, MUL VL] // CHECK-NEXT: st1w z1.s, p8, [x3, #1, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
st1w z12.d, p8, [x26, #3, MUL VL] st1w z12.d, p8, [x26, #3, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st1w z12.d, p8, [x26, #3, MUL VL] // CHECK-NEXT: st1w z12.d, p8, [x26, #3, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list // Invalid vector list
st1w { }, p0, [x0] st1w { }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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llvm/test/MC/AArch64/SVE/st2b-diagnostics.s

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
st2b { z0.b, z1.b }, p0, [x0, w0, uxtw] st2b { z0.b, z1.b }, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
// CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, w0, uxtw] // CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
st2b {z2.b, z3.b}, p8, [x15, #10, MUL VL] st2b {z2.b, z3.b}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st2b {z2.b, z3.b}, p8, [x15, #10, MUL VL] // CHECK-NEXT: st2b {z2.b, z3.b}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
st2b { }, p0, [x0] st2b { }, p0, [x0]
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llvm/test/MC/AArch64/SVE/st2d-diagnostics.s

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
st2d { z0.d, z1.d }, p0, [x0, w0, uxtw] st2d { z0.d, z1.d }, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
// CHECK-NEXT: st2d { z0.d, z1.d }, p0, [x0, w0, uxtw] // CHECK-NEXT: st2d { z0.d, z1.d }, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
st2d {z2.d, z3.d}, p8, [x15, #10, MUL VL] st2d {z2.d, z3.d}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st2d {z2.d, z3.d}, p8, [x15, #10, MUL VL] // CHECK-NEXT: st2d {z2.d, z3.d}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
st2d { }, p0, [x0] st2d { }, p0, [x0]
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llvm/test/MC/AArch64/SVE/st2h-diagnostics.s

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
st2h { z0.h, z1.h }, p0, [x0, w0, uxtw] st2h { z0.h, z1.h }, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, w0, uxtw] // CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
st2h {z2.h, z3.h}, p8, [x15, #10, MUL VL] st2h {z2.h, z3.h}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st2h {z2.h, z3.h}, p8, [x15, #10, MUL VL] // CHECK-NEXT: st2h {z2.h, z3.h}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
st2h { }, p0, [x0] st2h { }, p0, [x0]
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llvm/test/MC/AArch64/SVE/st2w-diagnostics.s

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
st2w { z0.s, z1.s }, p0, [x0, w0, uxtw] st2w { z0.s, z1.s }, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
// CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0, w0, uxtw] // CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
st2w {z2.s, z3.s}, p8, [x15, #10, MUL VL] st2w {z2.s, z3.s}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st2w {z2.s, z3.s}, p8, [x15, #10, MUL VL] // CHECK-NEXT: st2w {z2.s, z3.s}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
st2w { }, p0, [x0] st2w { }, p0, [x0]
Show All 39 Lines

llvm/test/MC/AArch64/SVE/st3b-diagnostics.s

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
st3b { z0.b, z1.b, z2.b }, p0, [x0, w0, uxtw] st3b { z0.b, z1.b, z2.b }, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
// CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, w0, uxtw] // CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
st3b {z2.b, z3.b, z4.b}, p8, [x15, #10, MUL VL] st3b {z2.b, z3.b, z4.b}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st3b {z2.b, z3.b, z4.b}, p8, [x15, #10, MUL VL] // CHECK-NEXT: st3b {z2.b, z3.b, z4.b}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
st3b { }, p0, [x0] st3b { }, p0, [x0]
Show All 39 Lines

llvm/test/MC/AArch64/SVE/st3d-diagnostics.s

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
st3d { z0.d, z1.d, z2.d }, p0, [x0, w0, uxtw] st3d { z0.d, z1.d, z2.d }, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, w0, uxtw] // CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
st3d {z2.d, z3.d, z4.d}, p8, [x15, #10, MUL VL] st3d {z2.d, z3.d, z4.d}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st3d {z2.d, z3.d, z4.d}, p8, [x15, #10, MUL VL] // CHECK-NEXT: st3d {z2.d, z3.d, z4.d}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
st3d { }, p0, [x0] st3d { }, p0, [x0]
Show All 39 Lines

llvm/test/MC/AArch64/SVE/st3h-diagnostics.s

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
st3h { z0.h, z1.h, z2.h }, p0, [x0, w0, uxtw] st3h { z0.h, z1.h, z2.h }, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x0, w0, uxtw] // CHECK-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
st3h {z2.h, z3.h, z4.h}, p8, [x15, #10, MUL VL] st3h {z2.h, z3.h, z4.h}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st3h {z2.h, z3.h, z4.h}, p8, [x15, #10, MUL VL] // CHECK-NEXT: st3h {z2.h, z3.h, z4.h}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
st3h { }, p0, [x0] st3h { }, p0, [x0]
Show All 39 Lines

llvm/test/MC/AArch64/SVE/st3w-diagnostics.s

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
st3w { z0.s, z1.s, z2.s }, p0, [x0, w0, uxtw] st3w { z0.s, z1.s, z2.s }, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
// CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, w0, uxtw] // CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
st3w {z2.s, z3.s, z4.s}, p8, [x15, #10, MUL VL] st3w {z2.s, z3.s, z4.s}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st3w {z2.s, z3.s, z4.s}, p8, [x15, #10, MUL VL] // CHECK-NEXT: st3w {z2.s, z3.s, z4.s}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
st3w { }, p0, [x0] st3w { }, p0, [x0]
Show All 39 Lines

llvm/test/MC/AArch64/SVE/st4b-diagnostics.s

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0, uxtw] st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
// CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0, uxtw] // CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
st4b {z2.b, z3.b, z4.b, z5.b}, p8, [x15, #10, MUL VL] st4b {z2.b, z3.b, z4.b, z5.b}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st4b {z2.b, z3.b, z4.b, z5.b}, p8, [x15, #10, MUL VL] // CHECK-NEXT: st4b {z2.b, z3.b, z4.b, z5.b}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
st4b { }, p0, [x0] st4b { }, p0, [x0]
Show All 39 Lines

llvm/test/MC/AArch64/SVE/st4d-diagnostics.s

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, w0, uxtw] st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
// CHECK-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, w0, uxtw] // CHECK-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
st4d {z2.d, z3.d, z4.d, z5.d}, p8, [x15, #10, MUL VL] st4d {z2.d, z3.d, z4.d, z5.d}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st4d {z2.d, z3.d, z4.d, z5.d}, p8, [x15, #10, MUL VL] // CHECK-NEXT: st4d {z2.d, z3.d, z4.d, z5.d}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
st4d { }, p0, [x0] st4d { }, p0, [x0]
Show All 39 Lines

llvm/test/MC/AArch64/SVE/st4h-diagnostics.s

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0, uxtw] st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0, uxtw] // CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
st4h {z2.h, z3.h, z4.h, z5.h}, p8, [x15, #10, MUL VL] st4h {z2.h, z3.h, z4.h, z5.h}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st4h {z2.h, z3.h, z4.h, z5.h}, p8, [x15, #10, MUL VL] // CHECK-NEXT: st4h {z2.h, z3.h, z4.h, z5.h}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
st4h { }, p0, [x0] st4h { }, p0, [x0]
Show All 39 Lines

llvm/test/MC/AArch64/SVE/st4w-diagnostics.s

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0, uxtw] st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0, uxtw] // CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
st4w {z2.s, z3.s, z4.s, z5.s}, p8, [x15, #10, MUL VL] st4w {z2.s, z3.s, z4.s, z5.s}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st4w {z2.s, z3.s, z4.s, z5.s}, p8, [x15, #10, MUL VL] // CHECK-NEXT: st4w {z2.s, z3.s, z4.s, z5.s}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
st4w { }, p0, [x0] st4w { }, p0, [x0]
Show All 39 Lines

llvm/test/MC/AArch64/SVE/stnt1b-diagnostics.s

Show All 31 Lines
// CHECK-NEXT: stnt1b z0.d, p0, [x0] // CHECK-NEXT: stnt1b z0.d, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// invalid predicate // invalid predicate
stnt1b z27.b, p8, [x0] stnt1b z27.b, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: stnt1b z27.b, p8, [x0] // CHECK-NEXT: stnt1b z27.b, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1b z0.h, p0/z, [x0] stnt1b z0.h, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1b z0.h, p0/z, [x0] // CHECK-NEXT: stnt1b z0.h, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Show All 34 Lines

llvm/test/MC/AArch64/SVE/stnt1d-diagnostics.s

Show All 31 Lines
// CHECK-NEXT: stnt1d z0.s, p0, [x0] // CHECK-NEXT: stnt1d z0.s, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// invalid predicate // invalid predicate
stnt1d z27.d, p8, [x0] stnt1d z27.d, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: stnt1d z27.d, p8, [x0] // CHECK-NEXT: stnt1d z27.d, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1d z0.d, p0/z, [x0] stnt1d z0.d, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1d z0.d, p0/z, [x0] // CHECK-NEXT: stnt1d z0.d, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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llvm/test/MC/AArch64/SVE/stnt1h-diagnostics.s

Show All 31 Lines
// CHECK-NEXT: stnt1h z0.d, p0, [x0] // CHECK-NEXT: stnt1h z0.d, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// invalid predicate // invalid predicate
stnt1h z27.h, p8, [x0] stnt1h z27.h, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: stnt1h z27.h, p8, [x0] // CHECK-NEXT: stnt1h z27.h, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1h z0.h, p0/z, [x0] stnt1h z0.h, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1h z0.h, p0/z, [x0] // CHECK-NEXT: stnt1h z0.h, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Show All 34 Lines

llvm/test/MC/AArch64/SVE/stnt1w-diagnostics.s

Show All 31 Lines
// CHECK-NEXT: stnt1w z0.d, p0, [x0] // CHECK-NEXT: stnt1w z0.d, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// invalid predicate // invalid predicate
stnt1w z27.s, p8, [x0] stnt1w z27.s, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: stnt1w z27.s, p8, [x0] // CHECK-NEXT: stnt1w z27.s, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1w z0.s, p0/z, [x0] stnt1w z0.s, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1w z0.s, p0/z, [x0] // CHECK-NEXT: stnt1w z0.s, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Show All 34 Lines

llvm/test/MC/AArch64/SVE/sub-diagnostics.s

Show All 25 Lines
// Missing predicate suffix // Missing predicate suffix
sub z29.d, p7, z29.d, z8.d sub z29.d, p7, z29.d, z8.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sub z29.d, p7, z29.d, z8.d // CHECK-NEXT: sub z29.d, p7, z29.d, z8.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
sub z26.b, p8/m, z26.b, z27.b sub z26.b, p8/m, z26.b, z27.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sub z26.b, p8/m, z26.b, z27.b // CHECK-NEXT: sub z26.b, p8/m, z26.b, z27.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sub z14.h, p8/m, z14.h, z18.h sub z14.h, p8/m, z14.h, z18.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sub z14.h, p8/m, z14.h, z18.h // CHECK-NEXT: sub z14.h, p8/m, z14.h, z18.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sub z30.s, p8/m, z30.s, z23.s sub z30.s, p8/m, z30.s, z23.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sub z30.s, p8/m, z30.s, z23.s // CHECK-NEXT: sub z30.s, p8/m, z30.s, z23.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sub z29.d, p8/m, z29.d, z3.d sub z29.d, p8/m, z29.d, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sub z29.d, p8/m, z29.d, z3.d // CHECK-NEXT: sub z29.d, p8/m, z29.d, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Source and Destination Registers must match // Source and Destination Registers must match
sub z25.b, p4/m, z26.b, z2.b sub z25.b, p4/m, z26.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
▲ Show 20 Lines • Show All 108 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SVE/subr-diagnostics.s

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// Missing predicate suffix // Missing predicate suffix
subr z0.d, p7, z0.d, z0.d subr z0.d, p7, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: subr z0.d, p7, z0.d, z0.d // CHECK-NEXT: subr z0.d, p7, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
subr z26.b, p8/m, z26.b, z27.b subr z26.b, p8/m, z26.b, z27.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: subr z26.b, p8/m, z26.b, z27.b // CHECK-NEXT: subr z26.b, p8/m, z26.b, z27.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z14.h, p8/m, z14.h, z18.h subr z14.h, p8/m, z14.h, z18.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: subr z14.h, p8/m, z14.h, z18.h // CHECK-NEXT: subr z14.h, p8/m, z14.h, z18.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z30.s, p8/m, z30.s, z23.s subr z30.s, p8/m, z30.s, z23.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: subr z30.s, p8/m, z30.s, z23.s // CHECK-NEXT: subr z30.s, p8/m, z30.s, z23.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z29.d, p8/m, z29.d, z3.d subr z29.d, p8/m, z29.d, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: subr z29.d, p8/m, z29.d, z3.d // CHECK-NEXT: subr z29.d, p8/m, z29.d, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Source and Destination Registers must match // Source and Destination Registers must match
subr z25.b, p4/m, z26.b, z2.b subr z25.b, p4/m, z26.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
▲ Show 20 Lines • Show All 96 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SVE/sxtb-diagnostics.s

Show All 17 Lines
sxtb z0.b, p0/m, z0.b sxtb z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sxtb z0.b, p0/m, z0.b // CHECK-NEXT: sxtb z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
sxtb z0.h, p8/m, z0.h sxtb z0.h, p8/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sxtb z0.h, p8/m, z0.h // CHECK-NEXT: sxtb z0.h, p8/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sxtb z0.s, p8/m, z0.s sxtb z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sxtb z0.s, p8/m, z0.s // CHECK-NEXT: sxtb z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sxtb z0.d, p8/m, z0.d sxtb z0.d, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sxtb z0.d, p8/m, z0.d // CHECK-NEXT: sxtb z0.d, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/sxth-diagnostics.s

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sxth z0.h, p0/m, z0.h sxth z0.h, p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sxth z0.h, p0/m, z0.h // CHECK-NEXT: sxth z0.h, p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
sxth z0.s, p8/m, z0.s sxth z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sxth z0.s, p8/m, z0.s // CHECK-NEXT: sxth z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sxth z0.d, p8/m, z0.d sxth z0.d, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sxth z0.d, p8/m, z0.d // CHECK-NEXT: sxth z0.d, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/sxtw-diagnostics.s

Show All 27 Lines
sxtw z0.s, p0/m, z0.s sxtw z0.s, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sxtw z0.s, p0/m, z0.s // CHECK-NEXT: sxtw z0.s, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
sxtw z0.d, p8/m, z0.d sxtw z0.d, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sxtw z0.d, p8/m, z0.d // CHECK-NEXT: sxtw z0.d, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/uabd-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
uabd z0.b, p8/m, z0.b, z0.b uabd z0.b, p8/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uabd z0.b, p8/m, z0.b, z0.b // CHECK-NEXT: uabd z0.b, p8/m, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/uaddv-diagnostics.s

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// CHECK-NEXT: uaddv s0, p7, z31.s // CHECK-NEXT: uaddv s0, p7, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
uaddv d0, p8, z31.b uaddv d0, p8, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uaddv d0, p8, z31.b // CHECK-NEXT: uaddv d0, p8, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d movprfx z31.d, p7/z, z6.d
uaddv d0, p7, z31.d uaddv d0, p7, z31.d
Show All 9 Lines

llvm/test/MC/AArch64/SVE/ucvtf-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
ucvtf z0.s, p0/m, z0.h ucvtf z0.s, p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ucvtf z0.s, p0/m, z0.h // CHECK-NEXT: ucvtf z0.s, p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ucvtf z0.d, p0/m, z0.h ucvtf z0.d, p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ucvtf z0.d, p0/m, z0.h // CHECK-NEXT: ucvtf z0.d, p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
ucvtf z0.h, p8/m, z0.h ucvtf z0.h, p8/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ucvtf z0.h, p8/m, z0.h // CHECK-NEXT: ucvtf z0.h, p8/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/udiv-diagnostics.s

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// CHECK-NEXT: udiv z0.s, p7/m, z1.s, z2.s // CHECK-NEXT: udiv z0.s, p7/m, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
udiv z0.s, p8/m, z0.s, z1.s udiv z0.s, p8/m, z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: udiv z0.s, p8/m, z0.s, z1.s // CHECK-NEXT: udiv z0.s, p8/m, z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/udivr-diagnostics.s

Show All 22 Lines
// CHECK-NEXT: udivr z0.s, p7/m, z1.s, z2.s // CHECK-NEXT: udivr z0.s, p7/m, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
udivr z0.s, p8/m, z0.s, z1.s udivr z0.s, p8/m, z0.s, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: udivr z0.s, p8/m, z0.s, z1.s // CHECK-NEXT: udivr z0.s, p8/m, z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/umax-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
umax z0.b, z0.b, #-1 umax z0.b, z0.b, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
// CHECK-NEXT: umax z0.b, z0.b, #-1 // CHECK-NEXT: umax z0.b, z0.b, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umax z31.b, z31.b, #256 umax z31.b, z31.b, #256
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
// CHECK-NEXT: umax z31.b, z31.b, #256 // CHECK-NEXT: umax z31.b, z31.b, #256
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umax z0.b, p8/m, z0.b, z0.b umax z0.b, p8/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: umax z0.b, p8/m, z0.b, z0.b // CHECK-NEXT: umax z0.b, p8/m, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.b, p0/z, z6.b movprfx z31.b, p0/z, z6.b
umax z31.b, z31.b, #255 umax z31.b, z31.b, #255
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: umax z31.b, z31.b, #255 // CHECK-NEXT: umax z31.b, z31.b, #255
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/umaxv-diagnostics.s

Show All 23 Lines
// CHECK-NEXT: umaxv v0.2d, p7, z31.d // CHECK-NEXT: umaxv v0.2d, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
umaxv h0, p8, z31.h umaxv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: umaxv h0, p8, z31.h // CHECK-NEXT: umaxv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d movprfx z31.d, p7/z, z6.d
umaxv d0, p7, z31.d umaxv d0, p7, z31.d
Show All 9 Lines

llvm/test/MC/AArch64/SVE/umin-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
umin z0.b, z0.b, #-1 umin z0.b, z0.b, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
// CHECK-NEXT: umin z0.b, z0.b, #-1 // CHECK-NEXT: umin z0.b, z0.b, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umin z31.b, z31.b, #256 umin z31.b, z31.b, #256
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
// CHECK-NEXT: umin z31.b, z31.b, #256 // CHECK-NEXT: umin z31.b, z31.b, #256
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umin z0.b, p8/m, z0.b, z0.b umin z0.b, p8/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: umin z0.b, p8/m, z0.b, z0.b // CHECK-NEXT: umin z0.b, p8/m, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.b, p0/z, z6.b movprfx z31.b, p0/z, z6.b
umin z31.b, z31.b, #255 umin z31.b, z31.b, #255
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
// CHECK-NEXT: umin z31.b, z31.b, #255 // CHECK-NEXT: umin z31.b, z31.b, #255
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/uminv-diagnostics.s

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// CHECK-NEXT: uminv v0.2d, p7, z31.d // CHECK-NEXT: uminv v0.2d, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
uminv h0, p8, z31.h uminv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uminv h0, p8, z31.h // CHECK-NEXT: uminv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31.d, p7/z, z6.d movprfx z31.d, p7/z, z6.d
uminv d0, p7, z31.d uminv d0, p7, z31.d
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llvm/test/MC/AArch64/SVE/umulh-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Tied operands must match // Tied operands must match
umulh z0.b, p7/m, z1.b, z2.b umulh z0.b, p7/m, z1.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: umulh z0.b, p7/m, z1.b, z2.b // CHECK-NEXT: umulh z0.b, p7/m, z1.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
umulh z0.b, p8/m, z0.b, z1.b umulh z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: umulh z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: umulh z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/addp-diagnostics.s

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// Invalid predicate // Invalid predicate
addp z0.b, p0/z, z0.b, z1.b addp z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: addp z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: addp z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
addp z0.b, p8/m, z0.b, z1.b addp z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: addp z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: addp z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/faddp-diagnostics.s

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// CHECK-NEXT: faddp z0.h, p0/z, z0.h, z1.h // CHECK-NEXT: faddp z0.h, p0/z, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
faddp z0.h, p8/m, z0.h, z1.h faddp z0.h, p8/m, z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: faddp z0.h, p8/m, z0.h, z1.h // CHECK-NEXT: faddp z0.h, p8/m, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/fcvtlt-diagnostics.s

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
// CHECK-NEXT: fcvtlt z0.s, p0/z, z0.h // CHECK-NEXT: fcvtlt z0.s, p0/z, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
fcvtlt z0.s, p8/m, z0.h fcvtlt z0.s, p8/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fcvtlt z0.s, p8/m, z0.h // CHECK-NEXT: fcvtlt z0.s, p8/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/m, z7.s movprfx z0.s, p0/m, z7.s
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llvm/test/MC/AArch64/SVE2/fcvtnt-diagnostics.s

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// CHECK-NEXT: fcvtnt z0.h, p0/z, z0.s // CHECK-NEXT: fcvtnt z0.h, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
fcvtnt z0.h, p8/m, z0.s fcvtnt z0.h, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fcvtnt z0.h, p8/m, z0.s // CHECK-NEXT: fcvtnt z0.h, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/m, z7.s movprfx z0.s, p0/m, z7.s
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llvm/test/MC/AArch64/SVE2/fcvtx-diagnostics.s

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fcvtx z0.s, p0/z, z0.d fcvtx z0.s, p0/z, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvtx z0.s, p0/z, z0.d // CHECK-NEXT: fcvtx z0.s, p0/z, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7]. // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
fcvtx z0.s, p8/m, z0.d fcvtx z0.s, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fcvtx z0.s, p8/m, z0.d // CHECK-NEXT: fcvtx z0.s, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/fcvtxnt-diagnostics.s

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// CHECK-NEXT: fcvtxnt z0.s, p0/z, z0.d // CHECK-NEXT: fcvtxnt z0.s, p0/z, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
fcvtxnt z0.s, p8/m, z0.d fcvtxnt z0.s, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fcvtxnt z0.s, p8/m, z0.d // CHECK-NEXT: fcvtxnt z0.s, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/m, z7.s movprfx z0.s, p0/m, z7.s
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llvm/test/MC/AArch64/SVE2/flogb-diagnostics.s

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// CHECK-NEXT: flogb z0.s, p0/z, z0.s // CHECK-NEXT: flogb z0.s, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
flogb z0.s, p8/m, z0.s flogb z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: flogb z0.s, p8/m, z0.s // CHECK-NEXT: flogb z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/fmaxnmp-diagnostics.s

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// CHECK-NEXT: fmaxnmp z0.h, p0/z, z0.h, z1.h // CHECK-NEXT: fmaxnmp z0.h, p0/z, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
fmaxnmp z0.h, p8/m, z0.h, z1.h fmaxnmp z0.h, p8/m, z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmaxnmp z0.h, p8/m, z0.h, z1.h // CHECK-NEXT: fmaxnmp z0.h, p8/m, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/fmaxp-diagnostics.s

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// CHECK-NEXT: fmaxp z0.h, p0/z, z0.h, z1.h // CHECK-NEXT: fmaxp z0.h, p0/z, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
fmaxp z0.h, p8/m, z0.h, z1.h fmaxp z0.h, p8/m, z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmaxp z0.h, p8/m, z0.h, z1.h // CHECK-NEXT: fmaxp z0.h, p8/m, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/fminnmp-diagnostics.s

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// CHECK-NEXT: fminnmp z0.h, p0/z, z0.h, z1.h // CHECK-NEXT: fminnmp z0.h, p0/z, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
fminnmp z0.h, p8/m, z0.h, z1.h fminnmp z0.h, p8/m, z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fminnmp z0.h, p8/m, z0.h, z1.h // CHECK-NEXT: fminnmp z0.h, p8/m, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/fminp-diagnostics.s

Show All 39 Lines
// CHECK-NEXT: fminp z0.h, p0/z, z0.h, z1.h // CHECK-NEXT: fminp z0.h, p0/z, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
fminp z0.h, p8/m, z0.h, z1.h fminp z0.h, p8/m, z0.h, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fminp z0.h, p8/m, z0.h, z1.h // CHECK-NEXT: fminp z0.h, p8/m, z0.h, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/histcnt-diagnostics.s

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// CHECK-NEXT: histcnt z0.s, p0/m, z1.s, z2.s // CHECK-NEXT: histcnt z0.s, p0/m, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
histcnt z0.s, p8/z, z1.s, z2.s histcnt z0.s, p8/z, z1.s, z2.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: histcnt z0.s, p8/z, z1.s, z2.s // CHECK-NEXT: histcnt z0.s, p8/z, z1.s, z2.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z0.s, p0/z, z7.s movprfx z0.s, p0/z, z7.s
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llvm/test/MC/AArch64/SVE2/ldnt1b-diagnostics.s

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// CHECK-NEXT: ldnt1b { z0.d }, p0/m, [z0.d] // CHECK-NEXT: ldnt1b { z0.d }, p0/m, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnt1b { z27.d }, p8/z, [z0.d] ldnt1b { z27.d }, p8/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnt1b { z27.d }, p8/z, [z0.d] // CHECK-NEXT: ldnt1b { z27.d }, p8/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnt1b { }, p0/z, [z0.d] ldnt1b { }, p0/z, [z0.d]
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llvm/test/MC/AArch64/SVE2/ldnt1d-diagnostics.s

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// CHECK-NEXT: ldnt1d { z0.d }, p0/m, [z0.d] // CHECK-NEXT: ldnt1d { z0.d }, p0/m, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnt1d { z27.d }, p8/z, [z0.d] ldnt1d { z27.d }, p8/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnt1d { z27.d }, p8/z, [z0.d] // CHECK-NEXT: ldnt1d { z27.d }, p8/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnt1d { }, p0/z, [z0.d] ldnt1d { }, p0/z, [z0.d]
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llvm/test/MC/AArch64/SVE2/ldnt1h-diagnostics.s

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// CHECK-NEXT: ldnt1h { z0.d }, p0/m, [z0.d] // CHECK-NEXT: ldnt1h { z0.d }, p0/m, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnt1h { z27.d }, p8/z, [z0.d] ldnt1h { z27.d }, p8/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnt1h { z27.d }, p8/z, [z0.d] // CHECK-NEXT: ldnt1h { z27.d }, p8/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnt1h { }, p0/z, [z0.d] ldnt1h { }, p0/z, [z0.d]
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llvm/test/MC/AArch64/SVE2/ldnt1sb-diagnostics.s

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// CHECK-NEXT: ldnt1sb { z0.d }, p0/m, [z0.d] // CHECK-NEXT: ldnt1sb { z0.d }, p0/m, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnt1sb { z27.d }, p8/z, [z0.d] ldnt1sb { z27.d }, p8/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnt1sb { z27.d }, p8/z, [z0.d] // CHECK-NEXT: ldnt1sb { z27.d }, p8/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnt1sb { }, p0/z, [z0.d] ldnt1sb { }, p0/z, [z0.d]
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llvm/test/MC/AArch64/SVE2/ldnt1sh-diagnostics.s

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// CHECK-NEXT: ldnt1sh { z0.d }, p0/m, [z0.d] // CHECK-NEXT: ldnt1sh { z0.d }, p0/m, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnt1sh { z27.d }, p8/z, [z0.d] ldnt1sh { z27.d }, p8/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnt1sh { z27.d }, p8/z, [z0.d] // CHECK-NEXT: ldnt1sh { z27.d }, p8/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnt1sh { }, p0/z, [z0.d] ldnt1sh { }, p0/z, [z0.d]
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llvm/test/MC/AArch64/SVE2/ldnt1sw-diagnostics.s

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// CHECK-NEXT: ldnt1sw { z0.d }, p0/m, [z0.d] // CHECK-NEXT: ldnt1sw { z0.d }, p0/m, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnt1sw { z27.d }, p8/z, [z0.d] ldnt1sw { z27.d }, p8/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnt1sw { z27.d }, p8/z, [z0.d] // CHECK-NEXT: ldnt1sw { z27.d }, p8/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnt1sw { }, p0/z, [z0.d] ldnt1sw { }, p0/z, [z0.d]
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llvm/test/MC/AArch64/SVE2/ldnt1w-diagnostics.s

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// CHECK-NEXT: ldnt1w { z0.d }, p0/m, [z0.d] // CHECK-NEXT: ldnt1w { z0.d }, p0/m, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
ldnt1w { z27.d }, p8/z, [z0.d] ldnt1w { z27.d }, p8/z, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ldnt1w { z27.d }, p8/z, [z0.d] // CHECK-NEXT: ldnt1w { z27.d }, p8/z, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
ldnt1w { }, p0/z, [z0.d] ldnt1w { }, p0/z, [z0.d]
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llvm/test/MC/AArch64/SVE2/match-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate out of range. // Restricted predicate out of range.
match p0.b, p8/z, z0.b, z0.b match p0.b, p8/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: match p0.b, p8/z, z0.b, z0.b // CHECK-NEXT: match p0.b, p8/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid predicate operation // Invalid predicate operation
match p0.b, p0/m, z0.b, z0.b match p0.b, p0/m, z0.b, z0.b
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llvm/test/MC/AArch64/SVE2/nmatch-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Restricted predicate out of range. // Restricted predicate out of range.
nmatch p0.b, p8/z, z0.b, z0.b nmatch p0.b, p8/z, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: nmatch p0.b, p8/z, z0.b, z0.b // CHECK-NEXT: nmatch p0.b, p8/z, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid predicate operation // Invalid predicate operation
nmatch p0.b, p0/m, z0.b, z0.b nmatch p0.b, p0/m, z0.b, z0.b
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llvm/test/MC/AArch64/SVE2/sadalp-diagnostics.s

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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sadalp z0.d, p0/m, z1.d // CHECK-NEXT: sadalp z0.d, p0/m, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
sadalp z0.h, p8/m, z1.b sadalp z0.h, p8/m, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sadalp z0.h, p8/m, z1.b // CHECK-NEXT: sadalp z0.h, p8/m, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative movprfx tests // Negative movprfx tests
movprfx z31.s, p0/z, z6.s // element type of the source operand, rather than destination. movprfx z31.s, p0/z, z6.s // element type of the source operand, rather than destination.
sadalp z31.d, p0/m, z30.s sadalp z31.d, p0/m, z30.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size
// CHECK-NEXT: sadalp z31.d, p0/m, z30.s // CHECK-NEXT: sadalp z31.d, p0/m, z30.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/shadd-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
shadd z0.b, p0/z, z0.b, z1.b shadd z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: shadd z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: shadd z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shadd z0.b, p8/m, z0.b, z1.b shadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: shadd z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: shadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/shsub-diagnostics.s

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// Invalid predicate // Invalid predicate
shsub z0.b, p0/z, z0.b, z1.b shsub z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: shsub z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: shsub z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shsub z0.b, p8/m, z0.b, z1.b shsub z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: shsub z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: shsub z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/shsubr-diagnostics.s

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// Invalid predicate // Invalid predicate
shsubr z0.b, p0/z, z0.b, z1.b shsubr z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: shsubr z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: shsubr z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
shsubr z0.b, p8/m, z0.b, z1.b shsubr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: shsubr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: shsubr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/smaxp-diagnostics.s

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// Invalid predicate // Invalid predicate
smaxp z0.b, p0/z, z0.b, z1.b smaxp z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smaxp z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: smaxp z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smaxp z0.b, p8/m, z0.b, z1.b smaxp z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: smaxp z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: smaxp z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/sminp-diagnostics.s

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// Invalid predicate // Invalid predicate
sminp z0.b, p0/z, z0.b, z1.b sminp z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sminp z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: sminp z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sminp z0.b, p8/m, z0.b, z1.b sminp z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sminp z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: sminp z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/splice-diagnostics.s

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// CHECK-NEXT: splice z0.b, p0/m, { z1.b, z2.b } // CHECK-NEXT: splice z0.b, p0/m, { z1.b, z2.b }
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
splice z0.b, p8, { z1.b, z2.b } splice z0.b, p8, { z1.b, z2.b }
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: splice z0.b, p8, { z1.b, z2.b } // CHECK-NEXT: splice z0.b, p8, { z1.b, z2.b }
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx // Negative tests for instructions that are incompatible with movprfx
movprfx z31, z6 movprfx z31, z6
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llvm/test/MC/AArch64/SVE2/sqabs-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
sqabs z0.s, p0/z, z1.s sqabs z0.s, p0/z, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqabs z0.s, p0/z, z1.s // CHECK-NEXT: sqabs z0.s, p0/z, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqabs z0.s, p8/m, z1.s sqabs z0.s, p8/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sqabs z0.s, p8/m, z1.s // CHECK-NEXT: sqabs z0.s, p8/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
sqabs z0.b, p7/m, z1.s sqabs z0.b, p7/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqabs z0.b, p7/m, z1.s // CHECK-NEXT: sqabs z0.b, p7/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/sqadd-diagnostics.s

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// Invalid predicate // Invalid predicate
sqadd z0.b, p0/z, z0.b, z1.b sqadd z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqadd z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: sqadd z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqadd z0.b, p8/m, z0.b, z1.b sqadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sqadd z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: sqadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/sqneg-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
sqneg z0.s, p0/z, z1.s sqneg z0.s, p0/z, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqneg z0.s, p0/z, z1.s // CHECK-NEXT: sqneg z0.s, p0/z, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqneg z0.s, p8/m, z1.s sqneg z0.s, p8/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sqneg z0.s, p8/m, z1.s // CHECK-NEXT: sqneg z0.s, p8/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
sqneg z0.b, p7/m, z1.s sqneg z0.b, p7/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqneg z0.b, p7/m, z1.s // CHECK-NEXT: sqneg z0.b, p7/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/sqrshl-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
sqrshl z0.b, p0/z, z0.b, z1.b sqrshl z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrshl z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: sqrshl z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshl z0.b, p8/m, z0.b, z1.b sqrshl z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sqrshl z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: sqrshl z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/sqrshlr-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
sqrshlr z0.b, p0/z, z0.b, z1.b sqrshlr z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrshlr z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: sqrshlr z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshlr z0.b, p8/m, z0.b, z1.b sqrshlr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sqrshlr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: sqrshlr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/sqshl-diagnostics.s

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
// Invalid predicate // Invalid predicate
sqshl z0.b, p0/z, z0.b, z1.b sqshl z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqshl z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: sqshl z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshl z0.b, p8/m, z0.b, z1.b sqshl z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sqshl z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: sqshl z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshl z0.b, p8/m, z0.b, #0 sqshl z0.b, p8/m, z0.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sqshl z0.b, p8/m, z0.b, #0 // CHECK-NEXT: sqshl z0.b, p8/m, z0.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/sqshlr-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
sqshlr z0.b, p0/z, z0.b, z1.b sqshlr z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqshlr z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: sqshlr z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshlr z0.b, p8/m, z0.b, z1.b sqshlr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sqshlr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: sqshlr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/sqshlu-diagnostics.s

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
// Invalid predicate // Invalid predicate
sqshlu z0.b, p0/z, z0.b, #0 sqshlu z0.b, p0/z, z0.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqshlu z0.b, p0/z, z0.b, #0 // CHECK-NEXT: sqshlu z0.b, p0/z, z0.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqshlu z0.b, p8/m, z0.b, #0 sqshlu z0.b, p8/m, z0.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sqshlu z0.b, p8/m, z0.b, #0 // CHECK-NEXT: sqshlu z0.b, p8/m, z0.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/sqsub-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
sqsub z0.b, p0/z, z0.b, z1.b sqsub z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqsub z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: sqsub z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqsub z0.b, p8/m, z0.b, z1.b sqsub z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sqsub z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: sqsub z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/sqsubr-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
sqsubr z0.b, p0/z, z0.b, z1.b sqsubr z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqsubr z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: sqsubr z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqsubr z0.b, p8/m, z0.b, z1.b sqsubr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sqsubr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: sqsubr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/srhadd-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
srhadd z0.b, p0/z, z0.b, z1.b srhadd z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: srhadd z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: srhadd z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srhadd z0.b, p8/m, z0.b, z1.b srhadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: srhadd z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: srhadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/srshl-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
srshl z0.b, p0/z, z0.b, z1.b srshl z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: srshl z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: srshl z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srshl z0.b, p8/m, z0.b, z1.b srshl z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: srshl z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: srshl z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/srshlr-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
srshlr z0.b, p0/z, z0.b, z1.b srshlr z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: srshlr z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: srshlr z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srshlr z0.b, p8/m, z0.b, z1.b srshlr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: srshlr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: srshlr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/srshr-diagnostics.s

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
// Invalid predicate // Invalid predicate
srshr z0.b, p0/z, z0.b, #1 srshr z0.b, p0/z, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: srshr z0.b, p0/z, z0.b, #1 // CHECK-NEXT: srshr z0.b, p0/z, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
srshr z0.b, p8/m, z0.b, #1 srshr z0.b, p8/m, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: srshr z0.b, p8/m, z0.b, #1 // CHECK-NEXT: srshr z0.b, p8/m, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/stnt1b-diagnostics.s

Show All 36 Lines
// CHECK-NEXT: stnt1b { z0.d }, p0, [z0.d, z1.d] // CHECK-NEXT: stnt1b { z0.d }, p0, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
stnt1b { z27.d }, p8, [z0.d] stnt1b { z27.d }, p8, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: stnt1b { z27.d }, p8, [z0.d] // CHECK-NEXT: stnt1b { z27.d }, p8, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
stnt1b { }, p0, [z0.d] stnt1b { }, p0, [z0.d]
Show All 29 Lines

llvm/test/MC/AArch64/SVE2/stnt1d-diagnostics.s

Show All 36 Lines
// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, z1.d] // CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
stnt1d { z27.d }, p8, [z0.d] stnt1d { z27.d }, p8, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: stnt1d { z27.d }, p8, [z0.d] // CHECK-NEXT: stnt1d { z27.d }, p8, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
stnt1d { }, p0, [z0.d] stnt1d { }, p0, [z0.d]
Show All 29 Lines

llvm/test/MC/AArch64/SVE2/stnt1h-diagnostics.s

Show All 36 Lines
// CHECK-NEXT: stnt1h { z0.d }, p0, [z0.d, z1.d] // CHECK-NEXT: stnt1h { z0.d }, p0, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
stnt1h { z27.d }, p8, [z0.d] stnt1h { z27.d }, p8, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: stnt1h { z27.d }, p8, [z0.d] // CHECK-NEXT: stnt1h { z27.d }, p8, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
stnt1h { }, p0, [z0.d] stnt1h { }, p0, [z0.d]
Show All 29 Lines

llvm/test/MC/AArch64/SVE2/stnt1w-diagnostics.s

Show All 36 Lines
// CHECK-NEXT: stnt1w { z0.d }, p0, [z0.d, z1.d] // CHECK-NEXT: stnt1w { z0.d }, p0, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// restricted predicate has range [0, 7]. // restricted predicate has range [0, 7].
stnt1w { z27.d }, p8, [z0.d] stnt1w { z27.d }, p8, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: stnt1w { z27.d }, p8, [z0.d] // CHECK-NEXT: stnt1w { z27.d }, p8, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Invalid vector list. // Invalid vector list.
stnt1w { }, p0, [z0.d] stnt1w { }, p0, [z0.d]
Show All 29 Lines

llvm/test/MC/AArch64/SVE2/suqadd-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
suqadd z0.b, p0/z, z0.b, z1.b suqadd z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: suqadd z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: suqadd z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
suqadd z0.b, p8/m, z0.b, z1.b suqadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: suqadd z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: suqadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/uadalp-diagnostics.s

Show All 22 Lines
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uadalp z0.d, p0/m, z1.d // CHECK-NEXT: uadalp z0.d, p0/m, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Predicate not in restricted predicate range // Predicate not in restricted predicate range
uadalp z0.h, p8/m, z1.b uadalp z0.h, p8/m, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uadalp z0.h, p8/m, z1.b // CHECK-NEXT: uadalp z0.h, p8/m, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Negative movprfx tests // Negative movprfx tests
movprfx z31.s, p0/z, z6.s // element type of the source operand, rather than destination. movprfx z31.s, p0/z, z6.s // element type of the source operand, rather than destination.
uadalp z31.d, p0/m, z30.s uadalp z31.d, p0/m, z30.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size
// CHECK-NEXT: uadalp z31.d, p0/m, z30.s // CHECK-NEXT: uadalp z31.d, p0/m, z30.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/uhadd-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
uhadd z0.b, p0/z, z0.b, z1.b uhadd z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uhadd z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: uhadd z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uhadd z0.b, p8/m, z0.b, z1.b uhadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uhadd z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: uhadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/uhsub-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
uhsub z0.b, p0/z, z0.b, z1.b uhsub z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uhsub z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: uhsub z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uhsub z0.b, p8/m, z0.b, z1.b uhsub z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uhsub z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: uhsub z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/uhsubr-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
uhsubr z0.b, p0/z, z0.b, z1.b uhsubr z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uhsubr z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: uhsubr z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uhsubr z0.b, p8/m, z0.b, z1.b uhsubr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uhsubr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: uhsubr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/umaxp-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
umaxp z0.b, p0/z, z0.b, z1.b umaxp z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umaxp z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: umaxp z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umaxp z0.b, p8/m, z0.b, z1.b umaxp z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: umaxp z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: umaxp z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/uminp-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
uminp z0.b, p0/z, z0.b, z1.b uminp z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uminp z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: uminp z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uminp z0.b, p8/m, z0.b, z1.b uminp z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uminp z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: uminp z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/uqadd-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
uqadd z0.b, p0/z, z0.b, z1.b uqadd z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uqadd z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: uqadd z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqadd z0.b, p8/m, z0.b, z1.b uqadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uqadd z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: uqadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/uqrshl-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
uqrshl z0.b, p0/z, z0.b, z1.b uqrshl z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uqrshl z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: uqrshl z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshl z0.b, p8/m, z0.b, z1.b uqrshl z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uqrshl z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: uqrshl z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/uqrshlr-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
uqrshlr z0.b, p0/z, z0.b, z1.b uqrshlr z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uqrshlr z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: uqrshlr z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshlr z0.b, p8/m, z0.b, z1.b uqrshlr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uqrshlr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: uqrshlr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/uqshl-diagnostics.s

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
// Invalid predicate // Invalid predicate
uqshl z0.b, p0/z, z0.b, z1.b uqshl z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uqshl z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: uqshl z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshl z0.b, p8/m, z0.b, z1.b uqshl z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uqshl z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: uqshl z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshl z0.b, p8/m, z0.b, #0 uqshl z0.b, p8/m, z0.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uqshl z0.b, p8/m, z0.b, #0 // CHECK-NEXT: uqshl z0.b, p8/m, z0.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/uqshlr-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
uqshlr z0.b, p0/z, z0.b, z1.b uqshlr z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uqshlr z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: uqshlr z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqshlr z0.b, p8/m, z0.b, z1.b uqshlr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uqshlr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: uqshlr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/uqsub-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
uqsub z0.b, p0/z, z0.b, z1.b uqsub z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uqsub z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: uqsub z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqsub z0.b, p8/m, z0.b, z1.b uqsub z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uqsub z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: uqsub z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/uqsubr-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
uqsubr z0.b, p0/z, z0.b, z1.b uqsubr z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uqsubr z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: uqsubr z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqsubr z0.b, p8/m, z0.b, z1.b uqsubr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uqsubr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: uqsubr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/urecpe-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
urecpe z0.s, p0/z, z1.s urecpe z0.s, p0/z, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: urecpe z0.s, p0/z, z1.s // CHECK-NEXT: urecpe z0.s, p0/z, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urecpe z0.s, p8/m, z1.s urecpe z0.s, p8/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: urecpe z0.s, p8/m, z1.s // CHECK-NEXT: urecpe z0.s, p8/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
urecpe z0.b, p7/m, z1.b urecpe z0.b, p7/m, z1.b
Show All 13 Lines

llvm/test/MC/AArch64/SVE2/urhadd-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
urhadd z0.b, p0/z, z0.b, z1.b urhadd z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: urhadd z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: urhadd z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urhadd z0.b, p8/m, z0.b, z1.b urhadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: urhadd z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: urhadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/urshl-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
urshl z0.b, p0/z, z0.b, z1.b urshl z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: urshl z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: urshl z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urshl z0.b, p8/m, z0.b, z1.b urshl z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: urshl z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: urshl z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/urshlr-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
urshlr z0.b, p0/z, z0.b, z1.b urshlr z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: urshlr z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: urshlr z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urshlr z0.b, p8/m, z0.b, z1.b urshlr z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: urshlr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: urshlr z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/urshr-diagnostics.s

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
// Invalid predicate // Invalid predicate
urshr z0.b, p0/z, z0.b, #1 urshr z0.b, p0/z, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: urshr z0.b, p0/z, z0.b, #1 // CHECK-NEXT: urshr z0.b, p0/z, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urshr z0.b, p8/m, z0.b, #1 urshr z0.b, p8/m, z0.b, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: urshr z0.b, p8/m, z0.b, #1 // CHECK-NEXT: urshr z0.b, p8/m, z0.b, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2/ursqrte-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid predicate // Invalid predicate
ursqrte z0.s, p0/z, z1.s ursqrte z0.s, p0/z, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ursqrte z0.s, p0/z, z1.s // CHECK-NEXT: ursqrte z0.s, p0/z, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ursqrte z0.s, p8/m, z1.s ursqrte z0.s, p8/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ursqrte z0.s, p8/m, z1.s // CHECK-NEXT: ursqrte z0.s, p8/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid element width // Invalid element width
ursqrte z0.b, p7/m, z1.b ursqrte z0.b, p7/m, z1.b
Show All 13 Lines

llvm/test/MC/AArch64/SVE2/usqadd-diagnostics.s

Show All 26 Lines
// Invalid predicate // Invalid predicate
usqadd z0.b, p0/z, z0.b, z1.b usqadd z0.b, p0/z, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: usqadd z0.b, p0/z, z0.b, z1.b // CHECK-NEXT: usqadd z0.b, p0/z, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usqadd z0.b, p8/m, z0.b, z1.b usqadd z0.b, p8/m, z0.b, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: usqadd z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: usqadd z0.b, p8/m, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: