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[AMDGPU] Fix the mis-handling of `vreg_1` copied from scalar register.
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Authored by hliao on May 27 2019, 11:28 AM.

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Summary
  • Don't treat the use of a scalar register as vreg_1 an VGPR usage. Otherwise, that promotes that scalar register into vector one, which breaks the assumption that scalar register holds the lane mask.
  • The issue is triggered in a complicated case, where if the uses of that (lane mask) scalar register is legalized firstly before its definition, e.g., due to the mismatch block placement and its topological order or loop. In that cases, the legalization of PHI introduces the use of that scalar register as vreg_1.

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rL LLVM

Event Timeline

hliao created this revision.May 27 2019, 11:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 27 2019, 11:28 AM
This revision is now accepted and ready to land.May 28 2019, 9:03 AM
arsenm added inline comments.May 28 2019, 9:08 AM
llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
23 ↗(On Diff #201556)

Test name should be more specific. Also could use a comment about what it's testing

This revision was automatically updated to reflect the committed changes.